TWI436461B - Package substrate structure and flip-chip package structure and methods of fabricating the same - Google Patents

Description

Package substrate structure, preparation method thereof and flip chip package structure and preparation method thereof

The present invention relates to a package structure and a method for manufacturing the same, and more particularly to a package substrate structure having a fine line pitch layout, a method for manufacturing the same, a flip chip package structure, and a method for fabricating the same.

With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. At present, a package substrate for carrying a semiconductor wafer includes a wire-bonded package substrate, a chip-scale package (CSP) substrate, and a flip-chip substrate (FCBGA); and is required for operation of a microprocessor, a wafer set, and a graphics chip. Packaged substrates with wiring also need to improve the quality of the transmitted chip signals, improve the bandwidth, control impedance and other functions in order to cope with the development of high I / O number of packages.

In the current flip chip technology, a semiconductor wafer is electrically connected to a package substrate, and an electronic pad is disposed on a surface of the semiconductor integrated circuit (IC) chip, and the package substrate has a corresponding electric power. a soldering pad, and a solder bump or other conductive adhesive material may be appropriately disposed between the semiconductor wafer and the package substrate, so that the semiconductor wafer is disposed on the package substrate with the electrical contact surface facing downward to Solder bumps or conductive adhesive materials electrically connect the semiconductor wafer to the package substrate, and fill an underfill resin between the semiconductor wafer and the package substrate to reduce the between the semiconductor wafer and the package substrate by the underfill Thermal stress due to differences in thermal expansion. The manufacturing method of the conventional flip chip package structure is shown in Figures 1A to 1E.

First, as shown in FIG. 1A, a substrate body 10 having at least one surface 10a is provided, a wiring layer 11 is formed on the surface 10a of the substrate body 10, and the circuit layer 11 has a plurality of electrical contact pads 112.

As shown in FIG. 1B, a solder resist layer 12 is formed on the surface 10a and the circuit layer 11, and a plurality of openings 120 are formed in the solder resist layer 12, so that the respective electrical contact pads 112 are correspondingly exposed to the respective openings. In the hole 120.

As shown in FIG. 1C, a pre-solder 14 is then formed on the electrical contact pads 112 in each of the openings 120.

As shown in FIG. 1D, after the pre-solder 14 on the substrate body 10 is reflowed and leveled to form solder bumps 14a of uniform height, a semiconductor wafer 15 having a plurality of electrode bumps 151 is attached.

Finally, as shown in FIG. 1E, a reflow process is performed such that the solder bumps 14a cover the electrode bumps 151 to form the conductive bumps 155, and the underfill 16 is filled between the substrate body 10 and the semiconductor wafer 15. Thereby, the thermal stress generated by the difference in thermal expansion between the semiconductor wafer 15 and the package substrate 10 is reduced.

However, in the flip chip packaging process described above, in the fine pitch layout of the high-density wiring, for example, the distance between the solder bumps 14a is less than 100 μm, the alignment accuracy is less than 10 μm, and the solder resist layer 12 is opened. The hole 120 has a hole diameter of 50 μm or less, which is liable to cause alignment and difficulty in forming the opening 120 of the solder resist layer 12, and also increases the cost of the process equipment.

Moreover, in the fine pitch layout, the opening 120 of the solder resist layer 12 is often small, so that the pre-solder 14 is not easily filled into the opening 120; and the spacing of the electrical contact pads 112 is narrow, resulting in The pitch of the opening 120 is narrow, and the solder bump 14a is easily overflowed in the reflow process to cause a bridge phenomenon, causing the electrical conduction to be short-circuited.

Moreover, the conventional flip chip method is to form a highly uniform solder bump 14a after the solder pre-solder 14 on the single substrate body 10 is reflowed and leveled, and then a semiconductor having a plurality of electrode bumps 151 is attached. The wafer 15 is subjected to a subsequent process; wherein the plate having the plurality of substrate bodies 10 has poor flatness, and it is difficult to form a solder bump 14a of uniform height for large-panel packaging, so that the conventional flip-chip package structure can only be performed. Single package, which consumes process steps and costs.

In addition, the underfill 16 must be filled between the substrate body 10 and the semiconductor wafer 15, and in the fine pitch process, the solder bumps 14a are reduced due to the narrowing of the pitch, resulting in conductive formation after reflow. The height of the bump 155 is also reduced, so that the distance between the semiconductor wafer 15 and the solder resist layer 12 of the substrate body 10 is shortened, so that the interval between the semiconductor wafer 15 and the solder resist layer 12 is narrow, so that the underfill is filled. 16 is not easy to flow into the fill, and is prone to voids, which is prone to reliability problems in subsequent processes.

Therefore, how to provide a package substrate, a flip chip package and a method for manufacturing the same, in order to overcome the difficulty of performing alignment of a line, forming a hole of a solder resist layer, and filling a hole with a pre-solder in a fine pitch layout of high-density wiring It can avoid the defects such as solder bump bridging short circuit and bottom filling not easy to be filled in the reflow process, which has become an urgent problem to be overcome in the industry.

In view of the above-mentioned shortcomings of the prior art, the main object of the present invention is to provide a package substrate structure, a method for manufacturing the same, a flip chip package structure and a method for fabricating the same, which can effectively overcome the alignment of the line in the fine line process and form the opening of the solder resist layer. The difficulty of filling the openings with the pre-solder and eliminating the lack of bridging shorts in the reflow process.

To achieve the above and other objects, the present invention provides a package substrate structure, comprising: a substrate body having a first surface; a first circuit layer formed on the first surface and having a plurality of electrical contact pads; and insulation The film is formed on the substrate body and the first circuit layer, and a plurality of first openings are formed, so that the electrical contact pads are exposed to the first openings, and the thickness of the insulating film is lower than a thickness of the first circuit layer; a first solder resist layer is formed on the insulating film, and an opening is formed in the first solder resist layer, so that a portion of the insulating film and the electrical contact pads are exposed at the opening And an anisotropic conductive paste formed on the insulating film and the electrical contact pad in the opening of the first solder resist layer.

The present invention provides a flip chip package structure, comprising: a substrate body having a first surface, a first circuit layer formed on the first surface, and the first circuit layer has a plurality of electrical contact pads; an insulating film, Forming on the substrate body and the first circuit layer, and forming a plurality of first openings, wherein the electrical contact pads are correspondingly exposed to the first openings, and the thickness of the insulating film is lower than the first a thickness of a circuit layer; a first solder resist layer is formed on the insulating film, and an opening is formed in the first solder resist layer to expose a portion of the insulating film and the electrical contact pads to the opening; a surface treatment layer corresponding to an electrical contact pad formed in each of the first openings; an anisotropic conductive paste formed on the insulating film and the electrical contact pad in the opening of the first solder resist layer; and a semiconductor The wafer is pressed onto the anisotropic conductive paste and has a plurality of electrode bumps corresponding to the electrical contact pads to make the difference between the electrode bumps and the electrical contact pads The square conductive adhesive forms a conductive path, The bump electrodes by electrically conductive paths are formed of the anisotropic conductive adhesive is electrically connected to the contact pad.

According to the package substrate structure and the flip chip package structure, the electrode bump can be pressed onto the anisotropic conductive paste, or the electrode bump can be embedded in the anisotropic conductive paste after being pressed. .

According to the above package substrate structure and flip chip package structure, the surface treatment layer is further included on the electrical contact pads formed in each of the first openings, and the material forming the surface treatment layer is selected from electroless nickel plating/ One of a group consisting of gold, nickel immersion gold, nickel-palladium immersion gold, electroless tin plating, and organic solder retention.

In addition, according to the package substrate structure and the flip chip package structure described above, the substrate body has a second surface opposite to the first surface and a second circuit layer formed on the second surface, the second circuit layer having a plurality of ball-forming pads; the package structure further comprising a second solder mask formed on the second surface and the second circuit layer, wherein the second solder mask forms a plurality of second openings, so that the ball The pads are correspondingly exposed to each of the second openings.

The invention further provides a method for fabricating a package substrate structure, comprising: providing a substrate body having a first surface, forming a first circuit layer on the first surface of the substrate body, and the first circuit layer has a plurality of electrical properties a contact pad; an insulating film is formed on the first surface and the first circuit layer, and the thickness of the insulating film is lower than a thickness of the first circuit layer, and the insulating film forms a plurality of first openings, so that the electricity The first contact layer is formed on the insulating film, and an opening is formed in the first solder resist layer to expose a portion of the insulating film and the electrical contact pads. And forming an anisotropic conductive paste on the insulating film in the opening of the first solder resist layer and the electrical contact pads in each of the first openings.

The invention provides a method for fabricating a flip chip package structure, comprising: providing a substrate body having a first surface, forming a first circuit layer on the first surface of the substrate body, and the first circuit layer has a plurality of electricity a contact pad; an insulating film is formed on the first surface and the first circuit layer, and the thickness of the insulating film is lower than the thickness of the first circuit layer, and a plurality of first openings are formed in the insulating film, so that The electrical contact pad is exposed to each of the first openings; a first solder resist layer is formed on the insulating film, and an opening is formed in the first solder resist layer to partially seal the insulating film and the electrical contacts a pad is exposed in the opening; an anisotropic conductive paste is formed on the insulating film in the opening of the first solder resist layer and the electrical contact pads in each of the first openings; and pressing on the anisotropic conductive paste a semiconductor wafer having a plurality of electrode bumps, such that the electrode bumps correspond to the respective electrical contact pads, so that the anisotropic conductive paste between the electrode bumps and the electrical contact pads forms a conductive path. Making the electrode bump Electrically conductive paths formed by the anisotropic conductive adhesive is electrically connected to the contact pad.

According to the package substrate structure and the flip chip package structure and the method for manufacturing the same, the electrode bump can be pressed onto the anisotropic conductive paste, or the electrode bump can be embedded in the anisotropy after being pressed. In conductive adhesive.

According to the above package substrate structure, the method for manufacturing the same, the flip chip package structure and the method for manufacturing the same, the surface treatment layer is formed on the electrical contact pads in each of the first openings, and the material forming the surface treatment layer is optional. One of a group consisting of electroless nickel/gold, nickel immersion gold, nickel-palladium immersion gold, electroless tin plating, and organic solder retention.

According to the package substrate structure and the flip chip package structure and the manufacturing method thereof, the substrate body has a second surface corresponding to the first surface, and a second circuit layer is formed on the second surface, the second line The layer has a plurality of ball-forming pads, and a second solder resist layer is formed on the second surface and the second circuit layer, and a plurality of second openings are formed in the second solder resist layer, so that the ball-forming pads correspond to Exposed to each of the second openings.

The package substrate structure of the present invention, the method for fabricating the same, and the method for manufacturing the same are mainly for forming an insulating film on the first surface of the substrate body and the first circuit layer, and forming a plurality of first openings in the insulating film. a hole corresponding to exposing the electrical contact pads of each of the first circuit layers, and then forming a first solder resist layer on the insulating film, and an opening is formed in the first solder resist layer to expose a portion of the insulating film and the An electrical contact pad, forming a surface treatment layer on the electrical contact pad, forming an anisotropic conductive paste on the insulating film and the surface treatment layer in the opening of the first solder resist layer, and then pressing the semiconductor wafer to the semiconductor wafer On the anisotropic conductive paste, the electrode bumps of the semiconductor wafer are pressed against the electrical contact pads of the substrate body, and a conductive path is formed in the anisotropic conductive paste, so that the electrode bumps are electrically conductive. The via is electrically connected to the electrical contact pad.

As can be seen from the above, the present invention can effectively overcome the difficulties of conventional alignment, formation of solder mask opening and pre-solder filling in the fine pitch layout, and can avoid soldering in the conventional reflow process. Further, the thickness of the bump bridge is short; further, the thickness of the insulating film is lower than the thickness of the first circuit layer, and the thickness of the solder resist layer is higher than that of the conventional circuit layer, thereby providing a sufficient height difference (high circuit layer) In the insulating film), the anisotropic conductive paste is easily dispersed after being filled, and the electrical contact pads of the substrate body are effectively coated without causing voids, and the electrode bumps of the semiconductor wafer are correspondingly pressed to the The anisotropic conductive adhesive or embedded in the anisotropic conductive adhesive can effectively avoid the problem that the underfill is easy to generate voids, thereby avoiding the reliability problem in the subsequent process.

Moreover, compared with the prior art, the present invention does not require a solder material, and does not need to form a highly uniform solder bump. The surface of the substrate body is covered by the anisotropic conductive adhesive to cover the electrical contact pad. And pressing a plurality of semiconductor wafers on the anisotropic conductive paste to simultaneously face the plates on the plurality of substrate bodies, so that the electrode bumps of the wafers correspond to the electrical contact pads of the substrate body. Large-area panel packaging saves process steps and costs; in addition, it can be packaged in a single package depending on the actual process requirements.

In addition, the present invention utilizes the anisotropic conductive paste as a conductive member, and the solder bump is not required to be soldered to form a conductive bump without conventional solder reflow, and the present invention does not require the use of solder bumps. The higher electrode bumps are not formed, and the thickness of the overall package structure is effectively reduced.

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure herein.

Please refer to FIGS. 2A to 2E , which are schematic diagrams of the package substrate structure, the manufacturing method thereof and the flip chip package structure and the manufacturing method thereof.

As shown in FIG. 2A, a substrate body 20 having an inner layer line (not shown) having a corresponding first surface 20a and a second surface 20b is provided on the first surface 20a of the substrate body 20. The first circuit layer 21a and the second circuit layer 21b are respectively formed on the second surface 20b, and the conductive vias (not shown in the drawing) and the conductive blind holes are formed by the inner layer lines in the substrate body 20. The first circuit layer 21a is electrically connected to the second circuit layer 21b, and the first circuit layer 21a has a plurality of electrical contact pads 211, and the second circuit layer 21b has a plurality of ball pads. 212.

As shown in FIG. 2B, an insulating film 22 is formed on the first surface 20a and the first circuit layer 21a, and a plurality of first openings 220 are formed in the insulating film 22, so that the electrical contact pads 211 are correspondingly exposed. Each of the first openings 220 and the thickness of the insulating film 22 is lower than the thickness of the first circuit layer 21a; wherein the thickness of the insulating film 22 is 0.1 to 5 μm; in addition, the insulating film 22 is high. Made of molecular materials.

As shown in FIG. 2C, a first solder resist layer 23a is formed on the insulating film 22, and an opening 230a is formed in the first solder resist layer 23a to expose a portion of the insulating film 22 and the electrical contact pads 211. Forming a second solder resist layer 23b on the second surface 20b and the second circuit layer 21b, and forming a plurality of second openings 230b in the second solder resist layer 23b, so that the ball pad 212 is correspondingly exposed to each of the second openings 230b.

As shown in FIG. 2D, a surface treatment layer 24 is formed on the electrical contact pads 211 in each of the first openings 220 of the insulating film 22; wherein the material forming the surface treatment layer 24 is selected from electroless nickel plating / Gold (Ni/Au, which forms nickel first, then gold), Electroless Ni & Immersion Gold (ENIG), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), One of a group of electroless tin plating (Immersion Tin) and organic solder resist (OSP); the present invention does not require the use of conductive bumps compared to the prior art, and thus has a lower height than conventional structures.

As shown in FIG. 2E, an anisotropic conductive film (Anisotropic Conductive Film) is formed on the insulating film 22 in the opening 230a of the first solder resist layer 23a and the electrical contact pads 211 in each of the first openings 220. ACF) 26.

The thickness of the insulating film 22 of the present invention is lower than the thickness of the first circuit layer 21a, and the present invention can provide a sufficient height difference (the first circuit layer 21a) compared to the structure in which the thickness of the conventional solder resist layer is higher than that of the circuit layer. Above the insulating film 22), the anisotropic conductive paste 26 is easily dispersed after being filled, and the electrical contact pads 211 of the substrate body 20 are effectively coated to avoid voids.

The anisotropic conductive adhesive (ACF, commonly known as the hetero-conducting conductive film) 26 is mainly composed of a binder and conductive particles, which can provide two kinds of bonding objects for electrical conduction only in a single direction. In the embodiment, it is electrically conductive in the vertical direction and has an insulating effect in the horizontal direction.

The present invention provides a package substrate structure, comprising: a substrate body 20 having a first surface 20a; a first circuit layer 21a formed on the first surface 20a and having a plurality of electrical contact pads 211; 22, formed on the first surface 20a of the substrate body 20 and the first circuit layer 21a, and a plurality of first openings 220 are formed, so that the electrical contact pads 211 are correspondingly exposed to the first openings 220, The thickness of the insulating film 22 is lower than the thickness of the first circuit layer 21a. The first solder resist layer 23a is formed on the insulating film 22, and the opening 230a is formed in the first solder resist layer 23a. The insulating film 22 and the electrical contact pads 211 are exposed in the opening 230a; and the anisotropic conductive paste 26 is an insulating film 22 and an electrical contact pad formed in the opening 230a of the first solder resist layer 23a. The surface treatment layer 24 is formed between the electrical contact pad 211 and the anisotropic conductive paste 26.

According to the above package substrate structure, the material for forming the surface treatment layer 24 is selected from the group consisting of electroless nickel/gold (Ni/Au), nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), and electroless tin plating ( One of a group of Immersion Tin) and Organic Soldering Agent (OSP).

According to the above, the substrate body 20 has a second surface 20b opposite to the first surface 20a, and a second circuit layer 21b is formed on the second surface 20b. The second circuit layer 21b has a plurality of ball pads. The package substrate structure further includes a second solder resist layer 23b formed on the second surface 20b and the second circuit layer 21b, and the second solder resist layer 23b forms a plurality of second openings 230b, so that the implants The ball pad 212 is correspondingly exposed to each of the second openings 230b.

Referring to FIGS. 3 and 3', an embodiment of a semiconductor wafer on a package substrate of the present invention; as shown, a semiconductor wafer 27 is laminated on the anisotropic conductive paste 26, the semiconductor wafer 27 having The plurality of electrode bumps 271 are disposed such that the electrode bumps 271 correspond to the respective electrical contact pads 211, so that the anisotropic conductive paste 26 between the electrode bumps 271 and the electrical contact pads 211 form a conductive path 260. The electrode bump 271 is electrically connected to the electrical contact pad 211 by the conductive via 260; wherein the electrode bump 271 of the semiconductor wafer 27 is pressed against the anisotropic conductive paste 26, as shown in FIG. Alternatively, or as shown in FIG. 3', the electrode bump 271 is embedded in the anisotropic conductive paste 26 after being pressed.

The present invention does not need to use a solder material, and it is not necessary to form a highly uniform solder bump. The first surface 20a of the substrate body 20 is covered by the anisotropic conductive paste 26 to cover each of the electrical contact pads 211. Then, a plurality of semiconductor wafers 27 are pressed onto the anisotropic conductive paste 26, and the plates of the plurality of substrate bodies 20 are simultaneously aligned, so that the electrode bumps 271 of the semiconductor wafers 27 are accurate. Corresponding to each of the electrical contact pads 211 of the substrate body 20, a large panel package can be performed, which saves process steps and costs, and can also be packaged in a single package according to actual process requirements.

According to the present invention, the anisotropic conductive paste 26 is used as a conductive member, and the solder bump is not required to be soldered to form a conductive bump, so that the semiconductor wafer 27 of the present invention does not need to be used. The high electrode bumps effectively reduce the thickness of the overall package structure.

The present invention further provides a flip chip package structure, comprising: a substrate body 20 having a first surface 20a, a first circuit layer 21a formed on the first surface 20a, and the first circuit layer 21a having a plurality of electrical contacts The insulating film 22 is formed on the substrate body 20 and the first circuit layer 21a, and a plurality of first openings 220 are formed, and the electrical contact pads 211 are exposed to the first openings 220. The thickness of the insulating film 22 is lower than the thickness of the first circuit layer 21a; the first solder resist layer 23a is formed on the insulating film 22, and the opening 230a is formed in the first solder resist layer 23a. A portion of the insulating film 22 and the electrical contact pads 212 are exposed to the opening 230a; the surface treatment layer 24 is corresponding to the electrical contact pads 211 formed in each of the first openings 220; the anisotropic conductive adhesive 26, formed on the insulating film 22 and the surface treatment layer 24 in the opening 230a of the first solder resist layer 23a; the semiconductor wafer 27 is press-bonded to the anisotropic conductive paste 26 and has a plurality of electrode bumps 271, and each of the electrode bumps 271 corresponds to each of the electrical contact pads 211 The anisotropic conductive paste 26 between the electrode bumps 271 and the electrical contact pads 211 forms a conductive via 260, such that the electrode bumps 271 are electrically connected to the electrical contact pads 211 through the conductive vias 260; The electrode bump 271 is pressed onto the anisotropic conductive paste 26 or embedded in the anisotropic conductive layer 26.

According to the above flip chip package structure, the material for forming the surface treatment layer 24 is selected from the group consisting of electroless nickel/gold (Ni/Au), nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), and electroless tin plating. One of a group of (Immersion Tin) and Organic Preservative (OSP).

According to the above, the substrate body 20 has a second surface 20b opposite to the first surface 20a, and a second circuit layer 21b is formed on the second surface 20b. The second circuit layer 21b has a plurality of ball pads. The package substrate structure includes a solder resist layer 23 formed on the second surface 20b and the second circuit layer 21b, and a plurality of second openings 230 are formed in the solder resist layer 23, so that the ball bump 212 corresponds to Exposed to each of the second openings 230.

The present invention is characterized in that the first surface 20a of the substrate body 20 and the first circuit layer 21a are first formed with an insulating film 22, and a plurality of first openings are formed in the insulating film 22. 220, correspondingly exposing each of the electrical contact pads 211, then forming a surface treatment layer 24 on the electrical contact pads 211, and forming an anisotropic conductive paste 26 on the insulating film 22 and the electrical contact pads 211, and then The semiconductor wafer 27 is pressed onto the anisotropic conductive paste 26, and the electrode bumps 271 of the semiconductor wafer 27 are pressed against the electrical contact pads 211 of the substrate body 20, and the anisotropic conductive paste 26 is pressed. The conductive via 260 is formed to electrically connect the electrode bump 271 to the electrical contact pad 211 via the conductive via 260. In the fine pitch layout, it can effectively overcome the difficulties of conventional alignment, formation of solder mask opening and pre-solder filling, and can avoid solder bump bridging short circuit in the conventional reflow process. Missing.

Furthermore, the electrical contact pads 211 of the substrate body 20 are covered by the anisotropic conductive paste 26, and the electrode bumps 271 of the semiconductor wafer 27 are correspondingly pressed onto the anisotropic conductive paste 26 or embedded therein. In the anisotropic conductive adhesive 26, the crucible can effectively avoid the problem that the bottom filling is easy to generate voids, thereby avoiding the reliability problem generated in the subsequent process.

Moreover, in the present invention, the first surface 20a of the substrate body 20 is covered by the anisotropic conductive paste 26 to cover the respective electrical contact pads 211, and the plurality of semiconductor wafers 27 are pressed against the anisotropy. The conductive paste 26 enables the semiconductor wafers 27 to simultaneously align the plurality of substrate bodies 20 with the plurality of substrate bodies 20, so that the electrode bumps 271 of the semiconductor wafers 27 correspond to the electrical contact pads 211 of the substrate bodies 20, thereby It can be used for large-area panel packaging to save process steps and costs. In addition, it can be packaged in a single package according to actual process requirements.

The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.

10, 20. . . Substrate body

10a. . . surface

112, 211. . . Electrical contact pad

11. . . Circuit layer

12. . . Solder mask

120. . . Opening

14. . . Pre-solder

14a. . . Solder bump

15, 27. . . Semiconductor wafer

151, 271. . . Electrode bump

155‧‧‧Electrical bumps

16‧‧‧Bottom filling

20a‧‧‧ first surface

20b‧‧‧second surface

21a‧‧‧First circuit layer

21b‧‧‧Second circuit layer

212‧‧‧Ball mat

22‧‧‧Insulation film

220‧‧‧First opening

23a‧‧‧First solder mask

230a‧‧‧ openings

23b‧‧‧Second solder mask

230b‧‧‧second opening

24‧‧‧Surface treatment layer

26‧‧‧ anisotropic conductive adhesive

260‧‧‧Electrical path

1A to 1E are schematic cross-sectional views showing a conventional method for fabricating a flip chip package structure;

2A to 2E are schematic cross-sectional views showing the structure of the package substrate of the present invention and a method of manufacturing the same;

The third and third views are schematic cross-sectional views of the flip chip package structure of the present invention.

20. . . Substrate body

20a. . . First surface

20b. . . Second surface

21a. . . First circuit layer

211. . . Electrical contact pad

21b. . . Second circuit layer

212. . . Ball pad

twenty two. . . Insulating film

23a. . . First solder mask

230a. . . Opening

23b. . . Second solder mask

230b. . . Second opening

twenty four. . . Surface treatment layer

26. . . Anisotropic conductive adhesive

Claims (24)

The package substrate structure includes: a substrate body having a first surface and a second surface opposite to the first surface; a first circuit layer formed on the first surface and having a plurality of electrical contact pads; An insulating film is formed on the first surface of the substrate body and the first circuit layer, and is formed with a plurality of first openings, so that the electrical contact pads are exposed to the first openings, and the insulating film The thickness of the first circuit layer is lower than the thickness of the first circuit layer; the first solder resist layer is formed on the insulating film, and an opening is formed in the first solder resist layer to partially seal the insulating film and the electrical contacts The pad is exposed on the opening; the second circuit layer is formed on the second surface; and the anisotropic conductive adhesive is formed on the insulating film and the electrical contact pad in the opening of the first solder resist layer. The package substrate structure of claim 1, further comprising a surface treatment layer formed between the electrical contact pad and the anisotropic conductive paste. The package substrate structure of claim 2, wherein the material for forming the surface treatment layer is selected from the group consisting of electroless nickel/gold plating (Ni/Au, forming nickel first, then forming gold), and nickel immersion gold ( Electroless Ni & Immersion Gold, ENIG), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), Electroless Tin (Immersion Tin) and Organic Soldering Agent (OSP) One of the groups. The package substrate structure of claim 1, wherein the second circuit layer has a plurality of ball pads. The package substrate structure of claim 4, further comprising a second solder resist layer formed on the second surface and the second circuit layer, wherein the second solder resist layer forms a plurality of second openings, The ball-forming pads are correspondingly exposed to each of the second openings. A flip chip package structure includes: a substrate body having a first surface and a second surface opposite to the first surface, a first circuit layer formed on the first surface, and the first circuit layer has a plurality of a second contact layer is formed on the second surface; an insulating film is formed on the first surface of the substrate body and the first circuit layer, and a plurality of first openings are formed to make the electricity The contact pads are correspondingly exposed to the first openings, and the thickness of the insulating film is lower than the thickness of the first circuit layer; the first solder resist layer is formed on the insulating film, and the first solder resist is Forming an opening in the layer to expose a portion of the insulating film and the electrical contact pads to the opening; the anisotropic conductive adhesive is formed on the insulating film and the electrical contact pad in the opening of the first solder resist layer; And a semiconductor wafer bonded to the anisotropic conductive paste and having a plurality of electrode bumps corresponding to the electrical contact pads so as to be between the electrode bumps and the electrical contact pads Anisotropy The electro-glue forms a conductive path, and the electrode bump is electrically connected to the electrical contact pad by the conductive path formed by the anisotropic conductive paste. The flip chip package structure of claim 6 further comprises a surface treatment layer corresponding to the electrical contact pads formed in each of the first openings. The flip chip package structure of claim 7, wherein the material for forming the surface treatment layer is selected from the group consisting of electroless nickel/gold, nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), electroless plating. One of a group of tin (Immersion Tin) and organic solder resist (OSP). The flip chip package structure of claim 6, wherein the second circuit layer has a plurality of ball pads. The flip chip package structure of claim 9 further comprising a second solder resist layer formed on the second surface and the second circuit layer, wherein the second solder resist layer forms a plurality of second openings, The ball-forming pads are correspondingly exposed to each of the second openings. The flip chip package structure of claim 6, wherein the electrode bump is pressed against the anisotropic conductive paste. The flip-chip package structure of claim 6, wherein the electrode bump is embedded in the anisotropic conductive paste. A method for fabricating a package substrate structure includes: providing a substrate body having a first surface and a second surface opposite to the first surface, forming a first circuit layer on the first surface of the substrate body, and the first a circuit layer has a plurality of electrical contact pads, and a second circuit layer is formed on the second surface; Forming an insulating film on the first surface and the first circuit layer, and the thickness of the insulating film is lower than the thickness of the first circuit layer, and forming a plurality of first openings in the insulating film to make the electrical contacts The pad is correspondingly exposed to each of the first openings; a first solder resist layer is formed on the insulating film, and an opening is formed in the first solder resist layer, so that a portion of the insulating film and the electrical contact pads are exposed Opening; and forming an anisotropic conductive paste on the insulating film in the opening of the first solder resist layer and the electrical contact pads in each of the first openings. The method for manufacturing a package substrate structure according to claim 13 is characterized in that a surface treatment layer is formed on the electrical contact pads in each of the first openings. The method for manufacturing a package substrate structure according to claim 14, wherein the material for forming the surface treatment layer is selected from the group consisting of electroless nickel/gold, nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), and chemistry. One of a group of tin-plated (Immersion Tin) and organic solder resist (OSP). The method of fabricating a package substrate structure according to claim 13 , wherein the second circuit layer has a plurality of ball pads. The method for manufacturing a package substrate structure according to claim 16 , further comprising forming a second solder resist layer on the second surface and the second circuit layer, and forming a plurality of second openings in the second solder resist layer, The ball-forming pads are correspondingly exposed to each of the second openings. A method for manufacturing a flip chip package structure, comprising: Providing a substrate body having a first surface and a second surface opposite to the first surface, forming a first circuit layer on the first surface of the substrate body, and the first circuit layer has a plurality of electrical contact pads Forming a second circuit layer on the second surface; forming an insulating film on the first surface and the first circuit layer, and the thickness of the insulating film is lower than the thickness of the first circuit layer, and the insulating film is Forming a plurality of first openings, so that each of the electrical contact pads is exposed to each of the first openings; forming a first solder resist layer on the insulating film, and forming an opening in the first solder resist layer The insulating film and the electrical contact pads are exposed in the opening; the anisotropic conductive paste is formed on the insulating film in the opening of the first solder resist layer and the electrical contact pads in each of the first openings; Pressing the semiconductor wafer on the anisotropic conductive paste, the semiconductor wafer has a plurality of electrode bumps, and the electrode bumps correspond to the electrical contact pads to make the difference between the electrode bumps and the electrical contact pads The square conductive adhesive forms a conductive path, The bump electrodes by electrically conductive paths are formed of the anisotropic conductive adhesive is electrically connected to the contact pad. The method for manufacturing a flip chip package structure according to claim 18, comprising forming a surface treatment layer on the electrical contact pads in each of the first openings. The method for preparing a flip chip package structure according to claim 19, wherein the material for forming the surface treatment layer is selected from the group consisting of electroless nickel/gold plating, One of a group consisting of ENIG, ENEPIG, Immersion Tin, and Organic Soldering Agent (OSP). The method of fabricating a flip chip package structure according to claim 18, wherein the second circuit layer has a plurality of ball pads. The method for manufacturing a flip chip package structure according to claim 21, further comprising a second solder resist layer formed on the second surface and the second circuit layer, and forming a plurality of second openings in the second solder resist layer , the ball mats are correspondingly exposed to each of the second openings. The method of fabricating a flip chip package structure according to claim 18, wherein the electrode bump is pressed onto the anisotropic conductive paste. The method for manufacturing a flip chip package structure according to claim 18, wherein the electrode bump is embedded in the anisotropic conductive paste after being pressed.