CN202394947U - Single-base island embedded single-circle pin electrostatic discharge ring-passive device ball grid array packaging structure - Google Patents
Single-base island embedded single-circle pin electrostatic discharge ring-passive device ball grid array packaging structure Download PDFInfo
- Publication number
- CN202394947U CN202394947U CN2011204863257U CN201120486325U CN202394947U CN 202394947 U CN202394947 U CN 202394947U CN 2011204863257 U CN2011204863257 U CN 2011204863257U CN 201120486325 U CN201120486325 U CN 201120486325U CN 202394947 U CN202394947 U CN 202394947U
- Authority
- CN
- China
- Prior art keywords
- pin
- release ring
- static release
- passive device
- interior
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model relates to a single-base island embedded single-circle pin electrostatic discharge ring-passive device ball grid array packaging structure, comprising outer pins (1) and an outer electrostatic discharge ring (2), wherein an inner pin (4) is formed on the front face of each outer pin (1) in a multi-layer electroplating manner; a chip (6) is arranged inside the outer electrostatic discharge ring (2); the front face of the chip (6) is connected to the front face of the inner pin (4) by a metal wire (7); a passive device (12) is spanned between the inner pins (4); and tin balls (10) are arranged on the rear faces of the outer pin (1) and the outer electrostatic discharge ring (2). The single-base island embedded single-circle pin electrostatic discharge ring-passive device ball grid array packaging structure has the following advantages that: a high-temperature resistant coating on the rear face is omitted so that the packaging cost is reduced; the quality of the bonding of the metal wire and the stability of the reliability of the product are good; the binding power of the plastic package body and the metal pin is high; and the high-density capability of the inner pins is realized.
Description
Technical field
The utility model relates to the base island embedded individual pen pin of a kind of list static release ring passive device ball grid array package structure, belongs to the semiconductor packaging field.
Background technology
Traditional lead frame structure mainly contains two kinds:
First kind: after adopting metal substrate to carry out chemical etching and plating, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in Figure 3) that to carry out encapsulation process;
Second kind: employing is at first carried out chemistry at the back side of metal substrate and is etched partially; Again sealing of plastic packaging material carried out in the aforementioned zone that has etched partially through chemistry; The chemical etching of pin in afterwards the front of metal substrate being carried out; Carry out the plating on pin surface in the lead frame after the completion again, promptly accomplish the making (as shown in Figure 5) of lead frame.
And there has been following not enough point in above-mentioned two kinds of lead frames in encapsulation process:
First kind:
1, but the lead frame of this kind must stick the glued membrane of one deck costliness high temperature resistance because of the back side, so directly increased high cost;
2, but also because such a lead frame must be affixed on the back layer of high temperature of the film, during the packaging process so that the loading process can use conductive or non-conductive adhesive material, and can not be used completely eutectic solder process technology and for loading, so choose the types of products have greater limitations;
3, again because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; And in the metal wire bonding technology in encapsulation process; Because but the glued membrane of this high temperature resistance is a soft materials; So caused the instability of metal wire bonding parameter, seriously influenced the quality of metal wire bonding and the stability of production reliability;
4, again because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; And the plastic package process process in encapsulation process; Infiltrate plastic packaging material because the injecting glue pressure during plastic packaging is easy to cause between lead frame and the glued membrane, and be that the kenel of conduction is because infiltrated plastic packaging material and become insulation pin (as shown in Figure 4) on the contrary the former metal leg that should belong to.
Second kind:
1, because carried out the etching operation of secondary respectively, so increased the cost of operation operation more;
2, the composition of lead frame be metallics add epoxy resin material (plastic packaging material) thus at high temperature easily because the expansion of different material and shrinkage stress inequality, generation lead frame warpage issues;
3, also because the warpage of lead frame directly has influence on the precision of the device chip in the packaging process and thereby yield is produced in the smooth and easy influence of lead frame transport process;
4, also because the warpage of lead frame directly has influence on the aligning accuracy of the metal wire bonding in the packaging process and thereby yield is produced in the smooth and easy influence of lead frame transport process;
5, because the positive interior pin of lead frame is to adopt etched technology, must be so the pin of pin is wide in the etching greater than 100 μ m, and the gap of interior pin and interior pin also must be greater than 100 μ m, so difficult high density ability of accomplishing interior pin.
Summary of the invention
The purpose of the utility model is to overcome above-mentioned deficiency; The base island embedded individual pen pin of a kind of list static release ring passive device ball grid array package structure is provided, and it has saved the high temperature resistant glued membrane at the back side, has reduced packaging cost; Selectable product category is wide; The quality of metal wire bonding and the good stability of production reliability, the constraint ability of plastic-sealed body and metal leg is big, has realized the high density ability of interior pin.
The purpose of the utility model is achieved in that the base island embedded individual pen pin of a kind of list static release ring passive device ball grid array package structure; Be characterized in: it comprises outer pin and outer static release ring; Said outer pin front forms interior pin through the multilayer plating mode; Said outer static release ring front forms interior static release ring through the multilayer plating mode; Said outer static release ring set inside has chip; Be connected with metal wire between between said chip front side and the interior pin front and chip front side and the interior static release ring front; Cross-over connection has passive device between said interior pin and the interior pin, and said interior pin top and chip, metal wire and passive device are encapsulated with plastic packaging material outward, and zone between zone, outer static release ring and the outer pin of said outer pin periphery and the zone between outer pin and the outer pin all are equipped with gap filler; And expose outside the gap filler at the back side of outer pin and outer static release ring, the outer pin outside exposing gap filler and outside the back side of static release ring be provided with the tin ball.
The inner front of said outer static release ring forms interior Ji Dao through the multilayer plating mode, and basic island was positive in said chip was arranged at.
Said the first metal layer can adopt nickel, copper, nickel, palladium, five layers of metal level of gold or nickel, copper, silver-colored three-layer metal layer, perhaps other similar structures.With nickel, copper, nickel, palladium, five layers of metal level of gold is example; Wherein the ground floor nickel dam mainly plays the effect on anti-etching barrier layer; And middle copper layer, nickel dam and palladium layer mainly play a part to combine to increase, and outermost gold layer mainly plays the effect with the metal wire bonding.
Compared with prior art, the beneficial effect of the utility model is:
1, but the glued membrane of the expensive high temperature resistance of one deck need not sticked in the back side of this kind lead frame, so directly reduced high cost;
2, because but the glued membrane of one deck high temperature resistance need not sticked in the back side of this kind lead frame yet; So the technology in encapsulation process is except using conduction or nonconducting bonding material; Can also adopt the technology of eutectic technology and slicken solder to carry out load, so selectable kind is wider;
3,, guaranteed the stability of metal wire bonding parameter, guaranteed the stability of reliability of quality and the product of metal wire bonding again because but the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind;
, thereby in the technical process of encapsulation, can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material 4, again because but the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind;
5, because the fine rule electric plating method has been adopted in the front, so positive pin widths minimum can reach 25 μ m, and reach 25 μ m apart from minimum between interior pin and the interior pin, embody the high density ability of the interior pin of lead frame fully;
6, owing to used the plating mode and the back etched technology of positive interior pin; So can the pin in lead frame front be extended to as much as possible the next door of Ji Dao; Impel chip and pin distance significantly to shorten, so the cost of metal wire also can significantly reduce (the especially metal wire of expensive proof gold matter);
7, also because the shortening of metal wire makes the also speedup (especially the product of storage class and need the calculating of mass data more outstanding) significantly of signal output speed of chip; Because the length of metal wire has shortened, so also significantly reduce in the interference of the existing dead resistance of metal wire, parasitic capacitance and stray inductance to signal;
8, because of having used the plating elongation technology of interior pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin;
9, because volume after being encapsulated is significantly dwindled, more directly embody material cost and significantly descend, because the minimizing of material usage has also reduced environmental issue puzzlements such as discarded object significantly.
10, when the plastic-sealed body paster is to pcb board; Because of implanting or be coated with the tin ball in the position at plastic-sealed body pin and Ji Dao; It is big that spacing between the plastic-sealed body back side and the pcb board becomes, and especially the problem that causes tin fusion difficulty can not blown because of hot blast in the inner ring pin of plastic-sealed body or zone, basic island.
When if 11 plastic-sealed body pasters are not fine to pcb board, need do over again again heavily and to paste, because there are enough height at the tin cream place, cleaning agent cleans easily, maintenance easily behind the tin ball of burn-oning does not weld to take away like the tin ball and welds a ball again again behind the tin ball and get final product.
Description of drawings
Fig. 1 is the base island embedded individual pen pin of a kind of list of a utility model static release ring passive device ball grid array package structure sketch map.
Fig. 2 is the vertical view of Fig. 1.
Fig. 3 was not for there was the sketch map that high temperature resistant glued membrane is sticked at the pin lead frame back side on four sides in the past.
The sketch map of flash when the four sides that Fig. 4 sticks high temperature resistant glued membrane for the back side does not in the past have the pin leadframe package.
Fig. 5 was for sealed the structural representation of two-sided etched lead frame in the past in advance.
Wherein:
Outer static release ring 2
In basic island 3
Interior static release ring 5
Plastic packaging material 8
Conduction or non-conductive bonding material 9
Embodiment
Referring to Fig. 1, Fig. 2; The base island embedded individual pen pin of a kind of list of the utility model static release ring passive device ball grid array package structure; It comprises outer pin 1 and outer static release ring 2; Pin 4 in said outer pin 1 front forms through the multilayer plating mode; Static release ring 5 in said outer static release ring 2 fronts form through the multilayer plating mode; Said outer static release ring 2 inner positive form through the multilayer plating mode in basic island 3, basic island 3, interior pin 4 and interior static release ring 5 are referred to as the first metal layer in said, said in 3 fronts, basic island be provided with chip 6 through conduction or non-conductive bonding material 9; Said chip 6 positive with interior pin 4 fronts between and be connected with metal wire 7 between chip 6 fronts and the interior static release ring 5; Through conduction or 9 cross-over connections of non-conductive bonding material passive device 12 is arranged between pin 4 and the interior pin 4 in said, basic island 3, interior pin 4 and interior static release ring 5 tops and chip 6, metal wire 7 and the passive device 12 outer plastic packaging materials 8 that are encapsulated with in said, the zone between regional and outer pin 1 and the outer pin 1 between zone, outer static release ring 2 and the outer pin 1 of said outer pin 1 periphery all is equipped with gap filler 11; And expose outside the gap filler 11 at the back side of outer pin 1 and outer static release ring 2, the outer pin 1 outside exposing gap filler 11 and outside the back side of static release ring 2 be provided with tin ball 10.
Claims (2)
1. the base island embedded individual pen pin of list static release ring passive device ball grid array package structure; It is characterized in that: it comprises outer pin (1) and outer static release ring (2); Said outer pin (1) is positive to form interior pin (4) through the multilayer plating mode; Said outer static release ring (2) is positive to form interior static release ring (5) through the multilayer plating mode; Said outer static release ring (2) set inside has chip (6); Said chip (6) positive with interior pin (4) front between and be connected with metal wire (7) between chip (6) front and interior static release ring (5) front; Cross-over connection has passive device (12) between said interior pin (4) and the interior pin (4); The outer plastic packaging material (8) that is encapsulated with of pin (4) top and chip (6), metal wire (7) and passive device (12) in said; Zone between regional and outer pin (1) and the outer pin (1) between peripheral zone, outer static release ring (2) and the outer pin (1) of said outer pin (1) all is equipped with gap filler (11), and the back side of outer pin (1) and outer static release ring (2) exposes outside the gap filler (11), the outer pin (1) outside exposing gap filler (11) and outside the back side of static release ring (2) be provided with tin ball (10).
2. the base island embedded individual pen pin of a kind of list according to claim 1 static release ring passive device ball grid array package structure; It is characterized in that: the inner front of said outer static release ring (2) forms interior Ji Dao (3) through the multilayer plating mode, and said chip (6) is arranged at interior Ji Dao (3) front.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204863257U CN202394947U (en) | 2011-11-30 | 2011-11-30 | Single-base island embedded single-circle pin electrostatic discharge ring-passive device ball grid array packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204863257U CN202394947U (en) | 2011-11-30 | 2011-11-30 | Single-base island embedded single-circle pin electrostatic discharge ring-passive device ball grid array packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202394947U true CN202394947U (en) | 2012-08-22 |
Family
ID=46669852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011204863257U Expired - Lifetime CN202394947U (en) | 2011-11-30 | 2011-11-30 | Single-base island embedded single-circle pin electrostatic discharge ring-passive device ball grid array packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202394947U (en) |
-
2011
- 2011-11-30 CN CN2011204863257U patent/CN202394947U/en not_active Expired - Lifetime
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN202394869U (en) | Base-free chip repeater sphere gate matrix packaging structure | |
| CN202394868U (en) | Packaging structure of passive devices of single-base-island exposed type multi-circle pin electrostatic discharge rings | |
| CN202394873U (en) | Single-base-island exposure type single-circle-pin ball grid array packaging structure | |
| CN202394914U (en) | Multiple base island exposed single-circle pin and ball grid array packaging structure | |
| CN202394947U (en) | Single-base island embedded single-circle pin electrostatic discharge ring-passive device ball grid array packaging structure | |
| CN202394941U (en) | Single-base island embedded multi-circle pin electrostatic discharge ring-passive device ball grid array packaging structure | |
| CN202394940U (en) | Single-base island embedded multi-circle pin electrostatic discharge ring ball grid array packaging structure | |
| CN202394935U (en) | Multi-base island embedded multi-circle pin electrostatic discharge ring-passive device ball grid array packaging structure | |
| CN202394904U (en) | Single-base exposed single-loop-pin electrostatic discharge loop passive device packaging structure | |
| CN202394943U (en) | Multi-base island embedded single-circle pin electrostatic discharge ring ball grid array packaging structure | |
| CN202394880U (en) | Single-base island embedded single-circle pin ball grid array packaging structure | |
| CN202394938U (en) | Single-base island embedded multi-circle pin ball grid array packaging structure | |
| CN202394910U (en) | Non-base-island chip inversion ball grid array packaging structure | |
| CN202394879U (en) | Multi-base island embedded single-circle pin ball grid array packaging structure | |
| CN202394942U (en) | Multi-base island embedded multi-circle pin electrostatic discharge ring-passive device ball grid array packaging structure | |
| CN202394946U (en) | Single-island embedded single ring pin passive device ball grid array encapsulating structure | |
| CN202394945U (en) | Ball grid array packaging structure of single-base-island embedding single-circle pin electrostatic discharge rings | |
| CN202394915U (en) | Single base island exposed single-circle pin, passive device and ball grid array packaging structure | |
| CN202394878U (en) | Ball grid array packaging structure embedded with multiple base islands and provided with multi-ring pins and electrostatic release ring | |
| CN202394872U (en) | Single-base-island exposure type single-circle-pin electrostatic release ring ball grid array packaging structure | |
| CN202443966U (en) | Multi-base-island exposure type multi-circle-pin electrostatic release ring passive component ball grid array packaging structure | |
| CN202394922U (en) | Encapsulation structure for single-island reveal multi-ring pin ball grid array | |
| CN202394918U (en) | Single-base-island exposure type single-circle-pin electrostatic release ring passive component ball grid array packaging structure | |
| CN202394916U (en) | Encapsulation structure of multi-base-island exposed type single-circle pin static release ring passive device ball grid array | |
| CN202394920U (en) | multiple base island exposed single-circle pin, passive device and ball grid array packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170328 Address after: The 200127 Tianjin FTA test area (Dongjiang Bonded Port) No. 6865 North Road, 1-1-1802-7 financial and trade center of Asia Patentee after: Xin Xin finance leasing (Tianjin) Co., Ltd. Address before: 214434 Binjiang Middle Road, Jiangyin Development Zone, Jiangsu, China, No. 275, No. Patentee before: Jiangsu Changjiang Electronics Technology Co., Ltd. |
|
| TR01 | Transfer of patent right | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Jiangsu Changjiang Electronics Technology Co., Ltd. Assignor: Xin Xin finance leasing (Tianjin) Co., Ltd. Contract record no.: 2017320010028 Denomination of utility model: Single-base island embedded single-circle pin electrostatic discharge ring-passive device ball grid array packaging structure Granted publication date: 20120822 License type: Exclusive License Record date: 20170508 |
|
| EE01 | Entry into force of recordation of patent licensing contract | ||
| EC01 | Cancellation of recordation of patent licensing contract |
Assignee: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd. Assignor: Xin Xin finance leasing (Tianjin) Co., Ltd. Contract record no.: 2017320010028 Date of cancellation: 20200515 |
|
| EC01 | Cancellation of recordation of patent licensing contract | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200610 Address after: 214434, No. 78, mayor road, Chengjiang, Jiangsu, Jiangyin, Wuxi Patentee after: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 1-1-1802-7, North Zone, financial and Trade Center, No. 6865, Asia Road, Tianjin pilot free trade zone (Dongjiang Free Trade Port Area) Patentee before: Xin Xin finance leasing (Tianjin) Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120822 |
|
| CX01 | Expiry of patent term |