CN202394916U - Encapsulation structure of multi-base-island exposed type single-circle pin static release ring passive device ball grid array - Google Patents
Encapsulation structure of multi-base-island exposed type single-circle pin static release ring passive device ball grid array Download PDFInfo
- Publication number
- CN202394916U CN202394916U CN2011204738810U CN201120473881U CN202394916U CN 202394916 U CN202394916 U CN 202394916U CN 2011204738810 U CN2011204738810 U CN 2011204738810U CN 201120473881 U CN201120473881 U CN 201120473881U CN 202394916 U CN202394916 U CN 202394916U
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- China
- Prior art keywords
- pin
- release ring
- static release
- passive device
- dao
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- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
The utility model relates to an encapsulation structure of a multi-base-island exposed type single-circle pin static release ring passive device ball grid array. The encapsulation structure comprises a plurality of outer base islands (1), a circle of outer pins (2) and an outer static release ring (3), wherein the front of each outer pin (2) is provided with an inner pin (5) in a way of multilayer plating; the front of an inner base island (4) is provided with a chip (7); a passive device (13) is connected between every two adjacent inner pins (5) in a spanning way; and the backs of the outer base islands (1), the outer pins (2) and the outer static release ring (3) are respectively provided with a tin ball (11). The encapsulation structure has the beneficial effects that a high-temperature resistant glue film arranged at the back is omitted, so that the encapsulation cost is reduced; and the bonding quality of the metal wires and the stability of product reliability are good, the bonding capacity between a plastic package body and a metal leg is strong, and the high density capacity of the inner pins can be realized.
Description
Technical field
The utility model relates to a kind of how base island exposed individual pen pin static release ring passive device ball grid array package structure, belongs to the semiconductor packaging field.
Background technology
Traditional lead frame structure mainly contains two kinds:
First kind: after adopting metal substrate to carry out chemical etching and plating, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in Figure 2) that to carry out encapsulation process;
Second kind: employing is at first carried out chemistry at the back side of metal substrate and is etched partially; Again sealing of plastic packaging material carried out in the aforementioned zone that has etched partially through chemistry; The chemical etching of pin in afterwards the front of metal substrate being carried out; Carry out the plating on pin surface in the lead frame after the completion again, promptly accomplish the making (as shown in Figure 4) of lead frame.
And there has been following not enough point in above-mentioned two kinds of lead frames in encapsulation process:
First kind:
1, but the lead frame of this kind must stick the glued membrane of one deck costliness high temperature resistance because of the back side, so directly increased high cost;
2, also because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; So the load technology in encapsulation process can only be used conduction or non-conductive bonding material; And the technology that can not adopt eutectic technology and slicken solder is fully carried out load, so selectable product category just has bigger limitation;
3, again because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; And in the metal wire bonding technology in encapsulation process; Because but the glued membrane of this high temperature resistance is a soft materials; So caused the instability of metal wire bonding parameter, seriously influenced the quality of metal wire bonding and the stability of production reliability;
4, again because but the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind; And the plastic package process process in encapsulation process; Infiltrate plastic packaging material because the injecting glue pressure during plastic packaging is easy to cause between lead frame and the glued membrane, and be that the kenel of conduction is because infiltrated plastic packaging material and become insulation pin (as shown in Figure 3) on the contrary the former metal leg that should belong to.
Second kind:
1, because carried out the etching operation of secondary respectively, so increased the cost of operation operation more;
2, the composition of lead frame be metallics add epoxy resin material (plastic packaging material) thus at high temperature easily because the expansion of different material and shrinkage stress inequality, generation lead frame warpage issues;
3, also because the warpage of lead frame directly has influence on the precision of the device chip in the packaging process and thereby yield is produced in the smooth and easy influence of lead frame transport process;
4, also because the warpage of lead frame directly has influence on the aligning accuracy of the metal wire bonding in the packaging process and thereby yield is produced in the smooth and easy influence of lead frame transport process;
5, because the positive interior pin of lead frame is to adopt etched technology, must be so the pin of pin is wide in the etching greater than 100 μ m, and the gap of interior pin and interior pin also must be greater than 100 μ m, so difficult high density ability of accomplishing interior pin.
Summary of the invention
The purpose of the utility model is to overcome above-mentioned deficiency; A kind of how base island exposed individual pen pin static release ring passive device ball grid array package structure is provided, and it has saved the high temperature resistant glued membrane at the back side, has reduced packaging cost; Selectable product category is wide; The quality of metal wire bonding and the good stability of production reliability, the constraint ability of plastic-sealed body and metal leg is big, has realized the high density ability of interior pin.
The purpose of the utility model is achieved in that a kind of how base island exposed individual pen pin static release ring passive device ball grid array package structure; Be characterized in: it comprises outer Ji Dao, outer pin and outer static release ring; Said outer Ji Dao is provided with a plurality of; Said outer pin is provided with a circle; Said outer static release ring is arranged between outer Ji Dao and the outer pin, and said outer pin front forms interior pin through the multilayer plating mode, and said outer front, basic island is provided with chip; Be connected with metal wire between said chip front side and the interior pin front and between chip front side and the chip front side; Cross-over connection has passive device between said interior pin and the interior pin, and said interior pin top and chip, metal wire and passive device are encapsulated with plastic packaging material outward, and zone between zone, outer static release ring and the outer pin between zone, outer Ji Dao and the outer static release ring of said outer pin periphery and the zone between outer pin and the outer pin all are equipped with gap filler; And expose outside the gap filler at the back side of outer Ji Dao, outer pin and outer static release ring, the outer Ji Dao outside exposing gap filler, outer pin and outside the back side of static release ring be provided with the tin ball.
Said outer front, basic island forms interior Ji Dao through the multilayer plating mode, and basic island was positive in said chip was arranged at.
Said outer static release ring front forms interior static release ring through the multilayer plating mode.
Said the first metal layer can adopt nickel, copper, nickel, palladium, five layers of metal level of gold or nickel, copper, silver-colored three-layer metal layer, perhaps other similar structures.With nickel, copper, nickel, palladium, five layers of metal level of gold is example; Wherein the ground floor nickel dam mainly plays the effect on anti-etching barrier layer; And middle copper layer, nickel dam and palladium layer mainly play a part to combine to increase, and outermost gold layer mainly plays the effect with the metal wire bonding.
Compared with prior art, the beneficial effect of the utility model is:
1, but the glued membrane of the expensive high temperature resistance of one deck need not sticked in the back side of this kind lead frame, so directly reduced high cost;
2, because but the glued membrane of one deck high temperature resistance need not sticked in the back side of this kind lead frame yet; So the technology in encapsulation process is except using conduction or non-conductive bonding material; Can also adopt the technology of eutectic technology and slicken solder to carry out load, so selectable kind is wider;
3,, guaranteed the stability of metal wire bonding parameter, guaranteed the stability of reliability of quality and the product of metal wire bonding again because but the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind;
, thereby in the technical process of encapsulation, can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material 4, again because but the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind;
5, because the fine rule electric plating method has been adopted in the front, so positive pin widths minimum can reach 25 μ m, and reach 25 μ m apart from minimum between interior pin and the interior pin, embody the high density ability of the interior pin of lead frame fully;
6, owing to used the plating mode and the back etched technology of positive interior pin; So can the pin in lead frame front be extended to as much as possible the next door of Ji Dao; Impel chip and pin distance significantly to shorten, so the cost of metal wire also can significantly reduce (the especially metal wire of expensive proof gold matter);
7, also because the shortening of metal wire makes the also speedup (especially the product of storage class and need the calculating of mass data more outstanding) significantly of signal output speed of chip; Because the length of metal wire has shortened, so also significantly reduce in the interference of the existing dead resistance of metal wire, parasitic capacitance and stray inductance to signal;
8, because of having used the plating elongation technology of interior pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin;
9, because volume after being encapsulated is significantly dwindled, more directly embody material cost and significantly descend, because the minimizing of material usage has also reduced environmental issue puzzlements such as discarded object significantly.
10, when the plastic-sealed body paster is to pcb board; Because of implanting or be coated with the tin ball in the position at plastic-sealed body pin and Ji Dao; It is big that spacing between the plastic-sealed body back side and the pcb board becomes, and especially the problem that causes tin fusion difficulty can not blown because of hot blast in the inner ring pin of plastic-sealed body or zone, basic island.
When if 11 plastic-sealed body pasters are not fine to pcb board, need do over again again heavily and to paste, because there are enough height at the tin cream place, cleaning agent cleans easily, maintenance easily behind the tin ball of burn-oning does not weld to take away like the tin ball and welds a ball again again behind the tin ball and get final product.
Description of drawings
Fig. 1 is a kind of how base island exposed individual pen pin static release ring passive device ball grid array package structure sketch map of the utility model.
Fig. 2 is the vertical view of Fig. 1.
Fig. 3 was not for there was the sketch map that high temperature resistant glued membrane is sticked at the pin lead frame back side on four sides in the past.
The sketch map of flash when the four sides that Fig. 4 sticks high temperature resistant glued membrane for the back side does not in the past have the pin leadframe package.
Fig. 5 was for sealed the structural representation of two-sided etched lead frame in the past in advance.
Wherein:
Outer basic island 1
Outer pin 2
Outer static release ring 3
In basic island 3
Interior pin 4
Interior static release ring 6
Conduction or non-conductive bonding material 10
Embodiment
Referring to Fig. 1; A kind of how base island exposed individual pen pin static release ring passive device ball grid array package structure of the utility model; It comprises basic island 1, outer pin 2 and outer static release ring 3 outward; Said outer basic island 1 is provided with a plurality of; Said outer pin 2 is provided with a circle; Said outer static release ring 3 is arranged between outer basic island 1 and the outer pin 2; Basic island 4 in said outer 1 front, basic island forms through the multilayer plating mode, pin 5 in said outer pin 2 fronts form through the multilayer plating mode, static release ring 6 in said outer static release ring 3 fronts form through the multilayer plating mode; Basic island 4, interior pin 5 and interior static release ring 6 general designation the first metal layers in said; 4 fronts, basic island are provided with chip 7 through conduction or non-conductive bonding material 10 in said, said chip 7 positive with interior pin 5 fronts between and chip 7 positive with chip 7 fronts between be connected with metal wire 8, between said interior pin 5 and the interior pin 5 through conducting electricity or 10 cross-over connections of non-conductive bonding material have passive device 13; Basic island 4, interior pin 5 and interior static release ring 6 tops and chip 7, metal wire 8 and the passive device 13 outer plastic packaging materials 9 that are encapsulated with in said; Zone between regional and outer pin 2 and the outer pin 2 between zone, outer static release ring 3 and the outer pin 2 between peripheral zone, outer basic island 1 and the outer static release ring 3 of said outer pin 2 all is equipped with gap filler 12, and the back side of outer basic island 1, outer pin 2 and outer static release ring 3 exposes outside the gap filler 12, the outer basic island 1 outside exposing gap filler 12, outer pin 2 and outside the back side of static release ring 3 be provided with tin ball 11.
Basic island 4 in said outer 1 front, basic island can not form through the multilayer plating mode; Static release ring 6 in said outer static release ring 3 fronts also can not form through the multilayer plating mode; Basic island 4 in if 1 front, outer basic island does not form, the fronts on basic island 1 outside then chip 7 directly is arranged at through conduction or non-conductive bonding material 10 at this moment.
Claims (3)
1. base island exposed individual pen pin static release ring passive device ball grid array package structure more than a kind; It is characterized in that: it comprises outer Ji Dao (1), outer pin (2) and outer static release ring (3); Said outer Ji Dao (1) is provided with a plurality of; Said outer pin (2) is provided with a circle; Said outer static release ring (3) is arranged between outer Ji Dao (1) and the outer pin (2); Said outer pin (2) is positive to form interior pin (5) through the multilayer plating mode; Said outer Ji Dao (1) front is provided with chip (7); Said chip (7) positive with interior pin (5) front between and be connected with metal wire (8) between chip (7) front and chip (7) front; Cross-over connection has passive device (13) between said interior pin (5) and the interior pin (5), the outer plastic packaging material (9) that is encapsulated with of said interior pin (5) top and chip (7), metal wire (8) and passive device (13), and zone between zone, outer static release ring (3) and the outer pin (2) between zone, outer Ji Dao (1) and the outer static release ring (3) of said outer pin (2) periphery and the zone between outer pin (2) and the outer pin (2) all are equipped with gap filler (12); And expose outside the gap filler (12) at the back side of outer Ji Dao (1), outer pin (2) and outer static release ring (3), the outer Ji Dao (1) outside exposing gap filler (12), outer pin (2) and outside the back side of static release ring (3) be provided with tin ball (11).
2. a kind of how base island exposed individual pen pin static release ring passive device ball grid array package structure according to claim 1; It is characterized in that: said outer Ji Dao (1) is positive to form interior Ji Dao (4) through the multilayer plating mode, and said chip (7) is arranged at interior Ji Dao (4) front.
3. a kind of how base island exposed individual pen pin static release ring passive device ball grid array package structure according to claim 1 and 2 is characterized in that: said outer static release ring (3) is positive to form interior static release ring (6) through the multilayer plating mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204738810U CN202394916U (en) | 2011-11-25 | 2011-11-25 | Encapsulation structure of multi-base-island exposed type single-circle pin static release ring passive device ball grid array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204738810U CN202394916U (en) | 2011-11-25 | 2011-11-25 | Encapsulation structure of multi-base-island exposed type single-circle pin static release ring passive device ball grid array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202394916U true CN202394916U (en) | 2012-08-22 |
Family
ID=46669821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011204738810U Expired - Lifetime CN202394916U (en) | 2011-11-25 | 2011-11-25 | Encapsulation structure of multi-base-island exposed type single-circle pin static release ring passive device ball grid array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202394916U (en) |
-
2011
- 2011-11-25 CN CN2011204738810U patent/CN202394916U/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120822 |