CN1738035A - Integrated circuit or discrete component flat array bump package structure - Google Patents

Integrated circuit or discrete component flat array bump package structure Download PDF

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Publication number
CN1738035A
CN1738035A CN200510041044.XA CN200510041044A CN1738035A CN 1738035 A CN1738035 A CN 1738035A CN 200510041044 A CN200510041044 A CN 200510041044A CN 1738035 A CN1738035 A CN 1738035A
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CN
China
Prior art keywords
dao
output pin
function output
basic
integrated circuit
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Pending
Application number
CN200510041044.XA
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Chinese (zh)
Inventor
王新潮
于燮康
梁志忠
谢洁人
陶玉娟
龚臻
闻荣福
郑强
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN200510041044.XA priority Critical patent/CN1738035A/en
Publication of CN1738035A publication Critical patent/CN1738035A/en
Priority to PCT/CN2006/000610 priority patent/WO2006122467A1/en
Priority to US11/910,893 priority patent/US20080285251A1/en
Priority to US11/910,885 priority patent/US20080315412A1/en
Priority to PCT/CN2006/000608 priority patent/WO2006105734A1/en
Priority to US11/910,878 priority patent/US20080258273A1/en
Priority to PCT/CN2006/000609 priority patent/WO2006105735A1/en
Priority to PCT/CN2006/000607 priority patent/WO2006105733A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention relates to a plane point-protruded type packaging structure of integrated circuit or discrete component, belonging to the technique field of integrated circuit or discrete component. It comprises a base island (1), chip (2), function output pin (3) and plastic packaging body (5), wherein, said function output pin (3) is arranged on the outer side of base island (1); the chip (2) is arranged on the base island (1). The invention is characterized in that: the base island (1) and the function output pin (3) which out of the plastic packaging body (5) protrude from the surface of plastic packing body (5); said base Island (1) contains one or several base island; said function output pin (3) is arranged as ring (single or/and several rings), or in array (single or/and several arrays); said chip (2) is single or several ones. The invention improves the quality, reduces the cost, and increases the reliability and the elimination of heat.

Description

Integrated circuit or discrete component flat array bump package structure
Technical field:
The present invention relates to a kind of integrated circuit or discrete component, be specifically related to a kind of integrated circuit or discrete component flat array bump package structure. Belong to integrated circuit or discrete component encapsulation technology field.
Background technology:
Before the present invention made, traditional integrated circuit or discrete component packing forms mainly contained four limits without pin surface label chip encapsulation (QFN) and ball array formula encapsulation (BGA) two kinds, and there is certain deficiency separately in they, now are described below:
Four limits encapsulate without pin surface label chip The encapsulation of ball array formula
One, the collocation form of Ji Dao and chip Adopt total eclipse to carve and add the lead-in wire frame of adhesive tape, and be subjected to full etched lead frame capabilities limits, can only make single Ji Dao in the same packaging body, and the performance of the ability of single Ji Dao is limited. Adopt the plastic circuit substrate can accomplish that single basic island single-chip, many of single Ji Dao arrange chip, single basic island multiple-level stack chip, in same packaging body, can also accomplish many modes of emplacements of arranging chip and how basic island multiple-level stack chip of many Ji Dao, but the cost of plastic circuit substrate is higher.
Two, the difference mode of plastic packaging external body energy output pin Adopt total eclipse to carve and add the lead-in wire frame of adhesive tape, and be subjected to full etched lead frame capabilities limits, the plastic packaging external body only may accomplish that individual pen or single function output pin distribute. Because adopting the plastic circuit substrate, the distribution form of outside function output pin can be individual pen, multi-turn, single, many rows etc.; But there is equally the higher problem of plastic circuit substrate cost.
Three, the protrusion performance of plastic packaging external body function output pin The ability that is subjected to total eclipse to carve the lead-in wire frame that adds adhesive tape is limit, and can't accomplish that the function output pin of plastic packaging external body protrudes from plastic packaging body bottom; So function output pin is relative relatively poor with the Weldability between printed circuit board (PCB), and produce easily the problem of tin cream short circuit in the welding process. Limit by the ability of plastic circuit substrate, can't accomplish directly that the function output pin of plastic packaging external body protrudes from the plastic packaging surface, so for output pin being protruded and having increased the expensive tin ball technique of planting.
Four, the coplanar ability of Ji Dao and function pin Adopt total eclipse to carve the lead-in wire frame that adds adhesive tape, be easy in process of production produce function output pin and be depressed in plastic packaging body centre and cause the bad problem of paster contact. Employing is implanted the mode of tin ball at the plastic circuit base plate bottom, but the tin ball can't be implanted on the Ji Dao, thereby makes Ji Dao and tin ball that the size dimension inequality often be arranged again and the bad problem of contact when causing paster,
The tin ball also often has the phenomenon of ball and causes the problem that lacks ball in addition.
Five, the heat radiation ability bottom the base island exposed colloid Adopt total eclipse to carve the lead-in wire frame that adds adhesive tape and can make the base island exposed in plastic packaging body bottom of heat transmission, but can't protrude from the bottom of plastic packaging body, can not utilize air to dispel the heat. It is base island exposed in plastic packaging body bottom to adopt the plastic circuit substrate to make, and the plastic circuit substrate is indirectly to conduct heat to bottom, basic island by the mode that goes between, the air of Ji Dao recycling border dispels the heat, but the heat radiation resistance of air is larger, the heat radiation poor efficiency, and in the lead-in wire process even can badly influence because heat amasss on the plastic circuit plate reliability performance of plastic circuit plate.
Six, chip Single chips: take storage chip as example, the storage volume of its single chips is 128MB, because only having one chip on the Ji Dao, so maximum storage volume also only has 128MB. Arrange chip for many: for example simultaneously placement stores with chip and power protection chip on same Ji Dao, thereby can protect storage chip to avoid dashing forward the injury of unstable power supply.
Seven, chip and output function pin Single-chip, individual pen are or/and single: individual pen/row and a small amount of I/O (input and output signal) be if change multi-turn into or/and many row functions output pin, and its package dimension can be than original to when young 1/4th. Key is different chips or packing forms, and the size of single packaging body is saved and also had nothing in common with each other. Arrange chip, circle or/and row for many: may come according to the needs of product the chip of integrated or many difference in functionalitys, be packaged into many and arrange chips, multi-turn or/and the integrated circuit of many row functions output pin; Single chips individual packages face of comparing says that it can economize the at the most space of a packaging body of next base. Key is that the quantity of the chip that is arranged in parallel is different, and the size of packaging body can be different.
Summary of the invention:
The object of the invention is to overcome above-mentioned deficiency, provide smooth and easy, the good rate of a kind of production to improve, with low cost, best in quality, reliability is high, integrated circuit or discrete component flat array bump package structure that heat radiation property is high.
The object of the present invention is achieved like this: a kind of integrated circuit or discrete component flat array bump package structure, comprise Ji Dao, chip, function output pin and plastic packaging body, described function output pin is distributed in the outside of Ji Dao, and chip is positioned on the Ji Dao, it is characterized in that:
The Ji Dao of described plastic packaging external body and function output pin protrude from the plastic packaging surface;
Described Ji Dao has single Ji Dao or a plurality of Ji Dao;
Described function output pin has single or/and many rows;
Described chip has single or multiple.
Compared with prior art, the present invention adopts flat bump array encapsulation (FBP BGA) to have following advantage:
One, the collocation form of Ji Dao and chip:
The metal substrate adopts the mode etch partially to arrange in pairs or groups behind the circuit finish layer again, can accomplish that equally single basic island single-chip, many of single Ji Dao arrange chip, can accomplish equally that in same packaging body many of many Ji Dao arrange the modes of emplacements such as chip; And the cost of metal substrate is lower. The cost of plastic circuit substrate exceeds more than the twice at least than the Metal Substrate plate material cost of flat bump array encapsulation.
Two, the difference mode of plastic packaging external body function output pin:
The metal substrate adopts twice etched mode can easily reach the multiple distribution mode of plastic packaging external body function output pin, and such as single, many rows etc., and cost is lower.
Three, the protrusion performance of plastic packaging external body function output pin
The function output pin that the metal substrate adopts twice etched mode can easily reach the plastic packaging external body protrudes from the surface of plastic packaging body.
Four, the coplanar ability of Ji Dao and function output pin:
The metal substrate adopts twice etched mode to guarantee the absolute coplanar property of Ji Dao and function output pin, and the problem that can never have function output pin to fall, lack, cave in produces.
Five, the heat radiation ability bottom the base island exposed plastic packaging body
The metal substrate adopts the mode of second etch to make the Ji Dao of heat transmission directly expose and protrude from the bottom of plastic packaging body, and Ji Dao is welded on the printed circuit board (PCB) with function output pin; So, when utilizing air to dispel the heat, the heat energy that chip changes into because of electric energy directly can also be seen through rapidly printed circuit board (PCB) and dissipate away.
Description of drawings:
Fig. 1) be embodiments of the invention 1 cross-sectional structure schematic diagrames.
Fig. 2 (a), (b)～3 (a), (b) are embodiments of the invention 2 planes and O-O facade layout drawing.
Fig. 4 (a), (b) are embodiments of the invention 3 planes and O-O facade layout drawing.
Fig. 5 (a), (b)～6 (a), (b) are embodiments of the invention 4 planes and O-O facade layout drawing.
Fig. 6 (a), (b) are embodiments of the invention 4 planes and O-O facade layout drawing.
Fig. 7 (a), (b) are embodiments of the invention 5 planes and O-O facade layout drawing.
Fig. 8 (a), (b)～9 (a), (b) are embodiments of the invention 14 planes and O-O facade layout drawing.
Figure 10 (a), (b) are embodiments of the invention 15 planes and O-O facade layout drawing.
Figure 11 (a), (b) are embodiments of the invention 16 planes and O-O facade layout drawing.
Figure 12 (a), (b) are embodiments of the invention 17 planes and O-O facade layout drawing.
Concrete enforcement mode:
Embodiment 1:
Referring to Fig. 1, adopt integrated circuit of the present invention or discrete component flat array bump package structure, mainly formed by basic island 1, chip 2, function output pin 3, gold thread 4 and plastic packaging body 5. Described function output pin 3 is distributed in the outside on basic island 1, and described chip 2 is positioned on the basic island 1. Gold thread 4 is connected between chip 2 and the function output pin 3, and described basic island 1, chip 2, function output pin 3 and gold thread 4 are all sealed with plastic packaging body 5, and makes the basic island 1 of plastic packaging external body and function output pin 3 protrude from plastic packaging body 5 surfaces. Described function output pin 3 comprises metal layer 3.1, activation layer 3.2, metal substrate layer 3.3, activation layer 3.4 and metal layer 3.5 from the inside to the outside successively. The surface that function output pin 3 protrudes from plastic packaging body 5 is coated by skin activation layer 3.4 and outer layer metal layer 3.5. Described basic island 1 comprises metal layer 1.1, activation layer 1.2, metal substrate layer 1.3, activation layer 1.4 and metal layer 1.5 from the inside to the outside successively, and the surface that basic island 1 protrudes from plastic packaging body 5 is coated by skin activation layer 1.4 and outer layer metal layer 1.5.
There are single Ji Dao or a plurality of Ji Dao in described basic island 1; Described function output pin 3 has single or/and many rows distribute; Described chip 2 has single or many.
In addition: above-described embodiment 1 can also have several special cases:
1) inside and outside two layers of activation layer 3.2,3.4 and 1.2,1.4 also can be save in function output pin 3 and basic island 1.
2) function output pin 3 and basic island 1 part that protrudes from plastic packaging body 5 only has bottom face to be coated by skin activation layer 3.4,1.4 and outer layer metal layer 3.5,1.5, and all the other parts are not wrapped by.
3) inside and outside two layers of activation layer 3.2,3.4 and 1.2,1.4 are save on function output pin 3 and basic island 1, and the part that function output pin 3 and basic island 1 protrude from the plastic packaging body only has bottom face to be coated by outer layer metal layer 3.5,1.5, and the remaining surface part is not wrapped by.
Embodiment 2: single Ji Dao/single function output pin/single-chip
Referring to Fig. 2～3, described Ji Dao has single, and the function output pin in the outside, single basic island has single, and single function output pin is arranged in a side (Fig. 1) or the many sides (Fig. 2) of single Ji Dao, and single chips is arranged on single Ji Dao.
Embodiment 3: single Ji Dao/many row functions output pin/single-chip
Referring to Fig. 4, described Ji Dao has single, and the function output pin in the outside, single basic island has many rows, and many row functions output pin is arranged in a side or the many sides of single Ji Dao; On single Ji Dao single chips is arranged. (Fig. 5)
Embodiment 4: single Ji Dao/single function output pin/multi-chip
Referring to Fig. 5～6, described Ji Dao has single, and the function output pin in the outside, single basic island has single, and single function output pin is arranged in a side (Fig. 5) or the many sides (Fig. 6) of single Ji Dao, on single Ji Dao multiple chips is arranged. The arrangement of multiple chips on single Ji Dao has to be arranged or/and stacking.
Embodiment 5: single Ji Dao/many row functions output pin/multi-chip
Referring to Fig. 7, described Ji Dao has single, and the function output pin in the outside, single basic island has many rows, and many row functions output pin is arranged in a side or the many sides of single Ji Dao; On single Ji Dao multiple chips is arranged. The arrangement of multiple chips on single Ji Dao has to be arranged or/and stacking.
Embodiment 6: many Ji Dao/single function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin in the outside, a plurality of basic island has single, and single function output pin is arranged in a side or the many sides of a plurality of Ji Dao, on each Ji Dao single chips is arranged in a plurality of basic islands.
Embodiment 7: many Ji Dao/single function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin in a plurality of basic islands outside each basic island has single, and single function output pin is arranged in a side or the many sides of each Ji Dao, on each Ji Dao single chips is arranged in a plurality of basic islands.
Embodiment 8: many Ji Dao/many row functions output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin in each outside, basic island has many rows in a plurality of basic islands, and many row functions output pin is arranged in a side or the many sides of each Ji Dao; On each Ji Dao single chips is arranged in a plurality of basic islands.
Embodiment 9: many Ji Dao/list, many row functions output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin in a plurality of basic islands outside each basic island has single, and many rows are also arranged, and the single row or multiple rows function output pin is arranged in a side or the many sides of each Ji Dao; On each Ji Dao single chips is arranged in a plurality of basic islands.
Embodiment 10: many Ji Dao/single function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin in the outside, a plurality of basic island has single, and single function output pin is arranged in a side or the many sides of a plurality of Ji Dao; On each Ji Dao multiple chips is arranged in a plurality of basic islands. The arrangement of multiple chips on each Ji Dao has to be arranged or/and stacking.
Embodiment 11: many Ji Dao/single function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin in a plurality of basic islands outside each basic island has single, and single function output pin is arranged in a side or the many sides of each Ji Dao, on each Ji Dao multiple chips is arranged in a plurality of basic islands. The arrangement of multiple chips on each Ji Dao has to be arranged or/and stacking.
Embodiment 12: many Ji Dao/many row functions output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin in each outside, basic island has many rows in a plurality of basic islands, and many row functions output pin is arranged in a side or the many sides of each Ji Dao; On each Ji Dao multiple chips is arranged in a plurality of basic islands. The arrangement of multiple chips on each Ji Dao has to be arranged or/and stacking.
Embodiment 13: many Ji Dao/list, many row functions output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin in a plurality of basic islands outside each basic island has single, and many rows are also arranged, and the single row or multiple rows function output pin is arranged in a side or the many sides of each Ji Dao; On each Ji Dao multiple chips is arranged in a plurality of basic islands. The arrangement of multiple chips on each Ji Dao has to be arranged or/and stacking.
Embodiment 14: many Ji Dao/single function output pin/list, multi-chip
Referring to Fig. 8～9, described Ji Dao has a plurality of, and the function output pin in the outside, a plurality of basic island has single, and single function output pin is arranged in a side or the many sides of a plurality of Ji Dao; On the Ji Dao that has in a plurality of basic islands single chips is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 15: many Ji Dao/single function output pin/list, multi-chip
Referring to Figure 10, described Ji Dao has a plurality of, and the function output pin in a plurality of basic islands outside each basic island has single, and single function output pin is arranged in a side or the many sides of each Ji Dao; On the Ji Dao that has in a plurality of basic islands single chips is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 16: many Ji Dao/many row functions output pin/list, multi-chip
Referring to Figure 11, described Ji Dao has a plurality of, and the function output pin in each outside, basic island has many rows in a plurality of basic islands, and many row functions output pin is arranged in a side or the many sides of each Ji Dao; On the Ji Dao that has in a plurality of basic islands single chips is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 17: many Ji Dao/list, many row functions output pin/list, multi-chip
Referring to Figure 12, described Ji Dao has a plurality of, and the function output pin in a plurality of basic islands outside each basic island has single, and many rows are also arranged, and the single row or multiple rows function output pin is arranged in a side or the many sides of each Ji Dao; On the Ji Dao that has in a plurality of basic islands single chips is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.

Claims (21)

1, a kind of integrated circuit or discrete component flat array bump package structure, comprise Ji Dao (1), chip (2), function output pin (3) and plastic packaging body (5), described function output pin (3) is distributed in the outside of Ji Dao (1), chip (2) is positioned on the Ji Dao (1), it is characterized in that:
Outside Ji Dao (1) and the function output pin (3) of described plastic packaging body (5) protrudes from plastic packaging body (5) surface;
Described Ji Dao (1) has single Ji Dao or a plurality of Ji Dao;
Described function output pin (3) has single or/and many rows;
Described chip (2) has single or multiple.
2, a kind of integrated circuit according to claim 1 or discrete component flat array bump package structure, it is characterized in that: described function output pin (3) and Ji Dao (1) comprise metal layer (3.1,1.1), metal substrate layer (3.3,1.3) and metal layer (3.5,1.5) from the inside to the outside successively, and the bottom face that function output pin (3) and Ji Dao (1) protrude from plastic packaging body (5) is coated by metal layer (3.5,1.5).
3, a kind of integrated circuit according to claim 1 or discrete component flat array bump package structure, it is characterized in that: described function output pin (3) and Ji Dao (1) comprise metal layer (3.1,1.1), metal substrate layer (3.3,1.3) and metal layer (3.5,1.5) from the inside to the outside successively, and the surface that function output pin (3) and Ji Dao (1) protrude from plastic packaging body (5) is coated by metal layer (3.5,1.5).
4, a kind of integrated circuit according to claim 1 or discrete component flat array bump package structure, it is characterized in that: described function output pin (3) and Ji Dao (1) comprise metal layer (3.1,1.1), activation layer (3.2,1.2), metal substrate layer (3.3,1.3), activation layer (3.4,1.4) and metal layer (3.5,1.5) from the inside to the outside successively, and the bottom face that function output pin (3) and Ji Dao (1) protrude from plastic packaging body (5) is coated by skin activation layer (3.4,1.4) and outer layer metal layer (3.5,1.5).
5, a kind of integrated circuit according to claim 1 or discrete component flat array bump package structure, it is characterized in that: described function output pin (3) and Ji Dao (1) comprise metal layer (3.1,1.1), activation layer (3.2,1.2), metal substrate layer (3.3,1.3), activation layer (3.4,1.4) and metal layer (3.5,1.5) from the inside to the outside successively, and the surface that function output pin (3) and Ji Dao (1) protrude from plastic packaging body (5) is coated by skin activation layer (3.4,1.4) and outer layer metal layer (3.5,1.5).
6, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat array bump package structure, it is characterized in that: described Ji Dao has single, the function output pin in the outside, single basic island has single, single function output pin is arranged in many sides of single Ji Dao, and single chips is arranged on single Ji Dao.
7, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat array bump package structure, it is characterized in that: described Ji Dao has single, the function output pin in the outside, single basic island has many rows, and many row functions output pin is arranged in a side or the many sides of single Ji Dao; On single Ji Dao single chips is arranged.
8, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat array bump package structure, it is characterized in that: described Ji Dao has single, the function output pin in the outside, single basic island has single, single function output pin is arranged in a side or the many sides of single Ji Dao, on single Ji Dao multiple chips is arranged, the arrangement of multiple chips on single Ji Dao has to be arranged or/and stacking.
9, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat array bump package structure, it is characterized in that: described Ji Dao has single, the function output pin in the outside, single basic island has many rows, and many row functions output pin is arranged in a side or the many sides of single Ji Dao; On single Ji Dao multiple chips is arranged, the arrangement of multiple chips on single Ji Dao has to be arranged or/and stacking.
10, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat array bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin in the outside, a plurality of basic island has single, single function output pin is arranged in a side or the many sides of a plurality of Ji Dao, on each Ji Dao single chips is arranged in a plurality of basic islands.
11, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat array bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin in each outside, basic island has single in a plurality of basic islands, single function output pin is arranged in a side or the many sides of each Ji Dao, on each Ji Dao single chips is arranged in a plurality of basic islands.
12, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat array bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin in each outside, basic island has many rows in a plurality of basic islands, and many row functions output pin is arranged in a side or the many sides of each Ji Dao; On each Ji Dao single chips is arranged in a plurality of basic islands.
13, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat array bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin in each outside, basic island has single in a plurality of basic islands, many rows are also arranged, and the single row or multiple rows function output pin is arranged in a side or the many sides of each Ji Dao; On each Ji Dao single chips is arranged in a plurality of basic islands.
14, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat array bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin in the outside, a plurality of basic island has single, and single function output pin is arranged in a side or the many sides of a plurality of Ji Dao; On each Ji Dao multiple chips is arranged in a plurality of basic islands, the arrangement of multiple chips on each Ji Dao has to be arranged or/and stacking.
15, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat array bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin in each outside, basic island has single in a plurality of basic islands, single function output pin is arranged in a side or the many sides of each Ji Dao, on each Ji Dao multiple chips is arranged in a plurality of basic islands, the arrangement of multiple chips on each Ji Dao has to be arranged or/and stacking.
16, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat array bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin in each outside, basic island has many rows in a plurality of basic islands, and many row functions output pin is arranged in a side or the many sides of each Ji Dao; On each Ji Dao multiple chips is arranged in a plurality of basic islands, the arrangement of multiple chips on each Ji Dao has to be arranged or/and stacking.
17, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat array bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin in each outside, basic island has single in a plurality of basic islands, many rows are also arranged, and the single row or multiple rows function output pin is arranged in a side or the many sides of each Ji Dao; On each Ji Dao multiple chips is arranged in a plurality of basic islands, the arrangement of multiple chips on each Ji Dao has to be arranged or/and stacking.
18, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat array bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin in the outside, a plurality of basic island has single, and single function output pin is arranged in a side or the many sides of a plurality of Ji Dao; On the Ji Dao that has in a plurality of basic islands single chips is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
19, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat array bump package structure, it is characterized in that: described Ji Dao has a plurality of, function output pin in a plurality of basic islands outside each basic island has single, and single function output pin is arranged in a side or the many sides of each Ji Dao; On the Ji Dao that has in a plurality of basic islands single chips is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
20, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat array bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin in each outside, basic island has many rows in a plurality of basic islands, and many row functions output pin is arranged in a side or the many sides of each Ji Dao; On the Ji Dao that has in a plurality of basic islands single chips is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
21, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat array bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin in each outside, basic island has single in a plurality of basic islands, many rows are also arranged, and the single row or multiple rows function output pin is arranged in a side or the many sides of each Ji Dao; On the Ji Dao that has in a plurality of basic islands single chips is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
CN200510041044.XA 2005-04-07 2005-07-02 Integrated circuit or discrete component flat array bump package structure Pending CN1738035A (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
CN200510041044.XA CN1738035A (en) 2005-07-02 2005-07-02 Integrated circuit or discrete component flat array bump package structure
PCT/CN2006/000610 WO2006122467A1 (en) 2005-04-07 2006-04-06 A packaging substrate with flat bumps for ic or discrete device and method of manufacturing the same
US11/910,893 US20080285251A1 (en) 2005-04-07 2006-04-06 Packaging Substrate with Flat Bumps for Electronic Devices and Method of Manufacturing the Same
US11/910,885 US20080315412A1 (en) 2005-04-07 2006-04-06 Package Structure with Flat Bumps for Integrate Circuit or Discrete Device and Method of Manufacture the Same
PCT/CN2006/000608 WO2006105734A1 (en) 2005-04-07 2006-04-06 A packaging substrate with flat bumps for electronic devices and method of manufacturing the same
US11/910,878 US20080258273A1 (en) 2005-04-07 2006-04-06 Package Structure With Flat Bumps For Electronic Device and Method of Manufacture the Same
PCT/CN2006/000609 WO2006105735A1 (en) 2005-04-07 2006-04-06 Package structure with flat bumps for integrate circuit or discrete device and method of manufacture the same
PCT/CN2006/000607 WO2006105733A1 (en) 2005-04-07 2006-04-06 Package structure with flat bumps for electronic device and method of manufacture the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN200510041044.XA CN1738035A (en) 2005-07-02 2005-07-02 Integrated circuit or discrete component flat array bump package structure

Publications (1)

Publication Number Publication Date
CN1738035A true CN1738035A (en) 2006-02-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN200510041044.XA Pending CN1738035A (en) 2005-04-07 2005-07-02 Integrated circuit or discrete component flat array bump package structure

Country Status (1)

Country Link
CN (1) CN1738035A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102403283A (en) * 2011-11-25 2012-04-04 江苏长电科技股份有限公司 Ball grid array packaging structure with basic islands and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102403283A (en) * 2011-11-25 2012-04-04 江苏长电科技股份有限公司 Ball grid array packaging structure with basic islands and manufacturing method thereof

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