CN2831433Y - Plane surrounded salient point encapsulation structure of integrated circuit or discrete component - Google Patents

Plane surrounded salient point encapsulation structure of integrated circuit or discrete component Download PDF

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Publication number
CN2831433Y
CN2831433Y CNU2005200737279U CN200520073727U CN2831433Y CN 2831433 Y CN2831433 Y CN 2831433Y CN U2005200737279 U CNU2005200737279 U CN U2005200737279U CN 200520073727 U CN200520073727 U CN 200520073727U CN 2831433 Y CN2831433 Y CN 2831433Y
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China
Prior art keywords
dao
output pin
function output
integrated circuit
discrete component
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Expired - Lifetime
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CNU2005200737279U
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Chinese (zh)
Inventor
王新潮
于燮康
梁志忠
谢洁人
陶玉娟
龚臻
闻荣福
郑强
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

The utility model relates to a planar surrounded salient point type packaging structure of an integrated circuit or discrete components, which belongs to the technical field of integrated circuits or discrete components. The utility model comprises a base (1), a chip (2), functional output pins (3) and a plastic packaging body (5), wherein the functional output pins (3) are distributed on an outer circle of the base (1), and the chip (2) is placed on the base (1). The utility model is characterized in that the base (1) and the functional output pins (3) out of the plastic packaging body (5) are bulged out of the plastic packaging body (5); the base (1) has a single base or a plurality of bases; the functional output pins (3) has a single circle or / and a plurality of circles, and a single or a plurality of chips (2) can be arranged. The utility model has the advantages of fluent production, high qualified rate, low cost, favorable quality, high reliability and high heat radiating performance.

Description

Integrated circuit or discrete component flat pen bump package structure
Technical field:
The utility model relates to a kind of integrated circuit or discrete component, is specifically related to a kind of integrated circuit or discrete component flat pen bump package structure. Belong to integrated circuit or discrete component encapsulation technology field.
Background technology:
Before the utility model is made, traditional integrated circuit or discrete component packing forms mainly contain four limits without pin surface label chip encapsulation (QFN) and ball array formula encapsulation (BGA) two kinds, there is certain deficiency separately in they, now are described below:
Four limits encapsulate without pin surface label chip The encapsulation of ball array formula
One, the collocation form of Ji Dao and chip Adopt total eclipse to carve and add the lead frame of adhesive tape, and be subjected to total eclipse to carve the lead frame capabilities limits, can only make single Ji Dao in the same packaging body, and the performance of the ability of single Ji Dao is limited. Adopt the plastic circuit substrate can accomplish that single basic island single-chip, many of single Ji Dao arrange chip, single basic island multiple-level stack chip, in same packaging body, can also accomplish many modes of emplacements of arranging chip and how basic island multiple-level stack chip of many Ji Dao, but the cost of plastic circuit substrate is higher.
Two, the difference mode of plastic-sealed body external energy output pin Adopt total eclipse to carve and add the lead frame of adhesive tape, and be subjected to total eclipse to carve the lead frame capabilities limits, outside individual pen or the single function output pin only may accomplished of plastic-sealed body distributes. Because adopting the plastic circuit substrate, the distribution form of external function output pin can be individual pen, multi-turn, single, many rows etc.; But there is equally the higher problem of plastic circuit substrate cost.
Three, the protrusion performance of plastic-sealed body external function output pin The ability that is subjected to total eclipse to carve the lead frame that adds adhesive tape is limit, and can't accomplish that the function output pin of plastic-sealed body outside protrudes from the plastic-sealed body bottom; So function output pin is relative relatively poor with the Weldability between printed circuit board (PCB), and produce easily the problem of tin cream short circuit in the welding process. Limit by the ability of plastic circuit substrate, can't accomplish directly that the function output pin of plastic-sealed body outside protrudes from the plastic-sealed body surface, so for output pin being protruded and having increased the expensive tin ball technique of planting.
Four, the coplanar ability of Ji Dao and function pin Adopt total eclipse to carve the lead frame that adds adhesive tape, be easy in process of production produce function output pin and be depressed in the plastic-sealed body centre and cause the bad problem of paster contact. The mode of tin ball is implanted in employing at the plastic circuit base plate bottom, but the tin ball can't be implanted on the Ji Dao, thereby make Ji Dao and tin ball that the uneven and bad problem of contact when causing paster of size dimension often be arranged again, the tin ball also often has the phenomenon of ball and causes the problem that lacks ball in addition.
Five, the heat-sinking capability bottom the base island exposed colloid Adopt total eclipse to carve the lead frame that adds adhesive tape and can make the base island exposed in the plastic-sealed body bottom of heat transmission, but can't protrude from the bottom of plastic-sealed body, can not utilize air to dispel the heat. It is base island exposed in the plastic-sealed body bottom to adopt the plastic circuit substrate to make, and the plastic circuit substrate is indirectly to conduct heat to bottom, basic island by the mode that goes between, the air of Ji Dao recycling border dispels the heat, but the heat radiation resistance of air is larger, radiating efficiency is very poor, and in the lead-in wire process even can badly influence because heat amasss on the plastic circuit plate reliability performance of plastic circuit plate.
Six, chip Single chips: take storage chip as example, the storage volume of its single chips is 128MB, because only having one chip on the Ji Dao, so the maximum storage capacity also only has 128MB. Arrange chip for many: for example simultaneously placement stores with chip and power protection chip on same Ji Dao, thereby can protect storage chip to avoid dashing forward the injury of unstable power supply.
Seven, chip and output function pin Single-chip, individual pen are or/and single: individual pen/row and a small amount of I/O (input and output signal) be if change multi-turn into or/and many row functions output pin, and its package dimension can be than original to when young 1/4th. Key is different chips or packing forms, and the size of single packaging body is saved and also had nothing in common with each other. Arrange chip, circle or/and row for many: may come according to the needs of product the chip of integrated or many difference in functionalitys, be packaged into many and arrange chips, multi-turn or/and the integrated circuit of many row functions output pin; Single chips individual packages face of comparing says that it can economize the at the most space of a packaging body of next base. Key is that the quantity of the chip that is arranged in parallel is different, and the size of packaging body can be different.
Summary of the invention:
The purpose of this utility model is to overcome above-mentioned deficiency, provides that a kind of production is smooth and easy, yield improves, and with low cost, best in quality, reliability is high, the integrated circuit that thermal diffusivity is high or discrete component flat pen bump package structure.
The purpose of this utility model is achieved in that a kind of integrated circuit or discrete component flat pen bump package structure, comprise Ji Dao, chip, function output pin and plastic-sealed body, described function output pin is distributed in the outer ring of Ji Dao, and chip is positioned on the Ji Dao, it is characterized in that:
Ji Dao and the function output pin of described plastic-sealed body outside protrude from the plastic-sealed body surface;
Described Ji Dao has single Ji Dao or a plurality of Ji Dao;
Individual pen is arranged described function output pin or/and multi-turn;
Described chip has single or multiple.
Compared with prior art, the utility model adopts flat bump array encapsulation (FBP BGA) to have following advantage:
One, the collocation form of Ji Dao and chip:
Metal substrate adopts the mode etch partially to arrange in pairs or groups behind the circuit finish layer again, can accomplish equally single basic island single-chip, single basic island multiple chips, can accomplish the modes of emplacements such as many Ji Dao, multiple chips equally in same packaging body; And the cost of metal substrate is lower. The cost of plastic circuit substrate exceeds more than the twice at least than the metal substrate material cost of flat bump array encapsulation.
Two, the difference mode of plastic-sealed body external function output pin:
Metal substrate adopts twice etched mode can easily reach the multiple distribution mode of plastic-sealed body external function output pin, and such as individual pen, multi-turn etc., and cost is lower.
Three, the protrusion performance of plastic-sealed body external function output pin
The function output pin that metal substrate adopts twice etched mode can easily reach the plastic-sealed body outside protrudes from the surface of plastic-sealed body.
Four, the coplanar ability of Ji Dao and function output pin:
Metal substrate adopts twice etched mode to guarantee the absolute coplanarity of Ji Dao and function output pin, and the problem that can never have function output pin to fall, lack, cave in produces.
Five, the heat-sinking capability bottom the base island exposed plastic-sealed body
Metal substrate adopts the mode of second etch to make the Ji Dao of heat transmission directly expose and protrude from the bottom of plastic-sealed body, and Ji Dao is welded on the printed circuit board (PCB) with function output pin; So, when utilizing air to dispel the heat, the heat energy that chip changes into because of electric energy directly can also be seen through rapidly printed circuit board (PCB) and dissipate away.
Six, multi-turn output function pin
Can be packaged into according to the needs of product the integrated circuit of multi-turn function output pin; Single chips individual packages of comparing, it can economize the space of next even many packaging bodies.
Description of drawings:
Fig. 1 is cross sectional representation of the present utility model.
Fig. 2 (a), (b) are respectively embodiment of the present utility model 2 planes and O-O facade layout drawing.
Fig. 3 (a), (b) are respectively embodiment of the present utility model 4 planes and O-O facade layout drawing.
Fig. 4 (a), (b) are respectively embodiment of the present utility model 13 planes and O-O facade layout drawing.
Fig. 5 (a), (b) are respectively embodiment of the present utility model 14 planes and O-O facade layout drawing.
Fig. 6 (a), (b) are respectively embodiment of the present utility model 15 planes and O-O facade layout drawing.
Fig. 7 (a), (b) are respectively embodiment of the present utility model 16 planes and O-O facade layout drawing.
The specific embodiment:
Referring to Fig. 1, a kind of integrated circuit or discrete component flat pen bump package structure mainly are comprised of basic island 1, chip 2, function output pin 3, gold thread 4 and plastic-sealed body 5. Described function output pin 3 is distributed in the outer ring on basic island 1, and described chip 2 is positioned on the basic island 1. Gold thread 4 is connected between chip 2 and the function output pin 3, and described basic island 1, chip 2, function output pin 3 and gold thread 4 are all sealed with plastic-sealed body 5, and makes the basic island 1 of plastic-sealed body outside and function output pin 3 protrude from plastic-sealed body 5 surfaces. Described function output pin 3 comprises metal level 3.1, active layer 3.2, metal substrate layer 3.3, active layer 3.4 and metal level 3.5 from the inside to the outside successively. The surface that function output pin 3 protrudes from plastic-sealed body 5 is coated by outer active layer 3.4 and outer layer metal layer 3.5. Described basic island 1 comprises metal level 1.1, active layer 1.2, metal substrate layer 1.3, active layer 1.4 and metal level 1.5 from the inside to the outside successively, and the surface that basic island 1 protrudes from plastic-sealed body 5 is coated by outer active layer 1.4 and outer layer metal layer 1.5.
There are single Ji Dao or a plurality of Ji Dao in described basic island 1; Described function output pin 3 has individual pen or/and multi-turn distributes; Described chip 2 has single or many.
In addition: above-described embodiment 1 can also have several special cases:
1) inside and outside two-layer active layer 3.2,3.4 and 1.2,1.4 also can be save in function output pin 3 and basic island 1.
2) function output pin 3 and basic island 1 part that protrudes from plastic-sealed body 5 only has bottom face by outer active layer 3.4,1.4 and outer layer metal layer 3.5,1.5 plating, and remainder is not by plating.
3) inside and outside two-layer active layer 3.2,3.4 and 1.2,1.4 is save on function output pin 3 and basic island 1, and the part that function output pin 3 and basic island 1 protrude from plastic-sealed body only has bottom face by outer layer metal layer 3.5,1.5 plating, and the remaining surface part is not by plating.
Below in conjunction with accompanying drawing the specific embodiment of the present utility model is described in further detail:
Embodiment 2: single Ji Dao/multi-turn function output pin/single-chip
Referring to Fig. 2, described Ji Dao has single, and the function output pin of single Ji Dao outer ring has multi-turn; On single Ji Dao single chips is arranged.
Embodiment 3: single Ji Dao/individual pen function output pin/multi-chip
Described Ji Dao has single, and the function output pin of single Ji Dao outer ring has individual pen, on single Ji Dao multiple chips is arranged, and the arrangement of multiple chips on single Ji Dao has to be arranged or/and stacking.
Embodiment 4: single Ji Dao/multi-turn function output pin/multi-chip
Referring to Fig. 3, described Ji Dao has single, and the function output pin of single Ji Dao outer ring has multi-turn; On single Ji Dao multiple chips is arranged, the arrangement of multiple chips on single Ji Dao has to be arranged or/and stacking.
Embodiment 5: many Ji Dao/individual pen function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin of a plurality of Ji Dao outer ring has individual pen, on each Ji Dao single chips is arranged in a plurality of basic islands.
Embodiment 6: many Ji Dao/individual pen function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin of each Ji Dao outer ring has individual pen in a plurality of basic islands, on each Ji Dao single chips is arranged in a plurality of basic islands.
Embodiment 7: many Ji Dao/multi-turn function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin of each Ji Dao outer ring has multi-turn in a plurality of basic islands, on each Ji Dao single chips is arranged in a plurality of basic islands.
Embodiment 8: many Ji Dao/list, multi-turn function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin of each Ji Dao outer ring has individual pen in a plurality of basic islands, and multi-turn is also arranged, and on each Ji Dao single chips is arranged in a plurality of basic islands.
Embodiment 9: many Ji Dao/individual pen function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin of a plurality of Ji Dao outer ring has individual pen, on each Ji Dao multiple chips is arranged in a plurality of basic islands, and the arrangement of multiple chips on each Ji Dao has to be arranged or/and stacking.
Embodiment 10: many Ji Dao/individual pen function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin of each Ji Dao outer ring has individual pen in a plurality of basic islands, on each Ji Dao multiple chips is arranged in a plurality of basic islands, and the arrangement of multiple chips on each Ji Dao has to be arranged or/and stacking.
Embodiment 11: many Ji Dao/multi-turn function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin of each Ji Dao outer ring has multi-turn in a plurality of basic islands, on each Ji Dao multiple chips is arranged in a plurality of basic islands, and the arrangement of multiple chips on each Ji Dao has to be arranged or/and stacking.
Embodiment 12: many Ji Dao/list, multi-turn function output pin/multi-chip
Described Ji Dao has a plurality of, and the function output pin of each Ji Dao outer ring has individual pen in a plurality of basic islands, and multi-turn is also arranged, and on each Ji Dao multiple chips is arranged in a plurality of basic islands, and the arrangement of multiple chips on each Ji Dao has to be arranged or/and stacking.
Embodiment 13: many Ji Dao/individual pen function output pin/list, multi-chip
Referring to Fig. 4, described Ji Dao has a plurality of, and the function output pin of a plurality of Ji Dao outer ring has individual pen, on the Ji Dao that has in a plurality of basic islands single chips is arranged, and on the Ji Dao that has multiple chips is arranged, and the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 14: many Ji Dao/individual pen function output pin/list, multi-chip
Referring to Fig. 5, described Ji Dao has a plurality of, and the function output pin of each Ji Dao outer ring has individual pen in a plurality of basic islands, on the Ji Dao that has in a plurality of basic islands single chips is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 15: many Ji Dao/multi-turn function output pin/list, multi-chip
Referring to Fig. 6, described Ji Dao has a plurality of, and the function output pin of each Ji Dao outer ring has multi-turn in a plurality of basic islands, on the Ji Dao that has in a plurality of basic islands single chips is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
Embodiment 16: many Ji Dao/list, multi-turn function output pin/list, multi-chip
Referring to Fig. 7, described Ji Dao has a plurality of, and the function output pin of each Ji Dao outer ring has individual pen in a plurality of basic islands, multi-turn is also arranged, on the Ji Dao that has in a plurality of basic islands single chips is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.

Claims (20)

1, a kind of integrated circuit or discrete component flat pen bump package structure, comprise Ji Dao (1), chip (2), function output pin (3) and plastic-sealed body (5), described function output pin (3) is distributed in the outer ring of Ji Dao (1), chip (2) is positioned on the Ji Dao (1), it is characterized in that:
Outside Ji Dao (1) and the function output pin (3) of described plastic-sealed body (5) protrudes from plastic-sealed body (5) surface;
Described Ji Dao (1) has single Ji Dao or a plurality of Ji Dao;
Described function output pin (3) has individual pen or/and multi-turn;
Described chip (2) has single or multiple.
2, a kind of integrated circuit according to claim 1 or discrete component flat pen bump package structure, it is characterized in that: described function output pin (3) and Ji Dao (1) comprise metal level (3.1,1.1), metal substrate layer (3.3,1.3) and metal level (3.5,1.5) from the inside to the outside successively, protrude from the bottom face of the function output pin (3) of plastic-sealed body (5) and Ji Dao (1) all by metal level (3.5,1.5) plating.
3, a kind of integrated circuit according to claim 1 or discrete component flat pen bump package structure, it is characterized in that: described function output pin (3) and Ji Dao (1) comprise metal level (3.1,1.1), metal substrate layer (3.3,1.3) and metal level (3.5,1.5) from the inside to the outside successively, protrude from the function output pin (3) of plastic-sealed body (5) and the surface of Ji Dao (1) and are all coated by metal level (3.5,1.5).
4, a kind of integrated circuit according to claim 1 or discrete component flat pen bump package structure, it is characterized in that: described function output pin (3) and Ji Dao (1) comprise metal level (3.1,1.1), active layer (3.2,1.2), metal substrate layer (3.3,1.3), active layer (3.4,1.4) and metal level (3.5,1.5) from the inside to the outside successively, protrude from the bottom face of the function output pin (3) of plastic-sealed body (5) and Ji Dao (1) all by outer active layer (3.4,1.4) and outer layer metal layer (3.5,1.5) plating.
5, a kind of integrated circuit according to claim 1 or discrete component flat pen bump package structure, it is characterized in that: described function output pin (3) and Ji Dao (1) comprise metal level (3.1,1.1), active layer (3.2,1.2), metal substrate layer (3.3,1.3), active layer (3.4,1.4) and metal level (3.5,1.5) from the inside to the outside successively, protrude from the function output pin (3) of plastic-sealed body (5) and the surface of Ji Dao (1) and are all coated by outer active layer (3.4,1.4) and outer layer metal layer (3.5,1.5).
6, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat pen bump package structure, it is characterized in that: described Ji Dao has single, and the function output pin of single Ji Dao outer ring has multi-turn; On single Ji Dao single chips is arranged.
7, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat pen bump package structure, it is characterized in that: described Ji Dao has single, the function output pin of single Ji Dao outer ring has individual pen, on single Ji Dao multiple chips is arranged, the arrangement of multiple chips on single Ji Dao has to be arranged or/and stacking.
8, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat pen bump package structure, it is characterized in that: described Ji Dao has single, and the function output pin of single Ji Dao outer ring has multi-turn; On single Ji Dao multiple chips is arranged, the arrangement of multiple chips on single Ji Dao has to be arranged or/and stacking.
9, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat pen bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin of a plurality of Ji Dao outer ring has individual pen, on each Ji Dao single chips is arranged in a plurality of basic islands.
10, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat pen bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin of each Ji Dao outer ring has individual pen in a plurality of basic islands, on each Ji Dao single chips is arranged in a plurality of basic islands.
11, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat pen bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin of each Ji Dao outer ring has multi-turn in a plurality of basic islands, on each Ji Dao single chips is arranged in a plurality of basic islands.
12, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat pen bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin of each Ji Dao outer ring has individual pen in a plurality of basic islands, multi-turn is also arranged, on each Ji Dao single chips is arranged in a plurality of basic islands.
13, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat pen bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin of a plurality of Ji Dao outer ring has individual pen, on each Ji Dao multiple chips is arranged in a plurality of basic islands, the arrangement of multiple chips on each Ji Dao has to be arranged or/and stacking.
14, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat pen bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin of each Ji Dao outer ring has individual pen in a plurality of basic islands, on each Ji Dao multiple chips is arranged in a plurality of basic islands, the arrangement of multiple chips on each Ji Dao has to be arranged or/and stacking.
15, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat pen bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin of each Ji Dao outer ring has multi-turn in a plurality of basic islands, on each Ji Dao multiple chips is arranged in a plurality of basic islands, the arrangement of multiple chips on each Ji Dao has to be arranged or/and stacking.
16, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat pen bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin of each Ji Dao outer ring has individual pen in a plurality of basic islands, multi-turn is also arranged, on each Ji Dao multiple chips is arranged in a plurality of basic islands, the arrangement of multiple chips on each Ji Dao has to be arranged or/and stacking.
17, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat pen bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin of a plurality of Ji Dao outer ring has individual pen, on the Ji Dao that has in a plurality of basic islands single chips is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
18, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat pen bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin of each Ji Dao outer ring has individual pen in a plurality of basic islands, on the Ji Dao that has in a plurality of basic islands single chips is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
19, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat pen bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin of each Ji Dao outer ring has multi-turn in a plurality of basic islands, on the Ji Dao that has in a plurality of basic islands single chips is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
20, according to claim 1～5 one of them described a kind of integrated circuit or discrete component flat pen bump package structure, it is characterized in that: described Ji Dao has a plurality of, the function output pin of each Ji Dao outer ring has individual pen in a plurality of basic islands, multi-turn is also arranged, on the Ji Dao that has in a plurality of basic islands single chips is arranged, on the Ji Dao that has multiple chips is arranged, the arrangement of multiple chips on Ji Dao has to be arranged or/and stacking.
CNU2005200737279U 2005-07-06 2005-07-06 Plane surrounded salient point encapsulation structure of integrated circuit or discrete component Expired - Lifetime CN2831433Y (en)

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