CN1941343A - Chip structure and stacked chip packing structure - Google Patents
Chip structure and stacked chip packing structure Download PDFInfo
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- CN1941343A CN1941343A CNA2005101080964A CN200510108096A CN1941343A CN 1941343 A CN1941343 A CN 1941343A CN A2005101080964 A CNA2005101080964 A CN A2005101080964A CN 200510108096 A CN200510108096 A CN 200510108096A CN 1941343 A CN1941343 A CN 1941343A
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- 238000012856 packing Methods 0.000 title description 7
- 238000004806 packaging method and process Methods 0.000 claims description 43
- 239000000758 substrate Substances 0.000 claims description 42
- 239000011241 protective layer Substances 0.000 claims description 39
- 239000010410 layer Substances 0.000 claims description 33
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000003466 welding Methods 0.000 abstract 13
- 238000000034 method Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 7
- 239000000084 colloidal system Substances 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 230000012447 hatching Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
Abstract
The invention is concerned with the CMOS chip structure, including: the main body of the CMOS chip, the first protecting layer, the re-configuring circuit layer, and the second protecting layer; it is: the main body of the CMOS chip is with the welding jointing area, near the single side edge or neighbor both sides of the main body of the CMOS chip, the main body of the CMOS chip is with the first welding underlay in several welding jointing area and the second welding underlay located out of several welding jointing area; the first protecting layer with several first hatches configures on the main body of the CMOS chip in order to emerge the first welding underlay and the second welding underlay; the re-configuring circuit layer with several third welding underlay located in the welding line jointing area configures on the first protecting layer, extends form the second welding underlay to the welding line jointing area; the second protecting layer with several second hatches covers on the re-configuring circuit layer in order to emerge the fires welding underlay and the third welding underlay.
Description
Technical field
The invention relates to a kind of chip structure and chip-packaging structure thereof, and particularly pile up the stack type chip packaging structure that is constituted relevant for a kind of chip structure of tool reconfiguration line layer and by it.
Background technology
In information society now, the user pursues electronic product high-speed, high-quality, multiplex's energy property.With regard to product appearance, the design of electronic product also strides forward towards light, thin, short, little trend.In order to achieve the above object, many companies all incorporate systematized notion when carrying out circuit design, and making single chips (chip is wafer, below all be called chip) to possess has multiple function, are configured in core number in the electronic product with saving.In addition, with regard to the Electronic Packaging technology, in order to cooperate light, thin, short, little designer trends, also develop and multi-chip modules (multi-chipmodule, MCM) package design notion, chip size structure dress (chip scale package, the notion of package design notion CSP) and stacked multicore sheet package design etc.
Figure 1A illustrates the known the cutaway view identical or stack chip packaging structure of close chip size that has.Please refer to Figure 1A, known stack chip packaging structure 100 comprises a circuit substrate (package substrate) 110, chip 120a, chip 120b, a sept (spacer) 130, many leads 140 and a packing colloid (encapsulant) 150.Have a plurality of weld pads 112 on the circuit substrate 110, and also have a plurality of weld pad 122a and 122b respectively on chip 120a and the 120b, wherein weld pad 122a and 122b are arranged on chip 120a and the 120b with kenel (periperal type) on every side.Chip 120a is disposed on the circuit substrate 110, and chip 120b is disposed at the top of chip 120a via sept 130.The two ends of part lead 140 are to be connected to weld pad 112 and 122a via routing processing procedure (wirebonding process), so that chip 120a is electrically connected at circuit substrate 110.And the two ends of other part leads 140 also are connected to weld pad 112 and 122b via the routing processing procedure, so that chip 120b is electrically connected at circuit substrate 110.Be disposed on the circuit substrate 110 as for 150 of packing colloids, and coat these leads 140, chip 120a and 120b.
Because weld pad 122a and 122b are arranged on chip 120a and the 120b with kenel on every side, therefore the direct carries chips 120b of chip 120a, be with known techniques must be between chip 120a and 120b configuration space thing 130, make between chip 120a and the 120b at a distance of a suitable distance, in order to the carrying out of follow-up routing processing procedure.Yet the use of sept 130 but causes the thickness of known stack chip packaging structure 100 to reduce further easily.
In addition, known techniques proposes another kind of stack chip packaging structure with different chip sizes, and its cutaway view is shown in Figure 1B.See also shown in Figure 1B, known stack chip packaging structure 100 ' comprises a circuit substrate (package substrate) 110, chip 120c, chip 120d, many leads 140 and a packing colloid 150.Have a plurality of weld pads 112 on the circuit substrate 110.The size of chip 120c is the size greater than chip 120d, and also has a plurality of weld pad 122c and 122d respectively on chip 120c and the 120d, and wherein weld pad 122c and 122d are arranged on chip 120c and the 120d with kenel (peripheral type) on every side.Chip 120c is disposed on the circuit substrate 110, and chip 120d is disposed at the top of chip 120c.The two ends of part lead 140 are to be connected to weld pad 112 and 122c via routing processing procedure (wirebonding process), so that chip 120c is electrically connected at circuit substrate 110.And the two ends of other part leads 140 also are connected to weld pad 112 and 122d via the routing processing procedure, so that chip 120d is electrically connected at circuit substrate 110.Be disposed on the circuit substrate 110 as for 150 of packing colloids, and coat these leads 140, chip 120c and 120d.
Because chip 120d is less than chip 120c, therefore when chip 120d was disposed on the chip 120c, chip 120d can not cover the weld pad 122c of chip 120c.But when known techniques piles up stack chip packaging structure 100 ' with the chip of a plurality of different size sizes in above-mentioned mode, because the chip size on upper strata must be more little more, be the restriction of piling up quantity that chip is arranged with stack chip packaging structure 100 '.
Summary of the invention
Purpose of the present invention is to provide a kind of chip structure exactly, and this chip structure is suitable for piling up in limited area.
A further object of the present invention provides a kind of stack chip packaging structure, and it has higher encapsulation integration and thin thickness.
The present invention proposes a kind of chip structure, and it comprises a chip body, one first protective layer, a reconfiguration line layer and one second protective layer.The first chip body has a wire bonds zone, and the wire bonds zone is single side or the adjacent dual-side that is adjacent to the chip body, and its chips body has a plurality of first weld pad and a plurality of extra-regional second weld pads of wire bonds that are positioned at that are positioned at the wire bonds zone.First protective layer is disposed on the chip body, and wherein first protective layer has a plurality of first openings, to expose these first weld pads and these second weld pads.Reconfiguration line layer then is disposed on first protective layer, and wherein reconfiguration line layer extends in the wire bonds zone from these second weld pads, and reconfiguration line layer has a plurality of the 3rd weld pads that are positioned at the wire bonds zone.Second protective layer is covered on the reconfiguration line layer, and wherein second protective layer has a plurality of second openings, to expose these first weld pads and these the 3rd weld pads.
The present invention proposes a kind of stack chip packaging structure, and it comprises a circuit substrate, a plurality of chip structure and many leads.Each chip structure comprises a chip body, one first protective layer, a reconfiguration line layer and one second protective layer.The first chip body has a wire bonds zone, and the wire bonds zone is single side or the adjacent dual-side that is adjacent to the chip body, and its chips body has a plurality of first weld pad and a plurality of extra-regional second weld pads of wire bonds that are positioned at that are positioned at the wire bonds zone.First protective layer is disposed on the chip body, and wherein first protective layer has a plurality of first openings, to expose these first weld pads and these second weld pads.Reconfiguration line layer then is disposed on first protective layer, and wherein reconfiguration line layer extends in the wire bonds zone from these second weld pads, and reconfiguration line layer has a plurality of the 3rd weld pads that are positioned at the wire bonds zone.Second protective layer is covered on the reconfiguration line layer, and wherein second protective layer has a plurality of second openings, to expose these first weld pads and these the 3rd weld pads.And these leads are to be connected in these chip structures and circuit substrate, so that these chip structures are electrically connected at circuit substrate.
According to the described stack chip packaging structure of preferred embodiment of the present invention, an end of these leads is connected in these first weld pads or these the 3rd weld pads, and the other end of these leads is connected in circuit substrate.
According to the described stack chip packaging structure of preferred embodiment of the present invention, these leads more comprise many first leads and many second leads, wherein the two ends of each bar first lead are first weld pad or the 3rd weld pads that is connected to adjacent two chip structures, and the two ends of each bar second lead be respectively the connecting circuit substrate be adjacent to first weld pad or the 3rd weld pad of the chip structure of circuit substrate.
According to the described stack chip packaging structure of preferred embodiment of the present invention, more comprise a control chip, be disposed on the chip packing-body of the superiors, and expose the wire bonds district of the chip structure of the superiors, and control chip is to be electrically connected at circuit substrate via these leads.
According to described chip structure of preferred embodiment of the present invention and stack chip packaging structure, wherein the material of reprovision line layer comprises gold, copper, nickel, titanizing tungsten or titanium.
According to described chip structure of preferred embodiment of the present invention and stack chip packaging structure, wherein these first weld pads and these second weld pads are so that kenel or face array kenel are arranged on this chip body on every side.
According to described chip structure of preferred embodiment of the present invention and stack chip packaging structure, wherein these first weld pads and these the 3rd weld pads are that single side along the chip body is arranged at least one row.
Because these the first and the 3rd weld pads all are positioned at the wire bonds district, therefore chip structure proposed by the invention can utilize zone in addition, wire bonds district directly to carry another chip structure.In addition, in stack chip packaging structure proposed by the invention, because each chip structure than the upper strata all can directly be stacked in than the zone beyond the wire bonds district of the chip structure of lower floor, therefore compared to known techniques, stack chip packaging structure of the present invention can be exempted the use of sept, is to have higher encapsulation integration and thin thickness with the present invention.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Figure 1A illustrates the cutaway view of known stack chip packaging structure.
Figure 1B illustrates the cutaway view of another kind of known stack chip packaging structure.
Fig. 2 A～2C illustrates the manufacturing process schematic diagram into chip structure of the present invention.
Fig. 3 and Fig. 4 cutaway view for being illustrated along hatching A-A ' and B-B ' respectively among Fig. 2 C.
Fig. 5 illustrates the schematic diagram into stack type chip packaging structure of the present invention.
Fig. 6 illustrates the schematic diagram into the stack type chip packaging structure of another embodiment of the present invention.
Fig. 7 illustrates the schematic diagram into the stack type chip packaging structure of further embodiment of this invention.
100,100 ', 400: stack chip packaging structure
110,410: circuit substrate
112,122a, 122b, 122c, 122d: weld pad
120a, 120b, 120c, 120d: chip
130: sept
140,242,420,420a, 420b: lead
150,430: packing colloid
210: the chip body
212a: first weld pad
212b: second weld pad
220: the wire bonds district
230: the first protective layers
232: the first openings
240: reconfiguration line layer
244: the three weld pads
250: the second protective layers
252: the second openings
300,300a, 300b: chip structure
412: the four weld pads
440: control chip
Embodiment
Fig. 2 A～2C illustrates the manufacturing process schematic diagram into chip structure of the present invention.Please refer to shown in Fig. 2 A, chip body 210 at first is provided, and cook up wire bonds district 220 at the single side that is adjacent to chip body 210, the a plurality of weld pads 212 on the active surface of chip body 210 are divided into the first weld pad 212a and the second weld pad 212b, wherein the first weld pad 212a is positioned at wire bonds district 220, the second weld pad 212b then to be positioned at outside the wire bonds district 220.
Please refer to shown in Fig. 2 B, form first protective layer 230 afterwards on chip body 210, wherein first protective layer 230 has a plurality of first openings 232, to expose the first weld pad 212a and the second weld pad 212b.On first protective layer 230, form reconfiguration line layer 240 then.And reconfiguration line layer 240 comprises many leads 242 and a plurality of the 3rd weld pads 244, wherein the 3rd weld pad 244 is to be positioned at wire bonds district 220, and these leads 242 are to extend to the 3rd weld pad 244 from the second weld pad 212b respectively, so that the second weld pad 212b is electrically connected at the 3rd weld pad 244.In addition, the material of reconfiguration line layer 240 for example can be gold, copper, nickel, titanizing tungsten, titanium or other electric conducting material.
It should be noted that, though the first above-mentioned weld pad 212a and the second weld pad 212b are arranged on the active surface of chip body 210 with kenel on every side, the first weld pad 212a and the second weld pad 212b can also be arranged on the chip body 210 via face array kenel (area array type) or other kenel, and certain second weld pad 212b is electrically connected at the 3rd weld pad 244 via lead 242.In addition, present embodiment does not also limit the arrangement mode of the 3rd weld pad 244, though the 3rd weld pad 244 and the first weld pad 212a are arranged in two row in Fig. 2 B, and the single side along chip body 210 is arranged, but the 3rd weld pad 244 and the first weld pad 212a can also with single-row, multiple row or other mode be arranged in the wire bonds district 220.
Please refer to Fig. 2 C, after forming reconfiguration line layer 240, second protective layer 250 is covered on the reconfiguration line layer 240, and form chip structure 300.Wherein second protective layer 250 has a plurality of second openings 252, to expose the first weld pad 212a and the 3rd weld pad 244.
Fig. 3 and Fig. 4 cutaway view for being illustrated along hatching A-A ' and B-B ' respectively among Fig. 2 C.Please jointly with reference to Fig. 2 C, Fig. 3 and shown in Figure 4, chip structure 300 mainly comprises chip body 210, first protective layer 230, reconfiguration line layer 240 and second protective layer 250 from the above.Wherein, chip body 210 has wire bonds district 220, and wire bonds district 220 is the single sides that are adjacent to chip body 210.In addition, chip body 210 has a plurality of first weld pad 212a and the second weld pad 212b, and wherein the first weld pad 212a is positioned at wire bonds district 220, and the second weld pad 212b is positioned at outside the wire bonds district 220.
First protective layer 230 is disposed on the chip body 210, and wherein first protective layer 230 has a plurality of first openings 232, to expose these the first weld pad 212a and the second weld pad 212b.Reconfiguration line layer 240 is disposed on first protective layer 230, and wherein reconfiguration line layer 240 extends in the wire bonds district 220 from the second weld pad 212b, and reconfiguration line layer 240 has a plurality of the 3rd weld pads 244, and it is disposed in the wire bonds district 220.Second protective layer 250 is covered on the reconfiguration line layer 240, and wherein second protective layer 250 has a plurality of second openings 252, to expose these first weld pad 212a and the 3rd weld pad 244.
Because the first weld pad 212a and the 3rd weld pad 244 all are positioned at wire bonds district 220, therefore the zone beyond the wire bonds district 220 on second protective layer 250 just can provide the platform of a carrying, to carry another chip structure.In addition, in other embodiments of the invention, more can cook up wire bonds district 220 at the adjacent dual-side of chip body 210.Yet because the difference of this embodiment and aforesaid embodiment only in the position of wire bonds district 220 on chip body 210, this just no longer giving unnecessary details more.
Be more to propose a kind of stack type chip packaging structure 400 with present embodiment according to this chip structure 300, its schematic diagram as shown in Figure 5.See also shown in Figure 5ly, stack type chip packaging structure 400 mainly comprises circuit substrate 410, chip structure 300a, 300b and many leads 420.Wherein have a plurality of the 4th weld pads 412 on the circuit substrate 410.And chip structure 300a, 300b are stacked on the circuit substrate 410, and wherein chip structure 300a, 300b are identical with chip structure 300, just repeat no more in this.One end of these leads 420 is the first weld pad 212a or the 3rd weld pads 244 that are connected in chip structure 300a, 300b, the other end of lead 420 then is connected in the 4th weld pad 412 of circuit substrate 410, so that chip structure 300a, 300b are electrically connected at circuit substrate 410, wherein the material of these leads 420 for example is a gold.In addition, stack type chip packaging structure 400 for example has more packing colloid 430 and is covered on the circuit substrate 410, and coating chip structure 300a, 300b and these leads 420.
It should be noted that chip structure 300b directly is stacked on the chip structure 300a, and be stacked in the zone beyond the wire bonds district 220, is can successfully carry out with follow-up routing processing procedure.In addition, present embodiment does not limit the quantity of the chip structure 300 that is stacked on the circuit substrate 410, all know this skill person should be according to above-mentioned disclosed method, and produce the stack type chip packaging structure 400 of the chip structure 300 that has more than three.
In addition, in other embodiments of the invention, the electrical connection between chip structure 300a, 300b and the circuit substrate 410 more can be as shown in Figure 6, and it illustrates the schematic diagram into the stack type chip packaging structure of another embodiment of the present invention.Please consult Fig. 5 and shown in Figure 6 jointly, main difference is that the end of lead 420a is the first weld pad 212a or the 3rd weld pad 244 that is connected in chip structure 300a between the stack type chip packaging structure 400 of Fig. 6 and the stack type chip packaging structure 400 of Fig. 5, and the other end of lead 420a then is connected in the 4th weld pad 412 of circuit substrate 410.And the end of lead 420b is the first weld pad 212a or the 3rd weld pad 244 that is connected in chip structure 300a, and the other end of lead 420b then is connected in the first weld pad 212a or the 3rd weld pad 244 of chip structure 300b.Thus, just chip structure 300a, 300b can be electrically connected at circuit substrate 410 via lead 420a, 420b.Because the stack type chip packaging structure 400 of Fig. 6 is similar to the stack type chip packaging structure 400 of Fig. 5, just no longer is explained in detail at this.
In addition, present embodiment is except being stacked in chip structure 300a and 300b on the circuit substrate 410, more control chip 440 can be stacked on the chip structure 300b, and expose the wire bonds district 220 of chip structure 300b, and be electrically connected at circuit substrate 410 via lead 420.
Except can piling up, more can pile up between the chip structure 300 of stack type chip packaging structure 400 in other mode with Fig. 5 and mode shown in Figure 6.For example, chip structure 300 for example is to be stacked on the circuit substrate 410 in the mode that is similar to pyramid, and its cutaway view as shown in Figure 7.Certainly, in stack type chip packaging structure shown in Figure 7 400, present embodiment can also be stacked in control chip 440 on these chip structures.
In sum, chip structure proposed by the invention mainly is planning and the reconfiguration line layer via suitable wire bonds district, first weld pad and the 3rd weld pad are concentrated on the single side of chip structure, make chip structure be suitable for via direct other chip structures of carrying in the zone beyond the wire bonds district.Therefore, pile up the stack type chip packaging structure that forms,, just can have thin thickness, and have higher encapsulation integration compared to known techniques via the said chip structure.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (10)
1, a kind of chip structure is characterized in that it comprises:
One chip body, has a wire bonds zone, this wire bonds zone is single side or the adjacent dual-side that is adjacent to this chip body, and wherein this chip body has a plurality of first weld pad and a plurality of extra-regional second weld pads of this wire bonds that are positioned at that are positioned at this wire bonds zone;
One first protective layer is disposed on this chip body, and wherein this first protective layer has a plurality of first openings, to expose those first weld pads and those second weld pads;
One reconfiguration line layer is disposed on this first protective layer, and wherein this reconfiguration line layer extends in this wire bonds zone from those second weld pads, and this reconfiguration line layer has a plurality of the 3rd weld pads that are positioned at this wire bonds zone; And
One second protective layer is covered on this reconfiguration line layer, and wherein this second protective layer has a plurality of second openings, to expose those first weld pads and those the 3rd weld pads.
2, chip structure according to claim 1 is characterized in that the material of wherein said reprovision line layer comprises gold, copper, nickel, titanizing tungsten or titanium.
3, chip structure according to claim 1 is characterized in that wherein those first weld pads and those second weld pads are so that kenel or face array kenel are arranged on this chip body on every side.
4, chip structure according to claim 1 is characterized in that those first weld pads wherein and those the 3rd weld pads are arranged at least one row along the single side of this chip body.
5, a kind of stack chip packaging structure is characterized in that it comprises:
One circuit substrate;
A plurality of chip structures, each those chip structure comprises:
One chip body, has a wire bonds zone, this wire bonds zone is single side or the adjacent dual-side that is adjacent to this chip body, and wherein this chip body has a plurality of first weld pad and a plurality of extra-regional second weld pads of this wire bonds that are positioned at that are positioned at this wire bonds zone;
One first protective layer is disposed on this chip body, and wherein this first protective layer has a plurality of first openings, to expose those first weld pads and those second weld pads;
One reconfiguration line layer is disposed on this first protective layer, and wherein this reconfiguration line layer extends in this wire bonds zone from those second weld pads, and this reconfiguration line layer has a plurality of the 3rd weld pads that are positioned at this wire bonds zone; And
One second protective layer, be covered on this reconfiguration line layer, wherein this second protective layer has a plurality of second openings, to expose those first weld pads and those the 3rd weld pads, wherein those chip structures are interlaced with each other piling up, to expose this wire bonds zone of each those chip structure; And
Many leads are connected in those chip structures and this circuit substrate, so that those chip structures are electrically connected at this circuit substrate.
6, stack chip packaging structure according to claim 5, an end that it is characterized in that those leads are to be connected to those first weld pads or those the 3rd weld pads, and the other end of those leads is connected to this circuit substrate.
7, stack chip packaging structure according to claim 5, it is characterized in that those leads more comprise many first leads and many second leads, wherein the two ends of each those first lead are those first weld pads or those the 3rd weld pads that are connected to adjacent two chip structures, and the two ends of each those second lead connect this circuit substrate and those first weld pads or those the 3rd weld pads that are adjacent to this chip structure of this circuit substrate respectively.
8, stack chip packaging structure according to claim 5, it is characterized in that it more comprises a control chip, be disposed on this chip structure of the superiors, with this wire bonds district of this chip structure of exposing the superiors, and this control chip is to be electrically connected to this circuit substrate via those leads.
9, stack chip packaging structure according to claim 5 is characterized in that wherein those first weld pads and those second weld pads of those chip structures are so that kenel or face array kenel are arranged on this chip body on every side.
10, chip structure according to claim 5 is characterized in that those first weld pads of those chip structures wherein and those the 3rd weld pads are arranged at least one row along the single side of this chip body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101080964A CN100449743C (en) | 2005-09-29 | 2005-09-29 | Chip structure and stacked chip packing structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101080964A CN100449743C (en) | 2005-09-29 | 2005-09-29 | Chip structure and stacked chip packing structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1941343A true CN1941343A (en) | 2007-04-04 |
| CN100449743C CN100449743C (en) | 2009-01-07 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101388385B (en) * | 2007-09-14 | 2010-06-09 | 联发科技股份有限公司 | Semiconductor device |
| CN103663362A (en) * | 2012-08-29 | 2014-03-26 | 飞思卡尔半导体公司 | Sensor packaging method and sensor package |
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| US10276545B1 (en) * | 2018-03-27 | 2019-04-30 | Powertech Technology Inc. | Semiconductor package and manufacturing method thereof |
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| JP3471270B2 (en) * | 1999-12-20 | 2003-12-02 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor device |
| JP2001230348A (en) * | 2000-02-18 | 2001-08-24 | Hitachi Ltd | Semiconductor device |
| CN1265452C (en) * | 2002-04-02 | 2006-07-19 | 台湾积体电路制造股份有限公司 | Metal welding pad of integrated circuit and method for making the same |
| JP2004253609A (en) * | 2003-02-20 | 2004-09-09 | Kawasaki Microelectronics Kk | Semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101388385B (en) * | 2007-09-14 | 2010-06-09 | 联发科技股份有限公司 | Semiconductor device |
| CN103663362A (en) * | 2012-08-29 | 2014-03-26 | 飞思卡尔半导体公司 | Sensor packaging method and sensor package |
| CN103663362B (en) * | 2012-08-29 | 2016-12-28 | 飞思卡尔半导体公司 | Sensor packaging method and sensor encapsulation |
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