TWI594379B - Semiconductor package and a method for fabricating the same - Google Patents
Semiconductor package and a method for fabricating the same Download PDFInfo
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- TWI594379B TWI594379B TW103120463A TW103120463A TWI594379B TW I594379 B TWI594379 B TW I594379B TW 103120463 A TW103120463 A TW 103120463A TW 103120463 A TW103120463 A TW 103120463A TW I594379 B TWI594379 B TW I594379B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Description
本發明係有關於一種半導體封裝件及其製法，尤指一種晶片尺寸封裝件型式的半導體封裝件及其製法。 The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package of a wafer size package type and a method of fabricating the same.
隨著半導體技術的演進，已開發出半導體產品的不同封裝產品型態，而為了追求半導體封裝件之輕薄短小，因而發展出一種晶片尺寸封裝件(Chip Scale Package，CSP)，其特徵在於此種晶片尺寸封裝件僅具有與晶片尺寸相等或略大的尺寸。 With the evolution of semiconductor technology, different package product types of semiconductor products have been developed, and in order to pursue the thinness and thinness of semiconductor packages, a chip scale package (CSP) has been developed, which is characterized by The wafer size package only has dimensions that are equal or slightly larger than the wafer size.
第1A至1I圖所示者，係習知半導體封裝件之製法的剖視圖。 1A to 1I are cross-sectional views showing a method of manufacturing a conventional semiconductor package.
如第1A圖所示，提供一第一承載板10，並於其上形成離型層11。 As shown in Fig. 1A, a first carrier plate 10 is provided and a release layer 11 is formed thereon.
如第1B圖所示，於該離型層11上以覆晶方式設置複數具有相對之作用面12a與非作用面12b的半導體晶片12，令該半導體晶片12以其作用面12a接置於該離型層11上。 As shown in FIG. 1B, a plurality of semiconductor wafers 12 having opposing active and unaffected surfaces 12a and 12b are provided on the release layer 11 in a flip chip manner, and the semiconductor wafer 12 is placed on the active surface 12a. On the release layer 11.
如第1C圖所示，於該離型層11上形成封裝膠體13， 以包覆該等半導體晶片12，並經過固化(curing)步驟以使該封裝膠體13固化，該封裝膠體13具有連接該離型層11的第一表面13a及與其相對之第二表面13b。 As shown in FIG. 1C, an encapsulant 13 is formed on the release layer 11. The semiconductor wafer 12 is coated and subjected to a curing step to cure the encapsulant 13, the encapsulant 13 having a first surface 13a connecting the release layer 11 and a second surface 13b opposite thereto.
如第1D圖所示，研磨該封裝膠體13，以使該半導體晶片12之非作用面12b外露於該封裝膠體13之第二表面13b。 As shown in FIG. 1D, the encapsulant 13 is polished to expose the non-active surface 12b of the semiconductor wafer 12 to the second surface 13b of the encapsulant 13.
如第1E圖所示，於該封裝膠體13之第二表面13b與該半導體晶片12的非作用面12b上依序接置黏著層14與第二承載板15。 As shown in FIG. 1E, the adhesive layer 14 and the second carrier 15 are sequentially disposed on the second surface 13b of the encapsulant 13 and the inactive surface 12b of the semiconductor wafer 12.
如第1F圖所示，移除該第一承載板10與離型層11，以外露該封裝膠體13之第一表面13a與該半導體晶片12的作用面12a。 As shown in FIG. 1F, the first carrier 10 and the release layer 11 are removed, and the first surface 13a of the encapsulant 13 and the active surface 12a of the semiconductor wafer 12 are exposed.
如第1G圖所示，於該封裝膠體13之第一表面13a與該半導體晶片12之作用面12a上形成電性連接該半導體晶片12的線路層16，並於該線路層16上形成複數導電元件17。 As shown in FIG. 1G, a wiring layer 16 electrically connected to the semiconductor wafer 12 is formed on the first surface 13a of the encapsulant 13 and the active surface 12a of the semiconductor wafer 12, and a plurality of conductive layers are formed on the wiring layer 16. Element 17.
如第1H圖所示，使第1G圖之結構以其導電元件17接置於一膠膜18上，並移除該黏著層14與第二承載板15，且徹底清除殘留之該黏著層14，再進行切單步驟。 As shown in FIG. 1H, the structure of the 1Gth image is placed on the adhesive film 18 with its conductive member 17, and the adhesive layer 14 and the second carrier 15 are removed, and the remaining adhesive layer 14 is completely removed. Then perform the singulation step.
如第1I圖所示，於該封裝膠體13之第二表面13b與該半導體晶片12的非作用面12b上依序接置散熱膏19與散熱片20。 As shown in FIG. 1I, the thermal grease 19 and the heat sink 20 are sequentially disposed on the second surface 13b of the encapsulant 13 and the non-active surface 12b of the semiconductor wafer 12.
惟，前述習知半導體封裝件之製程較為複雜，進而增加整體製程成本及時間。 However, the process of the aforementioned conventional semiconductor package is complicated, thereby increasing the overall process cost and time.
因此，如何避免上述習知技術中之種種問題，實為目前業界所急需解決的課題。 Therefore, how to avoid various problems in the above-mentioned prior art is an urgent problem to be solved in the industry.
有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件，係包括：板體；至少一半導體晶片，係設於該板體上，並具有相對之作用面與非作用面，且令該半導體晶片以其非作用面連接該板體；封裝膠體，係形成於該板體上，並包覆該半導體晶片，該封裝膠體具有相對之第一表面與第二表面，且令該封裝膠體以其第二表面連接該板體；線路層，係形成於該半導體晶片之作用面上與該封裝膠體之第一表面上，以電性連接該半導體晶片；以及至少一導電通孔，係貫穿該封裝膠體，以電性連接該線路層與板體。 In view of the above-mentioned deficiencies of the prior art, the present invention provides a semiconductor package comprising: a board; at least one semiconductor wafer is disposed on the board and has opposite active and non-active surfaces, and The semiconductor wafer is connected to the board body by an inactive surface thereof; the encapsulant is formed on the board body and covers the semiconductor wafer, the encapsulant has opposite first and second surfaces, and the encapsulant is The second surface is connected to the board; the circuit layer is formed on the active surface of the semiconductor wafer and the first surface of the encapsulant to electrically connect the semiconductor wafer; and at least one conductive via extends through the The encapsulant is electrically connected to the circuit layer and the board.
於前述之半導體封裝件中，該作用面與非作用面係分別外露於該第一表面與第二表面，復包括導熱層，係形成於該板體與該半導體晶片之非作用面之間及該板體與該封裝膠體之第二表面之間，且該板體係為散熱板或天線板。 In the above semiconductor package, the active surface and the inactive surface are respectively exposed on the first surface and the second surface, and the heat conducting layer is formed between the board and the non-active surface of the semiconductor wafer and The plate body is between the second surface of the encapsulant and the plate system is a heat sink or an antenna plate.
於本發明中，復包括複數導電元件，係形成於該線路層上，該板體係為氧化鋁板，且該封裝膠體之側表面係與該板體之側表面齊平。 In the present invention, a plurality of conductive elements are formed on the circuit layer, the plate system is an alumina plate, and a side surface of the encapsulant is flush with a side surface of the plate body.
本發明復提供一種半導體封裝件之製法，係包括：於一承載板上設置至少一具有相對之作用面與非作用面的半導體晶片，令該半導體晶片以其作用面接置於該承載板上；於該承載板上形成包覆該半導體晶片的封裝膠體，該 封裝膠體具有相對之第一表面與第二表面，且令該封裝膠體以其第一表面連接該承載板；於該封裝膠體之第二表面上接置板體；移除該承載板，以外露該半導體晶片的作用面與該封裝膠體之第一表面；以及形成貫穿該封裝膠體之至少一導電通孔，並於該半導體晶片之作用面上與該封裝膠體之第一表面上形成電性連接該半導體晶片的線路層，以令該導電通孔電性連接該線路層與板體。 The invention provides a method for fabricating a semiconductor package, comprising: disposing at least one semiconductor wafer having opposite active and non-active surfaces on a carrier plate, and placing the semiconductor wafer on the carrier plate with its active surface; Forming an encapsulant covering the semiconductor wafer on the carrier board, The encapsulant has a first surface and a second surface opposite to each other, and the encapsulant is connected to the carrier by a first surface thereof; the board is attached to the second surface of the encapsulant; and the carrier is removed and exposed a working surface of the semiconductor wafer and the first surface of the encapsulant; and forming at least one conductive via extending through the encapsulant and electrically connecting to the first surface of the encapsulant on the active surface of the semiconductor wafer The circuit layer of the semiconductor wafer is such that the conductive via is electrically connected to the circuit layer and the board.
於前述之半導體封裝件之製法中，該作用面與非作用面係分別外露於該第一表面與第二表面，該板體上復形成有導熱層，且該板體係藉由該導熱層接置於該半導體晶片之非作用面與該封裝膠體之第二表面上，於形成該線路層之後，復包括進行切單步驟，且於進行該切單步驟之後，該封裝膠體之側表面係與該板體之側表面齊平。 In the above method for manufacturing a semiconductor package, the active surface and the non-active surface are respectively exposed on the first surface and the second surface, and the heat dissipation layer is formed on the plate body, and the plate system is connected by the heat conduction layer. Placed on the non-active surface of the semiconductor wafer and the second surface of the encapsulant, after forming the circuit layer, including performing a singulation step, and after performing the singulation step, the side surface of the encapsulant is The side surface of the plate body is flush.
本發明之半導體封裝件之製法中，復包括於該線路層上形成複數導電元件，且於形成該封裝膠體之後，復包括從該封裝膠體之第二表面移除部分厚度之該封裝膠體，以外露該非作用面。 In the method of fabricating a semiconductor package of the present invention, a plurality of conductive elements are formed on the circuit layer, and after forming the encapsulant, the encapsulant is removed from a second surface of the encapsulant. Expose the non-active surface.
所述之製法中，於設置該半導體晶片之前，該承載板上復形成有離型層，令該半導體晶片以其作用面接置於該離型層上，且移除該承載板復包括移除該離型層，該板體係為散熱板或天線板，該板體係為氧化鋁板。 In the manufacturing method, before the semiconductor wafer is disposed, the carrier plate is formed with a release layer, so that the semiconductor wafer is placed on the release layer with its active surface, and removing the carrier plate includes removing The release layer, the plate system is a heat sink or an antenna plate, and the plate system is an alumina plate.
由上可知，本發明係以板體做為半導體封裝件的支撐與握持之用，且該板體亦可同時當作散熱片，因此本發明無須使用第二承載板及其上的黏著層且無須再於最後進行 接置散熱片的步驟，並能省去清除殘留之該黏著層的步驟，進而縮短製程步驟與降低成本；此外，本發明可藉由導電通孔電性連接半導體晶片與板體，俾使該板體亦可當作天線來使用。 It can be seen from the above that the present invention uses the plate body as the support and holding of the semiconductor package, and the plate body can also serve as the heat sink at the same time, so the invention does not need to use the second carrier plate and the adhesive layer thereon. And no longer need to do it at the end The step of arranging the heat sink and eliminating the step of removing the residual adhesive layer, thereby shortening the process steps and reducing the cost; further, the present invention can electrically connect the semiconductor wafer and the board body through the conductive vias, thereby enabling the The board can also be used as an antenna.
10‧‧‧第一承載板 10‧‧‧First carrier board
11、31‧‧‧離型層 11, 31‧‧‧ release layer
12、32‧‧‧半導體晶片 12, 32‧‧‧ semiconductor wafer
12a、32a‧‧‧作用面 12a, 32a‧‧‧ action surface
12b、32b‧‧‧非作用面 12b, 32b‧‧‧ non-active surface
13、33‧‧‧封裝膠體 13, 33‧‧‧Package colloid
13a、33a‧‧‧第一表面 13a, 33a‧‧‧ first surface
13b、33b‧‧‧第二表面 13b, 33b‧‧‧ second surface
14‧‧‧黏著層 14‧‧‧Adhesive layer
15‧‧‧第二承載板 15‧‧‧Second carrier board
16、37‧‧‧線路層 16, 37‧‧‧ circuit layer
17、38‧‧‧導電元件 17, 38‧‧‧ conductive elements
18‧‧‧膠膜 18‧‧‧film
19‧‧‧散熱膏 19‧‧‧ Thermal grease
20‧‧‧散熱片 20‧‧‧ Heat sink
30‧‧‧承載板 30‧‧‧Loading board
34‧‧‧導熱層 34‧‧‧thermal layer
35‧‧‧板體 35‧‧‧ board
36‧‧‧通孔 36‧‧‧through hole
361‧‧‧導電通孔 361‧‧‧Electrical through hole
第1A至1I圖所示者係習知半導體封裝件之製法的剖視圖；以及第2A至2I圖所示者係本發明之半導體封裝件之製法的剖視圖，其中，第2I’圖係第2I圖之另一實施態樣。 1A to 1I are cross-sectional views showing a method of fabricating a conventional semiconductor package; and FIGS. 2A to 2I are cross-sectional views showing a method of fabricating the semiconductor package of the present invention, wherein the 2I' figure is a 2I. Another implementation aspect.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之用語亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terminology used in the present specification is only for the purpose of illustration, and is not intended to limit the scope of the invention. The change or adjustment of the relative relationship is also considered as The scope of the invention can be implemented.
第2A至2I圖所示者，係本發明之半導體封裝件之製 法的剖視圖，其中，第2I’圖係第2I圖之另一實施態樣。 2A to 2I, which is a system for manufacturing a semiconductor package of the present invention A cross-sectional view of the method in which the second embodiment is a second embodiment of the second embodiment.
如第2A圖所示，於一承載板30上視需要形成離型層31。 As shown in FIG. 2A, a release layer 31 is formed on a carrier sheet 30 as needed.
如第2B圖所示，於該離型層31上設置至少一具有相對之作用面32a與非作用面32b的半導體晶片32，令該半導體晶片32以其作用面32a接置於該離型層31上。 As shown in FIG. 2B, at least one semiconductor wafer 32 having an opposite active surface 32a and an inactive surface 32b is disposed on the release layer 31, and the semiconductor wafer 32 is placed on the release layer with its active surface 32a. 31.
如第2C圖所示，於該離型層31上形成包覆該半導體晶片32的封裝膠體33，該封裝膠體33具有相對之第一表面33a與第二表面33b，且令該封裝膠體33以其第一表面33a連接該離型層31。 As shown in FIG. 2C, an encapsulant 33 covering the semiconductor wafer 32 is formed on the release layer 31. The encapsulant 33 has a first surface 33a and a second surface 33b opposite to each other, and the encapsulant 33 is Its first surface 33a is connected to the release layer 31.
如第2D圖所示，藉由例如研磨方式從該封裝膠體33之第二表面33b移除部分厚度之該封裝膠體33，以外露該非作用面32b，此時，該作用面32a與非作用面32b係分別外露於該第一表面33a與第二表面33b。要特別注意的是，此處移除部分厚度之該封裝膠體33之步驟並非必要。 As shown in FIG. 2D, the portion of the encapsulant 33 is removed from the second surface 33b of the encapsulant 33 by, for example, polishing, and the non-active surface 32b is exposed. At this time, the active surface 32a and the non-active surface are exposed. 32b is exposed to the first surface 33a and the second surface 33b, respectively. It is to be particularly noted that the step of removing a portion of the thickness of the encapsulant 33 herein is not necessary.
如第2E圖所示，於該半導體晶片32之非作用面32b與該封裝膠體33之第二表面33b上接置其上形成有導熱層34的板體35，該導熱層34可為散熱膏，且該板體35係藉由該導熱層34接置於該半導體晶片32之非作用面32b與該封裝膠體33之第二表面33b上，該板體35可為氧化鋁板，且該板體35可為散熱板或天線板。 As shown in FIG. 2E, a plate body 35 having a heat conductive layer 34 formed thereon is disposed on the non-acting surface 32b of the semiconductor wafer 32 and the second surface 33b of the encapsulant 33. The heat conductive layer 34 may be a thermal grease. The plate 35 is attached to the non-active surface 32b of the semiconductor wafer 32 and the second surface 33b of the encapsulant 33 by the heat conducting layer 34. The plate 35 may be an alumina plate, and the plate body 35 can be a heat sink or an antenna board.
如第2F圖所示，移除該承載板30與離型層31，以外露該半導體晶片32的作用面32a與該封裝膠體33之第一表面33a。 As shown in FIG. 2F, the carrier plate 30 and the release layer 31 are removed, and the active surface 32a of the semiconductor wafer 32 and the first surface 33a of the encapsulant 33 are exposed.
如第2G圖所示，形成貫穿該封裝膠體33與導熱層34的至少一通孔36。 As shown in FIG. 2G, at least one through hole 36 penetrating the encapsulant 33 and the heat conductive layer 34 is formed.
如第2H圖所示，於該通孔36中形成導電通孔361，並於該半導體晶片32之作用面32a上與該封裝膠體33之第一表面33a上形成電性連接該半導體晶片32的線路層37，該導電通孔361電性連接該線路層37與板體35，且於該線路層37上形成複數導電元件38。 As shown in FIG. 2H, a conductive via 361 is formed in the via hole 36, and the semiconductor wafer 32 is electrically connected to the first surface 33a of the encapsulant 33 on the active surface 32a of the semiconductor wafer 32. The conductive layer 361 is electrically connected to the circuit layer 37 and the board 35, and a plurality of conductive elements 38 are formed on the circuit layer 37.
如第2I圖所示，進行切單步驟，該封裝膠體33之側表面係與該板體35之側表面齊平；該切單步驟亦可於形成該等導電元件38之前進行。 As shown in FIG. 2I, the singulation step is performed, and the side surface of the encapsulant 33 is flush with the side surface of the plate body 35; the singulation step can also be performed before the formation of the conductive elements 38.
或者，如第2I’圖所示，其係不進行第2D圖之步驟時的最終結構。 Alternatively, as shown in Fig. 2I', it is the final structure when the step of the 2D diagram is not performed.
本發明復提供一種半導體封裝件，其包括：板體35；至少一半導體晶片32，係設於該板體35上，並具有相對之作用面32a與非作用面32b，且令該半導體晶片32以其非作用面32b連接該板體35；封裝膠體33，係形成於該板體35上，並包覆該半導體晶片32，該封裝膠體33具有相對之第一表面33a與第二表面33b，且令該封裝膠體33以其第二表面33b連接該板體35；線路層37，係形成於該半導體晶片32之作用面32a上與該封裝膠體33之第一表面33a上，以電性連接該半導體晶片32；以及至少一導電通孔361，係貫穿該封裝膠體33，以電性連接該線路層37與板體35。 The present invention further provides a semiconductor package comprising: a plate body 35; at least one semiconductor wafer 32 is disposed on the plate body 35, and has an opposite active surface 32a and an inactive surface 32b, and the semiconductor wafer 32 is provided. The plate body 35 is connected to the non-active surface 32b. The encapsulant 33 is formed on the plate body 35 and covers the semiconductor wafer 32. The encapsulant 33 has a first surface 33a and a second surface 33b opposite to each other. The package body 33 is connected to the board body 35 by the second surface 33b. The circuit layer 37 is formed on the active surface 32a of the semiconductor wafer 32 and electrically connected to the first surface 33a of the encapsulant 33. The semiconductor wafer 32 and the at least one conductive via 361 extend through the encapsulant 33 to electrically connect the circuit layer 37 and the board 35.
於前述之半導體封裝件中，該作用面32a與非作用面 32b係分別外露於該第一表面33a與第二表面33b，復包括導熱層34，係形成於該板體35與該半導體晶片32之非作用面32b之間及該板體35與該封裝膠體33之第二表面33b之間，且該板體35係為散熱板或天線板。 In the foregoing semiconductor package, the active surface 32a and the non-active surface 32b is exposed on the first surface 33a and the second surface 33b, respectively, and includes a heat conductive layer 34 formed between the plate body 35 and the non-active surface 32b of the semiconductor wafer 32, and the plate body 35 and the encapsulant Between the second surface 33b of the 33, and the plate 35 is a heat sink or an antenna plate.
於本實施例中，復包括複數導電元件38，係形成於該線路層37上，該板體35係為氧化鋁板，且該封裝膠體33之側表面係與該板體35之側表面齊平。 In this embodiment, a plurality of conductive elements 38 are formed on the circuit layer 37. The plate body 35 is an alumina plate, and the side surface of the encapsulant 33 is flush with the side surface of the plate body 35. .
綜上所述，相較於習知技術，由於本發明係以板體做為半導體封裝件的支撐與握持之用，且該板體亦可同時當作散熱片，因此本發明無須使用第二承載板及其上的黏著層且無須再於最後進行接置散熱片的步驟，進而縮短製程步驟與降低成本；此外，因為本發明無須使用用以接合該第二承載板的該黏著層，所以能省去清除殘留之該黏著層的步驟，以進一步降低製程時間與成本；再者，本發明可藉由導電通孔電性連接半導體晶片與板體，俾使該板體亦可當作天線來使用。 In summary, compared with the prior art, the present invention uses the board as the support and holding of the semiconductor package, and the board can also be used as a heat sink at the same time, so the invention does not need to use the first The second carrier board and the adhesive layer thereon do not need to be further connected to the heat sink, thereby shortening the process steps and reducing the cost; moreover, because the invention does not need to use the adhesive layer for bonding the second carrier board, Therefore, the step of removing the residual adhesive layer can be omitted to further reduce the processing time and cost; further, the present invention can electrically connect the semiconductor wafer and the board body through the conductive via, so that the board can also be regarded as Antenna to use.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
32‧‧‧半導體晶片 32‧‧‧Semiconductor wafer
33‧‧‧封裝膠體 33‧‧‧Package colloid
34‧‧‧導熱層 34‧‧‧thermal layer
35‧‧‧板體 35‧‧‧ board
361‧‧‧導電通孔 361‧‧‧Electrical through hole
37‧‧‧線路層 37‧‧‧Line layer
38‧‧‧導電元件 38‧‧‧Conducting components
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