TW201448163A - Semiconductor package and method of manufacture - Google Patents
Semiconductor package and method of manufacture Download PDFInfo
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- TW201448163A TW201448163A TW102120066A TW102120066A TW201448163A TW 201448163 A TW201448163 A TW 201448163A TW 102120066 A TW102120066 A TW 102120066A TW 102120066 A TW102120066 A TW 102120066A TW 201448163 A TW201448163 A TW 201448163A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 132
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims description 14
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 33
- 229910000679 solder Inorganic materials 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 16
- 239000012790 adhesive layer Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 description 69
- 238000006073 displacement reaction Methods 0.000 description 5
- 238000003466 welding Methods 0.000 description 5
- 239000000084 colloidal system Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
本發明係有關於一種半導體封裝件及其製法，尤指一種具有堆疊的半導體晶片之半導體封裝件及其製法。 The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package having a stacked semiconductor wafer and a method of fabricating the same.
隨著半導體技術的演進，目前已開發出不同封裝型態的半導體封裝件，而為了追求半導體封裝件之輕薄短小，遂發展出晶片尺寸封裝件(chip scale package，CSP)之技術，其特徵在於此種晶片尺寸封裝件僅具有與晶片尺寸相等或略大的尺寸。 With the evolution of semiconductor technology, semiconductor packages of different package types have been developed, and in order to pursue the thinness and thinness of semiconductor packages, a chip scale package (CSP) technology has been developed, which is characterized in that Such wafer size packages only have dimensions that are equal or slightly larger than the size of the wafer.
第1A至1F圖所示者，係習知第7202107號美國專利之晶片尺寸封裝件及其製法的剖視圖。 1A to 1F are cross-sectional views of a wafer-sized package of U.S. Patent No. 7,202,107 and a method of manufacturing the same.
如第1A圖所示，首先，提供一承載板10。 As shown in FIG. 1A, first, a carrier board 10 is provided.
如第1B圖所示，接者，於該承載板10上形成一熱感性黏著層11。 As shown in FIG. 1B, a heat-sensitive adhesive layer 11 is formed on the carrier 10 .
如第1C圖所示，貼合複數具有作用面12a之半導體晶片12於該熱感性黏著層11上，該作用面12a上具有複數電極墊121，且該半導體晶片12係以其作用面12a貼附於該熱感性黏著層11上。 As shown in FIG. 1C, a plurality of semiconductor wafers 12 having an active surface 12a are bonded to the thermally sensitive adhesive layer 11, the active surface 12a having a plurality of electrode pads 121, and the semiconductor wafer 12 is attached with its active surface 12a. Attached to the heat-sensitive adhesive layer 11.
如第1D圖所示，於該熱感性黏著層11上形成封裝膠體13，以使該封裝膠體13完全包覆該半導體晶片12。 As shown in FIG. 1D, an encapsulant 13 is formed on the thermally inductive adhesive layer 11 so that the encapsulant 13 completely covers the semiconductor wafer 12.
如第1E圖所示，之後進行加熱步驟，以使該半導體晶片12及封裝膠體13完全與該熱感性黏著層11分離。 As shown in FIG. 1E, a heating step is then performed to completely separate the semiconductor wafer 12 and the encapsulant 13 from the thermally sensitive adhesive layer 11.
如第1F圖所示，最後，於半導體晶片12之作用面12a及同側之封裝膠體13表面上形成線路層14。後續可視需要進行切單作業(未圖示)，以完成一不具封裝基板之封裝件。 As shown in FIG. 1F, finally, the wiring layer 14 is formed on the active surface 12a of the semiconductor wafer 12 and the surface of the encapsulant 13 on the same side. A subsequent singulation operation (not shown) may be performed to complete a package without a package substrate.
惟，前述習知封裝件如要增進產品多工性或功能時，則需在一封裝件中包含有複數半導體晶片。在複數半導體晶片相鄰設置的情況下，會大幅增加封裝件之平面尺寸；此外，因為有熱製程及封裝膠體填充等製程(例如將封裝膠體加熱成液體並灌入)，所以半導體晶片會有位移發生，而無論複數半導體晶片的尺寸是否相同，都難以讓每個半導體晶片的位移一致，進而導致後續線路增層製程之對位發生問題。 However, if the aforementioned conventional package is to improve product multiplexability or function, it is necessary to include a plurality of semiconductor wafers in one package. In the case where a plurality of semiconductor wafers are disposed adjacent to each other, the planar size of the package is greatly increased; in addition, because of processes such as thermal processing and encapsulation of the encapsulant (for example, heating the encapsulant into a liquid and filling it), the semiconductor wafer will have Displacement occurs, and regardless of whether the dimensions of the plurality of semiconductor wafers are the same, it is difficult to make the displacement of each semiconductor wafer uniform, thereby causing problems in the alignment of the subsequent line build-up process.
因此，如何解決封裝件的平面尺寸過大及同一封裝件中的複數半導體晶片的位移不相同等問題，實已成為目前業界所急需解決的課題。 Therefore, how to solve the problem that the planar size of the package is too large and the displacement of the plurality of semiconductor wafers in the same package is not the same has become an urgent problem to be solved in the industry.
有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件，係包括：第一半導體晶片，係具有相對之第一作用面與第一非作用面，且該第一作用面上形成有複數第一電極墊；第二半導體晶片，係具有相對之第二作用面與第 二非作用面，該第二作用面上形成有複數第二電極墊，且該第二半導體晶片係藉其第二非作用面接置於該第一半導體晶片之第一非作用面上；封裝膠體，係包覆該第一半導體晶片與第二半導體晶片，且具有相對之第一表面與第二表面，該第一作用面並係外露於該封裝膠體之第一表面；複數打線墊，係嵌埋且外露於該封裝膠體之第一表面；第一子銲線，係嵌埋於該封裝膠體中，且其兩端係分別連接該第二電極墊與外露於該第二表面；第二子銲線，係嵌埋於該封裝膠體中，且其兩端係分別連接該打線墊與外露於該第二表面；第一增層結構，係形成於該第一表面上，部分該第一增層結構電性連接該第一電極墊，部分該第一增層結構電性連接該打線墊；以及第二增層結構，係形成於該第二表面上，且部分該第二增層結構藉由該第一子銲線電性連接該第二電極墊，部分該第二增層結構藉由該第二子銲線電性連接該打線墊。 In view of the above-mentioned deficiencies of the prior art, the present invention provides a semiconductor package comprising: a first semiconductor wafer having a first active surface and a first non-active surface, and the first active surface is formed with a plurality of a first electrode pad; the second semiconductor wafer has a second active surface and a second a second non-active surface, the second active surface is formed with a plurality of second electrode pads, and the second semiconductor wafer is attached to the first non-active surface of the first semiconductor wafer by the second non-active surface; the encapsulant And covering the first semiconductor wafer and the second semiconductor wafer, and having opposite first and second surfaces, the first active surface is exposed on the first surface of the encapsulant; the plurality of wire mats are embedded Buried and exposed on the first surface of the encapsulant; the first sub-bonding wire is embedded in the encapsulant, and the two ends are respectively connected to the second electrode pad and exposed on the second surface; the second sub- The bonding wire is embedded in the encapsulant, and the two ends of the bonding wire are respectively connected to the bonding pad and exposed on the second surface; the first build-up structure is formed on the first surface, and the first increase is partially The layer structure is electrically connected to the first electrode pad, a portion of the first build-up structure is electrically connected to the wire bonding pad; and a second build-up structure is formed on the second surface, and a portion of the second build-up structure is borrowed Electrically connecting the second electric wire by the first sub-bonding wire Pad, the second part by the second sub-layer structure by bonding wires electrically connected to the wire pads.
於前述之半導體封裝件中，該第二半導體晶片之第二非作用面係藉由黏著層黏接至該第一半導體晶片之第一非作用面上。 In the foregoing semiconductor package, the second non-active surface of the second semiconductor wafer is adhered to the first non-active surface of the first semiconductor wafer by an adhesive layer.
依上所述之半導體封裝件，復包括複數導電元件，係電性連接該第一增層結構，且該導電元件係為銲球或銲針。 According to the semiconductor package, the plurality of conductive elements are electrically connected to the first build-up structure, and the conductive element is a solder ball or a solder pin.
本發明復提供一種半導體封裝件之製法，係包括：提供一承載板，其上設有第一半導體晶片與設於該第一半導體晶片上的第二半導體晶片，具有相對之第一作用面與第一非作用面的該第一半導體晶片係以其第一作用面接置於 承載板上，且該第一作用面上形成有複數第一電極墊，該承載板上並形成有複數打線墊，具有相對之第二作用面與第二非作用面之該第二半導體晶片並藉其第二非作用面接置於該第一非作用面上，且該第二作用面上形成有複數第二電極墊；藉由複數銲線電性連接各該第二電極墊與打線墊；於該承載板上形成包覆該第一半導體晶片、第二半導體晶片與銲線的具有相對之第一表面與第二表面之封裝膠體，該第一表面係面向該承載板；從該封裝膠體之第二表面移除部分厚度之該封裝膠體，並將各該銲線截斷成為一端外露之第一子銲線與第二子銲線，該第一子銲線與第二子銲線係分別連接該第二電極墊與打線墊；於該第二表面上形成電性連接該第一子銲線與第二子銲線的第二增層結構；移除該承載板；以及於該第一表面上形成電性連接該第一電極墊與打線墊的第一增層結構。 The invention provides a method for fabricating a semiconductor package, comprising: providing a carrier board having a first semiconductor wafer and a second semiconductor wafer disposed on the first semiconductor wafer, having a first active surface and The first semiconductor wafer of the first inactive surface is placed with its first active surface a plurality of first electrode pads are formed on the first active surface, and the plurality of wire pads are formed on the carrier plate, and the second semiconductor wafer is opposite to the second active surface and the second non-active surface. The second non-active surface is disposed on the first non-active surface, and the second active surface is formed with a plurality of second electrode pads; the second electrode pads and the wire bonding pads are electrically connected by a plurality of bonding wires; Forming an encapsulant having an opposite first surface and a second surface covering the first semiconductor wafer, the second semiconductor wafer and the bonding wire on the carrier board, the first surface facing the carrier board; The second surface removes the thickness of the encapsulant, and cuts each of the bonding wires into a first sub-bonding wire and a second sub-bonding wire which are exposed at one end, and the first sub-bonding wire and the second sub-soldering wire are respectively Connecting the second electrode pad and the wire bonding pad; forming a second build-up structure electrically connecting the first sub-bonding wire and the second sub-bonding wire on the second surface; removing the carrier plate; and the first Electrically connecting the first electrode pad and the wire on the surface First up structure.
所述之半導體封裝件之製法中，提供設置有該第一半導體晶片與第二半導體晶片的承載板之步驟係包括：將具有相對之第一作用面與第一非作用面的該第一半導體晶片以其第一作用面接置於該承載板上；以及於該第一半導體晶片之第一非作用面上接置具有相對之第二作用面與第二非作用面之該第二半導體晶片，該第二半導體晶片並係藉其第二非作用面接置於該第一非作用面上。 In the manufacturing method of the semiconductor package, the step of providing a carrier substrate provided with the first semiconductor wafer and the second semiconductor wafer includes: the first semiconductor having a first active surface and a first non-active surface The wafer is mounted on the carrier plate with its first active surface; and the second semiconductor wafer having the opposite second active surface and the second non-active surface is disposed on the first inactive surface of the first semiconductor wafer, The second semiconductor wafer is attached to the first inactive surface by its second non-active surface.
依前所述之製法，提供設置有該第一半導體晶片與第二半導體晶片的承載板之步驟係包括：將具有相對之第二作用面與第二非作用面之該第二半導體晶片藉其第二非作 用面接置於該第一半導體晶片之第一非作用面上；以及將該第一半導體晶片以其第一作用面接置於該承載板上。 According to the foregoing method, the step of providing the carrier sheet provided with the first semiconductor wafer and the second semiconductor wafer includes: borrowing the second semiconductor wafer having the opposite second active surface and the second non-active surface Second non-made Placed on the first inactive surface of the first semiconductor wafer; and the first semiconductor wafer is placed on the carrier plate with its first active surface.
於前述之半導體封裝件之製法中，該承載板上復形成有剝離層，供該第一半導體晶片藉由該剝離層接置於承載板上，且於移除該承載板時，併同移除該剝離層，且該第二非作用面係藉由黏著層接置於該第一非作用面上。 In the above method for manufacturing a semiconductor package, the carrier board is formed with a peeling layer for the first semiconductor wafer to be placed on the carrier board by the peeling layer, and when the carrier board is removed, In addition to the release layer, the second inactive surface is attached to the first inactive surface by an adhesive layer.
於本發明之半導體封裝件之製法中，復包括於該第一增層結構上電性連接複數導電元件，且該導電元件係為銲球或銲針。 In the manufacturing method of the semiconductor package of the present invention, the plurality of conductive elements are electrically connected to the first build-up structure, and the conductive elements are solder balls or solder pins.
依前所述之半導體封裝件之製法，該承載板係為晶圓或基板，且於形成該第一增層結構之後，復包括切單步驟。 According to the method for manufacturing a semiconductor package as described above, the carrier is a wafer or a substrate, and after forming the first build-up structure, a singulation step is included.
由上可知，由於本發明係堆疊一封裝件中的二半導體晶片，而非相鄰地設置，因此可減少封裝件的平面尺寸；此外，本發明之堆疊的二半導體晶片在製程中的位移將一致，故有利於後續製程之對位步驟，進而增進整體良率。 As can be seen from the above, since the present invention stacks two semiconductor wafers in a package instead of being disposed adjacently, the planar size of the package can be reduced; in addition, the displacement of the stacked two semiconductor wafers of the present invention in the process will be Consistent, it is beneficial to the alignment process of the subsequent process, thereby improving the overall yield.
10、20‧‧‧承載板 10, 20‧‧‧ carrier board
11‧‧‧熱感性黏著層 11‧‧‧Thermal adhesive layer
12‧‧‧半導體晶片 12‧‧‧Semiconductor wafer
12a‧‧‧作用面 12a‧‧‧Action surface
121‧‧‧電極墊 121‧‧‧electrode pads
13‧‧‧封裝膠體 13‧‧‧Package colloid
14‧‧‧線路層 14‧‧‧Line layer
21‧‧‧剝離層 21‧‧‧ peeling layer
22‧‧‧打線墊 22‧‧‧Line mat
23‧‧‧第一半導體晶片 23‧‧‧First semiconductor wafer
23a‧‧‧第一作用面 23a‧‧‧First action surface
23b‧‧‧第一非作用面 23b‧‧‧First non-active surface
231‧‧‧第一電極墊 231‧‧‧First electrode pad
24‧‧‧黏著層 24‧‧‧Adhesive layer
25‧‧‧第二半導體晶片 25‧‧‧Second semiconductor wafer
25a‧‧‧第二作用面 25a‧‧‧second action surface
25b‧‧‧第二非作用面 25b‧‧‧Second non-active surface
251‧‧‧第二電極墊 251‧‧‧Second electrode pad
26‧‧‧銲線 26‧‧‧welding line
261‧‧‧第一子銲線 261‧‧‧The first sub-welding line
262‧‧‧第二子銲線 262‧‧‧Second sub-welding line
27‧‧‧封裝膠體 27‧‧‧Package colloid
27a‧‧‧第一表面 27a‧‧‧ first surface
27b‧‧‧第二表面 27b‧‧‧second surface
28a‧‧‧第一增層結構 28a‧‧‧First buildup structure
28b‧‧‧第二增層結構 28b‧‧‧Second layered structure
29‧‧‧導電元件 29‧‧‧Conducting components
第1A至1F圖所示者係習知第7202107號美國專利之晶片尺寸封裝件及其製法的剖視圖；以及第2A至2T圖所示者係本發明之半導體封裝件及其製法的剖視圖。 1A to 1F are cross-sectional views showing a wafer-sized package of US Pat. No. 7,202,107 and a method of manufacturing the same, and a cross-sectional view showing a semiconductor package of the present invention and a method of manufacturing the same according to FIGS. 2A to 2T.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」及「中」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper" and "in" as used in the specification are merely for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship is changed or adjusted. Substantially changing the technical content is also considered to be within the scope of the invention.
第2A至2I圖所示者，係本發明之半導體封裝件及其製法的剖視圖。 2A to 2I are cross-sectional views showing a semiconductor package of the present invention and a method of manufacturing the same.
如第2A圖所示，於承載板20上形成剝離層(release layer)21，並於該承載板上並形成複數打線墊22，該等打線墊22之形成方式可包括濺鍍與蝕刻步驟。 As shown in FIG. 2A, a release layer 21 is formed on the carrier 20, and a plurality of wire pads 22 are formed on the carrier plate. The wire pads 22 may be formed by a sputtering and etching step.
如第2B圖所示，將具有相對之第一作用面23a與第一非作用面23b的第一半導體晶片23以其第一作用面23a接置於該剝離層21上，其中，該第一作用面23a上形成有複數第一電極墊231，該承載板20係為晶圓或基板。 As shown in FIG. 2B, the first semiconductor wafer 23 having the first active surface 23a and the first non-active surface 23b is placed on the peeling layer 21 with its first active surface 23a, wherein the first A plurality of first electrode pads 231 are formed on the active surface 23a, and the carrier 20 is a wafer or a substrate.
如第2C圖所示，於該第一半導體晶片23之第一非作用面23b上藉由黏著層24(例如貼晶材料(die attach material))接置具有相對之第二作用面25a與第二非作用面25b之第二半導體晶片25，且該第二作用面25a上形成有複數第二電極墊251，該第二半導體晶片25並係藉其第 二非作用面25b接置於該黏著層24上。 As shown in FIG. 2C, the first non-active surface 23b of the first semiconductor wafer 23 is attached to the second active surface 25a by an adhesive layer 24 (for example, a die attach material). a second semiconductor wafer 25 of the second non-active surface 25b, and a plurality of second electrode pads 251 formed on the second active surface 25a, the second semiconductor wafer 25 The second non-active surface 25b is attached to the adhesive layer 24.
如第2D圖所示，藉由複數銲線26電性連接各該第二電極墊251與打線墊22。 As shown in FIG. 2D, each of the second electrode pads 251 and the wire bonding pads 22 are electrically connected by a plurality of bonding wires 26.
如第2E圖所示，於該承載板20上形成包覆該第一半導體晶片23、第二半導體晶片25與銲線26的具有相對之第一表面27a與第二表面27b之封裝膠體27，該第一表面27a係面向該承載板20。 As shown in FIG. 2E, an encapsulant 27 having a first surface 27a and a second surface 27b opposite to the first semiconductor wafer 23, the second semiconductor wafer 25, and the bonding wires 26 is formed on the carrier 20, The first surface 27a faces the carrier plate 20.
如第2F圖所示，以例如研磨方式從該封裝膠體27之第二表面27b移除部分厚度之該封裝膠體27，並將各該銲線26截斷成為一端外露之第一子銲線261與第二子銲線262，該第一子銲線261與第二子銲線262係分別連接該第二電極墊251與打線墊22。 As shown in FIG. 2F, a portion of the thickness of the encapsulant 27 is removed from the second surface 27b of the encapsulant 27 by, for example, grinding, and each of the bonding wires 26 is cut into a first sub-bond 261 exposed at one end. The second sub-bonding wire 262 is connected to the second electrode pad 251 and the wire bonding pad 22 respectively.
如第2G圖所示，於該封裝膠體27之第二表面27b上形成第二增層結構28b，部分該第二增層結構28b電性連接該第一子銲線261，部分該第二增層結構28b電性連接該第二子銲線262，該第一子銲線261可電性連接或不電性連接該第二子銲線262。 As shown in FIG. 2G, a second build-up structure 28b is formed on the second surface 27b of the encapsulant 27, and a portion of the second build-up structure 28b is electrically connected to the first sub-bonding wire 261. The layer structure 28b is electrically connected to the second sub-bonding wire 262. The first sub-bonding wire 261 may be electrically connected or not electrically connected to the second sub-bonding wire 262.
如第2H圖所示，移除該承載板20與剝離層21。 The carrier sheet 20 and the peeling layer 21 are removed as shown in FIG. 2H.
如第2I圖所示，於該封裝膠體27之第一表面27a上形成第一增層結構28a，部分該第一增層結構28a電性連接該第一電極墊231，部分該第一增層結構28a電性連接該打線墊22，該第一電極墊231可電性連接或不電性連接該打線墊22，並於該第一增層結構28a上電性連接複數導電元件29，且該導電元件29可為銲球或銲針，接著，可 視需要地進行切單(singulation)步驟。 As shown in FIG. 2I, a first build-up structure 28a is formed on the first surface 27a of the encapsulant 27, and a portion of the first build-up structure 28a is electrically connected to the first electrode pad 231, and the first build-up layer is partially connected. The structure is electrically connected to the wire pad 22, and the first electrode pad 231 is electrically connected or electrically connected to the wire pad 22, and electrically connected to the plurality of conductive elements 29 on the first build-up structure 28a. The conductive element 29 can be a solder ball or a solder pin, and then The singulation step is performed as needed.
要補充說明的是，第2C圖之結構的製作亦可先將具有相對之第二作用面25a與第二非作用面25b之該第二半導體晶片25藉其第二非作用面25b接置於該第一半導體晶片23之第一非作用面23b上，再將該第一半導體晶片23以其第一作用面23a接置於該承載板20上。其細節並不再贅述。 It should be noted that the structure of FIG. 2C can also be formed by first attaching the second semiconductor wafer 25 having the opposite second active surface 25a and the second non-active surface 25b to the second non-active surface 25b. On the first non-active surface 23b of the first semiconductor wafer 23, the first semiconductor wafer 23 is placed on the carrier 20 with its first active surface 23a. The details are not repeated here.
本發明復提供一種半導體封裝件，係包括：第一半導體晶片23，係具有相對之第一作用面23a與第一非作用面23b，且該第一作用面23a上形成有複數第一電極墊231；第二半導體晶片25，係具有相對之第二作用面25a與第二非作用面25b，該第二作用面25a上形成有複數第二電極墊251，且該第二半導體晶片25係藉其第二非作用面25b接置於該第一半導體晶片23之第一非作用面23b上；封裝膠體27，係包覆該第一半導體晶片23與第二半導體晶片25，且具有相對之第一表面27a與第二表面27b，該第一作用面23a並係外露於該封裝膠體27之第一表面27a；複數打線墊22，係嵌埋且外露於該封裝膠體27之第一表面27a；第一子銲線261，係嵌埋於該封裝膠體27中，且其兩端係分別連接該第二電極墊251與外露於該第二表面27b；第二子銲線262，係嵌埋於該封裝膠體27中，且其兩端係分別連接該打線墊22與外露於該第二表面27b；第一增層結構28a，係形成於該第一表面27a上，部分該第一增層結構28a電性連接該第一電極墊231，部分該第一 增層結構28a電性連接該打線墊22；以及第二增層結構28b，係形成於該第二表面27b上，且部分該第二增層結構28b藉由該第一子銲線261電性連接該第二電極墊251，部分該第二增層結構28b藉由該第二子銲線262電性連接該打線墊22。 The present invention further provides a semiconductor package including a first semiconductor wafer 23 having a first active surface 23a and a first non-active surface 23b, and a plurality of first electrode pads formed on the first active surface 23a. The second semiconductor wafer 25 has a second active surface 25a and a second non-active surface 25b. The second active surface 25a is formed with a plurality of second electrode pads 251, and the second semiconductor wafer 25 is borrowed. The second non-active surface 25b is disposed on the first non-active surface 23b of the first semiconductor wafer 23; the encapsulant 27 covers the first semiconductor wafer 23 and the second semiconductor wafer 25, and has a relative a surface 27a and a second surface 27b, the first active surface 23a is exposed to the first surface 27a of the encapsulant 27; a plurality of wire mats 22 are embedded and exposed on the first surface 27a of the encapsulant 27; The first sub-bonding wire 261 is embedded in the encapsulant 27, and the two ends are respectively connected to the second electrode pad 251 and exposed to the second surface 27b; the second sub-bonding wire 262 is embedded in the second sub-bonding wire 262. The encapsulant 27 is connected to the wire at both ends thereof With 22 exposed from the second surface 27b; 28a first up structure, is formed based on the first surface 27a, the first portion 28a up structure is electrically connected to the first electrode pad 231, the first portion The build-up structure 28a is electrically connected to the wire bonding pad 22; and the second build-up structure 28b is formed on the second surface 27b, and a portion of the second build-up structure 28b is electrically connected by the first sub-bonding wire 261. The second electrode pad 251 is connected to the wire bonding pad 22 by the second sub-bonding wire 262.
於本發明之半導體封裝件中，該第二半導體晶片25之第二非作用面25b係藉由黏著層24黏接至該第一半導體晶片23之第一非作用面23b上。 In the semiconductor package of the present invention, the second non-active surface 25b of the second semiconductor wafer 25 is adhered to the first non-active surface 23b of the first semiconductor wafer 23 by the adhesive layer 24.
依前所述之半導體封裝件，復包括複數導電元件29，係電性連接該第一增層結構28a，且該導電元件29係為銲球或銲針。 The semiconductor package according to the foregoing includes a plurality of conductive elements 29 electrically connected to the first build-up structure 28a, and the conductive elements 29 are solder balls or solder pins.
綜上所述，相較於習知技術，由於本發明係堆疊一封裝件中的二半導體晶片，而非相鄰地設置，因此可減少封裝件的平面尺寸；此外，本發明之堆疊的二半導體晶片在製程中的位移將一致，故有利於後續製程之對位步驟，進而增進整體良率。 In summary, compared with the prior art, since the present invention stacks two semiconductor wafers in a package instead of being disposed adjacently, the planar size of the package can be reduced; moreover, the stacked two of the present invention The displacement of the semiconductor wafer in the process will be consistent, which is beneficial to the alignment process of the subsequent process, thereby improving the overall yield.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
22‧‧‧打線墊 22‧‧‧Line mat
23‧‧‧第一半導體晶片 23‧‧‧First semiconductor wafer
231‧‧‧第一電極墊 231‧‧‧First electrode pad
24‧‧‧黏著層 24‧‧‧Adhesive layer
25‧‧‧第二半導體晶片 25‧‧‧Second semiconductor wafer
261‧‧‧第一子銲線 261‧‧‧The first sub-welding line
262‧‧‧第二子銲線 262‧‧‧Second sub-welding line
27‧‧‧封裝膠體 27‧‧‧Package colloid
27a‧‧‧第一表面 27a‧‧‧ first surface
27b‧‧‧第二表面 27b‧‧‧second surface
28a‧‧‧第一增層結構 28a‧‧‧First buildup structure
28b‧‧‧第二增層結構 28b‧‧‧Second layered structure
29‧‧‧導電元件 29‧‧‧Conducting components
Claims (13)
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| TW102120066A TW201448163A (en) | 2013-06-06 | 2013-06-06 | Semiconductor package and method of manufacture |
| CN201310299694.9A CN104241240B (en) | 2013-06-06 | 2013-07-17 | Method for manufacturing semiconductor package |
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| TWI812124B (en) * | 2022-03-28 | 2023-08-11 | 李銘洛 | Electronic module and carrier structure thereof and manufacturing method thereof |
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| CN104505384A (en) * | 2014-12-30 | 2015-04-08 | 华天科技（西安）有限公司 | Bonding wire embedding fan-in type packaging part and production method thereof |
| CN104538377A (en) * | 2014-12-30 | 2015-04-22 | 华天科技（西安）有限公司 | Fan-out packaging structure based on carrier and preparation method of fan-out packaging structure |
| CN107564889B (en) * | 2017-08-28 | 2020-07-31 | 华进半导体封装先导技术研发中心有限公司 | Chip packaging structure and packaging method |
| CN111863782A (en) * | 2020-07-29 | 2020-10-30 | 济南南知信息科技有限公司 | Communication module and method for manufacturing the same |
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| JP2009088254A (en) * | 2007-09-28 | 2009-04-23 | Toshiba Corp | Electronic component package, and manufacturing method for electronic component package |
| CN101740551A (en) * | 2008-11-21 | 2010-06-16 | 育霈科技股份有限公司 | Laminated die package structure for semiconductor element and method thereof |
| KR101128063B1 (en) * | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | Package-on-package assembly with wire bonds to encapsulation surface |
| TWM449345U (en) * | 2012-11-14 | 2013-03-21 | Walton Advanced Eng Inc | Multi-chip stacked package to avoid chip crack when wire-bonding |
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