CN105321893A - Semiconductor package and fabrication method thereof - Google Patents

Semiconductor package and fabrication method thereof Download PDF

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Publication number
CN105321893A
CN105321893A CN201410311795.8A CN201410311795A CN105321893A CN 105321893 A CN105321893 A CN 105321893A CN 201410311795 A CN201410311795 A CN 201410311795A CN 105321893 A CN105321893 A CN 105321893A
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CN
China
Prior art keywords
plate body
packing colloid
semiconductor wafer
semiconductor package
making
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410311795.8A
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Chinese (zh)
Inventor
陈彦亨
林畯棠
纪杰元
詹慕萱
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN105321893A publication Critical patent/CN105321893A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

A semiconductor package and its preparation method, the semiconductor package includes the plate body, semiconductor wafer, encapsulation colloid, circuit layer and conductive via hole, the semiconductor wafer locates on the plate body, and have relative active surface and non-active surface, the encapsulation colloid forms on the plate body, and wrap the semiconductor wafer, the circuit layer is formed on active surface and encapsulation colloid of the semiconductor wafer, the conductive via hole runs through the encapsulation colloid, in order to connect electrically the circuit layer and plate body. The invention can effectively save the processing time and cost.

Description

Semiconductor package part and method for making thereof
Technical field
The present invention relates to a kind of semiconductor package part and method for making thereof, espespecially a kind of semiconductor package part of chip-size package part pattern and method for making thereof.
Background technology
Along with the evolution of semiconductor technology, the different encapsulating products kenels of semiconductor product are developed, and in order to pursue the compact of semiconductor package part, thus a kind of chip-size package part (ChipScalePackage is developed, CSP), it is characterized in that this kind of chip-size package part only has the size equal or bigger with wafer size.
Figure 1A to Fig. 1 I those shown is the cutaway view of the method for making of existing semiconductor package part.
As shown in Figure 1A, provide one first loading plate 10, and form release layer 11 thereon.
As shown in Figure 1B, on this release layer 11, multiple semiconductor wafer 12 with relative acting surface 12a and non-active face 12b is set to cover crystal type, makes this semiconductor wafer 12 connect with its acting surface 12a and be placed on this release layer 11.
As shown in Figure 1 C, packing colloid 13 is formed on this release layer 11, with these semiconductor wafers 12 coated, and solidify to make this packing colloid 13 through overcuring (curing) step, this packing colloid 13 has the first surface 13a and second surface 13b corresponding thereto that connect this release layer 11.
As shown in figure ip, grind this packing colloid 13, with the second surface 13b making the non-active face 12b of this semiconductor wafer 12 expose to this packing colloid 13.
As referring to figure 1e, sequentially connect on the second surface 13b of this packing colloid 13 and the non-active face 12b of this semiconductor wafer 12 and put adhesion coating 14 and the second loading plate 15.
As shown in fig. 1f, this first loading plate 10 and release layer 11 is removed, with the acting surface 12a of the first surface 13a and this semiconductor wafer 12 that expose this packing colloid 13.
As shown in Figure 1 G, on the first surface 13a of this packing colloid 13 and the acting surface 12a of this semiconductor wafer 12, form the line layer 16 being electrically connected this semiconductor wafer 12, and form multiple conducting element 17 on this line layer 16.
As shown in fig. 1h, the structure of Fig. 1 G is connect with its conducting element 17 and is placed on a glued membrane 18, and remove this adhesion coating 14 and the second loading plate 15, and thoroughly remove this residual adhesion coating 14, then carry out cutting single stage.
As shown in Figure 1 I, sequentially connect on the second surface 13b of this packing colloid 13 and the non-active face 12b of this semiconductor wafer 12 and put thermal grease 19 and fin 20.
Only, the processing procedure of aforementioned existing semiconductor package part is comparatively complicated, and then increases overall process cost and time.
Therefore, how to avoid above-mentioned variety of problems of the prior art, real be badly in need of by current industry the problem of solution.
Summary of the invention
Because the disappearance of above-mentioned prior art, object of the present invention, for providing a kind of semiconductor package part and method for making thereof, can effectively save processing time and cost.
Semiconductor package part of the present invention comprises: plate body; At least one semiconductor wafer, it is located on this plate body, and has relative acting surface and non-active face, and makes this semiconductor wafer connect this plate body with its non-active face; Packing colloid, it is formed on this plate body, and this semiconductor wafer coated, this packing colloid has relative first surface and second surface, and makes this packing colloid connect this plate body with its second surface; Line layer, with on the first surface of this packing colloid on its acting surface being formed at this semiconductor wafer, to be electrically connected this semiconductor wafer; And at least one conductive through hole, it runs through this packing colloid, to be electrically connected this line layer and plate body.
In aforesaid semiconductor package part, this acting surface and non-active face expose to this first surface and second surface respectively, also comprise heat-conducting layer, between its non-active face being formed at this plate body and this semiconductor wafer and between this plate body and second surface of this packing colloid, and this plate body is heating panel or antenna plate.
In the present invention, also comprise multiple conducting element, it is formed on this line layer, and this plate body is alumina plate, and the side surface of this packing colloid flushes with the side surface of this plate body.
The present invention also provides a kind of method for making of semiconductor package part, comprising: on a loading plate, arrange at least one semiconductor wafer with relative acting surface and non-active face, makes this semiconductor wafer connect with its acting surface and is placed on this loading plate; On this loading plate, form the packing colloid of this semiconductor wafer coated, this packing colloid has relative first surface and second surface, and makes this packing colloid connect this loading plate with its first surface; Connect on the second surface of this packing colloid and put plate body; Remove this loading plate, with the first surface of the acting surface and this packing colloid that expose this semiconductor wafer; And form at least one conductive through hole running through this packing colloid, and the line layer being electrically connected this semiconductor wafer is formed on the acting surface of this semiconductor wafer with on the first surface of this packing colloid, be electrically connected this line layer and plate body to make this conductive through hole.
In the method for making of aforesaid semiconductor package part, this acting surface and non-active face expose to this first surface and second surface respectively, this plate body is also formed with heat-conducting layer, and this plate body connects by this heat-conducting layer and is placed on the non-active face of this semiconductor wafer and the second surface of this packing colloid, after this line layer of formation, also comprise and carry out cutting single stage, and after carrying out this and cutting single stage, the side surface of this packing colloid flushes with the side surface of this plate body.
In the method for making of semiconductor package part of the present invention, be also included on this line layer and form multiple conducting element, and after this packing colloid of formation, also comprise this packing colloid removing segment thickness from the second surface of this packing colloid, to expose this non-active face.
In described method for making, before this semiconductor wafer is set, this loading plate is also formed with release layer, making this semiconductor wafer connect with its acting surface is placed on this release layer, and remove this loading plate and also comprise and remove this release layer, this plate body is heating panel or antenna plate, and this plate body is alumina plate.
As from the foregoing, the present invention is with the support of plate body as semiconductor package part and the use of gripping, and this plate body also can be used as fin simultaneously, therefore the present invention need not use the second loading plate and on adhesion coating and need not carry out connecing the step of putting fin in finally again, and the step removing this residual adhesion coating can be saved, and then shorten fabrication steps and reduce costs; In addition, the present invention can be electrically connected semiconductor wafer and plate body by conductive through hole, also can be used as antenna to use to make this plate body.
Accompanying drawing explanation
Figure 1A to Fig. 1 I those shown is the cutaway view of the method for making of existing semiconductor package part.
Fig. 2 A to Fig. 2 I those shown is the cutaway view of the method for making of semiconductor package part of the present invention, wherein, and another embodiment that Fig. 2 I ' is Fig. 2 I.
Symbol description
10 first loading plates
11,31 release layers
12,32 semiconductor wafers
12a, 32a acting surface
12b, 32b non-active face
13,33 packing colloids
13a, 33a first surface
13b, 33b second surface
14 adhesion coatings
15 second loading plates
16,37 line layers
17,38 conducting elements
18 glued membranes
19 thermal greases
20 fin
30 loading plates
34 heat-conducting layers
35 plate bodys
36 through holes
361 conductive through holes.
Embodiment
By particular specific embodiment, embodiments of the present invention are described below, those skilled in the art can understand other advantages of the present invention and effect easily by content disclosed in the present specification.
Notice, structure, ratio, size etc. that this specification institute accompanying drawings illustrates, content all only for coordinating specification to disclose, for understanding and the reading of those skilled in the art, be not intended to limit the enforceable qualifications of the present invention, therefore the not technical essential meaning of tool, the adjustment of the modification of any structure, the change of proportionate relationship or size, do not affecting under effect that the present invention can produce and the object that can reach, still all should drop on disclosed technology contents and obtain in the scope that can contain.Meanwhile, the term quoted in this specification is also only understanding, but not for limiting the enforceable scope of the present invention, the change of its relativeness or adjustment, without under essence change technology contents, when being also considered as the enforceable category of the present invention of being convenient to describe.
Fig. 2 A to Fig. 2 I those shown is the cutaway view of the method for making of semiconductor package part of the present invention, wherein, and another embodiment that Fig. 2 I ' is Fig. 2 I.
As shown in Figure 2 A, on a loading plate 30, release layer 31 is optionally formed.
As shown in Figure 2 B, at least one semiconductor wafer 32 with relative acting surface 32a and non-active face 32b is set on this release layer 31, makes this semiconductor wafer 32 connect with its acting surface 32a and be placed on this release layer 31.
As shown in Figure 2 C, form the packing colloid 33 of this semiconductor wafer 32 coated on this release layer 31, this packing colloid 33 has relative first surface 33a and second surface 33b, and makes this packing colloid 33 connect this release layer 31 with its first surface 33a.
As shown in Figure 2 D, remove this packing colloid 33 of segment thickness from the second surface 33b of this packing colloid 33 by such as lapping mode, to expose this non-active face 32b, now, this acting surface 32a and non-active face 32b exposes to this first surface 33a and second surface 33b respectively.It is important to note that remove the step of this packing colloid 33 of segment thickness herein and inessential.
As shown in Figure 2 E, the plate body 35 put and it is formed with heat-conducting layer 34 is connect on the non-active face 32b of this semiconductor wafer 32 and the second surface 33b of this packing colloid 33, this heat-conducting layer 34 can be thermal grease, and this plate body 35 connects by this heat-conducting layer 34 and is placed on the non-active face 32b of this semiconductor wafer 32 and second surface 33b of this packing colloid 33, this plate body 35 can be alumina plate, and this plate body 35 can be heating panel or antenna plate.
As shown in Figure 2 F, this loading plate 30 and release layer 31 is removed, with the first surface 33a of the acting surface 32a and this packing colloid 33 that expose this semiconductor wafer 32.
As shown in Figure 2 G, at least one through hole 36 running through this packing colloid 33 and heat-conducting layer 34 is formed.
As illustrated in figure 2h, conductive through hole 361 is formed in this through hole 36, and the line layer 37 being electrically connected this semiconductor wafer 32 is formed on the acting surface 32a of this semiconductor wafer 32 with on the first surface 33a of this packing colloid 33, this conductive through hole 361 is electrically connected this line layer 37 and plate body 35, and forms multiple conducting element 38 on this line layer 37.
As shown in figure 2i, carry out cutting single stage, the side surface of this packing colloid 33 flushes with the side surface of this plate body 35; This is cut single stage and also can carry out before these conducting elements 38 of formation.
Or, as shown in Fig. 2 I ', final structure when it is the step of not carrying out Fig. 2 D.
The present invention also provides a kind of semiconductor package part, and it comprises: plate body 35; At least one semiconductor wafer 32, it is located on this plate body 35, and has relative acting surface 32a and non-active face 32b, and makes this semiconductor wafer 32 connect this plate body 35 with its non-active face 32b; Packing colloid 33, it is formed on this plate body 35, and this semiconductor wafer 32 coated, this packing colloid 33 has relative first surface 33a and second surface 33b, and makes this packing colloid 33 connect this plate body 35 with its second surface 33b; Line layer 37, with on the first surface 33a of this packing colloid 33 on its acting surface 32a being formed at this semiconductor wafer 32, to be electrically connected this semiconductor wafer 32; And at least one conductive through hole 361, it runs through this packing colloid 33, to be electrically connected this line layer 37 and plate body 35.
In aforesaid semiconductor package part, this acting surface 32a and non-active face 32b exposes to this first surface 33a and second surface 33b respectively, also comprise heat-conducting layer 34, between its non-active face 32b being formed at this plate body 35 and this semiconductor wafer 32 and between this plate body 35 and second surface 33b of this packing colloid 33, and this plate body 35 is heating panel or antenna plate.
In the present embodiment, also comprise multiple conducting element 38, it is formed on this line layer 37, and this plate body 35 is alumina plate, and the side surface of this packing colloid 33 flushes with the side surface of this plate body 35.
In sum, compared to prior art, because the present invention is with the support of plate body as semiconductor package part and the use of gripping, and this plate body also can be used as fin simultaneously, therefore the present invention need not use the second loading plate and on adhesion coating and need not carry out connecing the step of putting fin in finally again, and then shorten fabrication steps with reduce costs; In addition, because the present invention need not use this adhesion coating for engaging this second loading plate, so the step removing this residual adhesion coating can be saved, to reduce processing time and cost further; In addition, the present invention can be electrically connected semiconductor wafer and plate body by conductive through hole, also can be used as antenna to use to make this plate body.
Above-described embodiment only for illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can modify to above-described embodiment.Therefore the scope of the present invention, should listed by claims.

Claims (17)

1. a semiconductor package part, it comprises:
Plate body;
At least one semiconductor wafer, it is located on this plate body, and has relative acting surface and non-active face, and makes this semiconductor wafer connect this plate body with its non-active face;
Packing colloid, it is formed on this plate body, and this semiconductor wafer coated, this packing colloid has relative first surface and second surface, and makes this packing colloid connect this plate body with its second surface;
Line layer, with on the first surface of this packing colloid on its acting surface being formed at this semiconductor wafer, to be electrically connected this semiconductor wafer; And
At least one conductive through hole, it runs through this packing colloid, to be electrically connected this line layer and plate body.
2. semiconductor package part as claimed in claim 1, it is characterized in that, this acting surface and non-active face expose to this first surface and second surface respectively.
3. semiconductor package part as claimed in claim 2, it is characterized in that, this semiconductor package part also comprises heat-conducting layer, between its non-active face being formed at this plate body and this semiconductor wafer and between this plate body and second surface of this packing colloid.
4. semiconductor package part as claimed in claim 1, it is characterized in that, this plate body is heating panel or antenna plate.
5. semiconductor package part as claimed in claim 1, it is characterized in that, this semiconductor package part also comprises multiple conducting element, and it is formed on this line layer.
6. semiconductor package part as claimed in claim 1, it is characterized in that, this plate body is alumina plate.
7. semiconductor package part as claimed in claim 1, it is characterized in that, the side surface of this packing colloid flushes with the side surface of this plate body.
8. a method for making for semiconductor package part, it comprises:
At least one semiconductor wafer with relative acting surface and non-active face is set on a loading plate, makes this semiconductor wafer connect with its acting surface and be placed on this loading plate;
On this loading plate, form the packing colloid of this semiconductor wafer coated, this packing colloid has relative first surface and second surface, and makes this packing colloid connect this loading plate with its first surface;
Connect on the second surface of this packing colloid and put plate body;
Remove this loading plate, with the first surface of the acting surface and this packing colloid that expose this semiconductor wafer; And
Form at least one conductive through hole running through this packing colloid, and form the line layer being electrically connected this semiconductor wafer on the acting surface of this semiconductor wafer with on the first surface of this packing colloid, be electrically connected this line layer and plate body to make this conductive through hole.
9. the method for making of semiconductor package part as claimed in claim 8, it is characterized in that, this acting surface and non-active face expose to this first surface and second surface respectively.
10. the method for making of semiconductor package part as claimed in claim 9, is characterized in that, this plate body is also formed with heat-conducting layer, and this plate body connects by this heat-conducting layer and is placed on the non-active face of this semiconductor wafer and the second surface of this packing colloid.
The method for making of 11. semiconductor package parts as claimed in claim 8, is characterized in that, after this line layer of formation, also comprises and carries out cutting single stage.
The method for making of 12. semiconductor package parts as claimed in claim 11, it is characterized in that, after carrying out this and cutting single stage, the side surface of this packing colloid flushes with the side surface of this plate body.
The method for making of 13. semiconductor package parts as claimed in claim 8, it is characterized in that, this method for making is also included on this line layer and forms multiple conducting element.
The method for making of 14. semiconductor package parts as claimed in claim 9, is characterized in that, after this packing colloid of formation, also comprises this packing colloid removing segment thickness from the second surface of this packing colloid, to expose this non-active face.
The method for making of 15. semiconductor package parts as claimed in claim 8, it is characterized in that, before this semiconductor wafer is set, this loading plate is also formed with release layer, make this semiconductor wafer connect with its acting surface be placed on this release layer, and remove this loading plate and also comprise and remove this release layer.
The method for making of 16. semiconductor package parts as claimed in claim 8, it is characterized in that, this plate body is heating panel or antenna plate.
The method for making of 17. semiconductor package parts as claimed in claim 8, it is characterized in that, this plate body is alumina plate.
CN201410311795.8A 2014-06-13 2014-07-02 Semiconductor package and fabrication method thereof Pending CN105321893A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW103120463A TWI594379B (en) 2014-06-13 2014-06-13 Semiconductor package and a method for fabricating the same
TW103120463 2014-06-13

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Publication Number Publication Date
CN105321893A true CN105321893A (en) 2016-02-10

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107644843A (en) * 2016-07-22 2018-01-30 中芯国际集成电路制造（天津）有限公司 Method for manufacturing wafer stack

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101226888A (en) * 2008-02-15 2008-07-23 日月光半导体制造股份有限公司 Heat sinking type chip packaging technology and constitution
US20110156236A1 (en) * 2009-12-30 2011-06-30 Stmicroelectronics Asia Pacific Pte Ltd. Thermally enhanced expanded wafer level package ball grid array structure and method of making the same
US20130009320A1 (en) * 2011-07-07 2013-01-10 Samsung Electro-Mechanics Co., Ltd. Semiconductor package and method of manufacturing the same
TW201405673A (en) * 2012-07-18 2014-02-01 矽品精密工業股份有限公司 Method of forming chip scale package

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWM450064U (en) * 2012-11-30 2013-04-01 Unistars Semiconductor structure and semiconductor unit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101226888A (en) * 2008-02-15 2008-07-23 日月光半导体制造股份有限公司 Heat sinking type chip packaging technology and constitution
US20110156236A1 (en) * 2009-12-30 2011-06-30 Stmicroelectronics Asia Pacific Pte Ltd. Thermally enhanced expanded wafer level package ball grid array structure and method of making the same
US20130009320A1 (en) * 2011-07-07 2013-01-10 Samsung Electro-Mechanics Co., Ltd. Semiconductor package and method of manufacturing the same
TW201405673A (en) * 2012-07-18 2014-02-01 矽品精密工業股份有限公司 Method of forming chip scale package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107644843A (en) * 2016-07-22 2018-01-30 中芯国际集成电路制造（天津）有限公司 Method for manufacturing wafer stack
CN107644843B (en) * 2016-07-22 2020-07-28 中芯国际集成电路制造（天津）有限公司 Wafer stack manufacturing method

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TW201546976A (en) 2015-12-16

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Application publication date: 20160210