CN104183509A - Method for manufacturing semiconductor package - Google Patents
Method for manufacturing semiconductor package Download PDFInfo
- Publication number
- CN104183509A CN104183509A CN201310222505.8A CN201310222505A CN104183509A CN 104183509 A CN104183509 A CN 104183509A CN 201310222505 A CN201310222505 A CN 201310222505A CN 104183509 A CN104183509 A CN 104183509A
- Authority
- CN
- China
- Prior art keywords
- making
- semiconductor package
- bearing part
- reinforced structure
- encapsulating material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title description 2
- 239000000463 material Substances 0.000 claims abstract description 43
- 238000000576 coating method Methods 0.000 claims description 42
- 239000011248 coating agent Substances 0.000 claims description 37
- 239000000084 colloidal system Substances 0.000 claims description 8
- 238000012856 packing Methods 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000005022 packaging material Substances 0.000 abstract 2
- 238000005728 strengthening Methods 0.000 abstract 2
- 238000005538 encapsulation Methods 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 230000003014 reinforcing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 19
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 239000003351 stiffener Substances 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Wire Bonding (AREA)
Abstract
A method for fabricating a semiconductor package includes: providing a first bearing piece with a first surface, a semiconductor component with an action surface and a first strengthening structure, wherein the action surface of the semiconductor component is arranged on the first surface of the first bearing piece, and the first strengthening structure is arranged on the first surface of the first bearing piece; forming an encapsulation material on the first surface of the first carrier to encapsulate the semiconductor device and expose the first reinforcing structure; and baking the first bearing piece, the packaging material and the first reinforced structure. Therefore, the invention can avoid the situation that the packaging material and the like generate warping, and further improve the yield of the semiconductor packaging piece.
Description
Technical field
The present invention relates to a kind of method for making of semiconductor package part, refer to especially a kind of method for making of the semiconductor package part with reinforced structure.
Background technology
Along with making rapid progress and the quick evolution of manufacture of semiconductor of semiconductor technology, for being formed with the semiconductor package part of packing colloid, it is passing through easily to produce after baking processing procedure the situation of warpage (warpage), make follow-up circuit rerouting and cut single processing procedure to be difficult to carry out, cause reducing the yield of this semiconductor package part, therefore how to avoid this semiconductor package part generation warpage, real in important problem to promote the yield of this semiconductor package part.
Figure 1A to Fig. 1 D is the cross-sectional schematic that illustrates the method for making of the semiconductor package part of prior art.
As shown in Figure 1A, first sequentially form peel ply (release layer) 11 and adhesion coating (adhesive layer) 12 on carrier 10.
As shown in Figure 1B, the chip 13 with weld pad 131 is set on this adhesion coating 12.
As shown in Figure 1 C, form packing colloid 14 on this adhesion coating 12, to be coated this chip 13.
As shown in Fig. 1 D, this carrier 10, peel ply 11, adhesion coating 12 are toasted with packing colloid 14 etc.
The shortcoming of above-mentioned method for making, be after the baking processing procedure of Fig. 1 D, this carrier 10, peel ply 11, adhesion coating 12 and packing colloid 14 etc. easily produce the situation of warpages, make be follow-uply difficult to carry out circuit rerouting and cut single processing procedure, cause reducing the yield of this semiconductor package part.
Therefore, how to overcome the problem of above-mentioned prior art, become in fact the problem of desiring most ardently at present solution.
Summary of the invention
In view of the disadvantages of above-mentioned prior art, object of the present invention, for a kind of method for making of semiconductor package part is provided, can be avoided the situation of the generation warpages (warpage) such as this encapsulating material, and then promotes the yield of this semiconductor package part.
Semiconductor package part of the present invention comprises: provide and have the first bearing part of first surface, the semiconductor subassembly with acting surface and the first reinforced structure, this semiconductor subassembly is arranged at this acting surface on the first surface of this first bearing part, and this first reinforced structure is arranged on the first surface of this first bearing part; Form encapsulating material on the first surface of this first bearing part, to be coated this semiconductor subassembly and to expose outside this first reinforced structure; And this first bearing part, encapsulating material and the first reinforced structure are toasted.
This first bearing part can have the first carrier, the first peel ply and the first adhesion coating, this first peel ply and this first adhesion coating are sequentially formed on this first carrier, this semiconductor subassembly and this first reinforced structure are arranged on this first adhesion coating, and this encapsulating material is formed on this first adhesion coating of part.
This first reinforced structure can be metal frame, and is arranged in the surrounding of first surface of this first bearing part.This encapsulating material can be packing colloid or laminated film.
The method for making of this semiconductor package part can comprise: the second bearing part and second reinforced structure with second surface are provided, and this second reinforced structure is arranged on the second surface of this second bearing part; And with this second surface, this second bearing part is arranged on the end face of this encapsulating material.
This second bearing part can have Second support, the second peel ply and the second adhesion coating, this second peel ply and this second adhesion coating are sequentially formed on this Second support, this second reinforced structure is arranged on this second adhesion coating, and this second bearing part is arranged on the end face of this encapsulating material with this second adhesion coating.
This second reinforced structure can be metal frame, and is arranged in the surrounding of second surface of this second bearing part.
The method for making of this semiconductor package part can comprise: remove this first bearing part and this first reinforced structure, to expose outside the weld pad on bottom surface and multiple acting surface that is arranged at this semiconductor subassembly of this encapsulating material.
The method for making of this semiconductor package part can comprise: form line layer on the bottom surface of this encapsulating material and be electrically connected the weld pad of this semiconductor subassembly; What formation had multiple openings refuses layer on the bottom surface of this encapsulating material, to be coated this line layer and this weld pad, and exposes outside this line layer of part by those openings; And connect put multiple soldered balls in those openings to be electrically connected this line layer.
The method for making of this semiconductor package part can comprise: remove this second bearing part and this second reinforced structure, to expose outside the end face of this encapsulating material; And cut single job to form semiconductor package part.
As from the foregoing, the method for making of semiconductor package part of the present invention, mainly by the first reinforced structure is first arranged on the first bearing part, again this first bearing part, encapsulating material and the first reinforced structure etc. are toasted, can avoid this first bearing part and this encapsulating material etc. to produce the situation of warpage, carry out circuit rerouting and cut single processing procedure in order to follow-up., the second reinforced structure is arranged on the second bearing part meanwhile, then this second bearing part is arranged to the end face of encapsulating material, can make the end face of this encapsulating material remain smooth, and make line layer and refuse layer etc. to be easy to be formed on the bottom surface of this encapsulating material.By this, the present invention can promote the yield of this semiconductor package part.
Brief description of the drawings
Figure 1A to Fig. 1 D is the cross-sectional schematic that illustrates the method for making of the semiconductor package part of prior art; And
Fig. 2 A to Fig. 2 I is the cross-sectional schematic that illustrates the method for making of semiconductor package part of the present invention, and wherein, Fig. 2 B' is the schematic top plan view of Fig. 2 B.
Symbol description
10 carriers
11 peel plies
12 adhesion coatings
13 chips
131 weld pads
14 packing colloids
2 semiconductor package parts
21 first bearing parts
211 first carriers
212 first peel plies
213 first adhesion coatings
214 first surfaces
22 first reinforced structures
23 semiconductor subassemblies
23a acting surface
The non-acting surface of 23b
231 weld pads
24 encapsulating materials
24a bottom surface
24b end face
25 second bearing parts
251 Second supports
252 second peel plies
253 second adhesion coatings
254 second surfaces
26 second reinforced structures
27 line layers
28 refuse layer
281 openings
29 soldered balls
SS line of cut.
Embodiment
By particular specific embodiment explanation embodiments of the present invention, the personage who is familiar with this skill can understand other advantage of the present invention and effect easily by content disclosed in the present specification below.
Notice, appended graphic the illustrated structure of this specification, ratio, size etc., all contents in order to coordinate specification to disclose only, for personage's understanding and the reading of being familiar with this skill, not in order to limit the enforceable qualifications of the present invention, so not technical essential meaning of tool, the adjustment of the modification of any structure, the change of proportionate relationship or size, not affecting under effect that the present invention can produce and the object that can reach, all should still drop on disclosed technology contents and obtain in the scope that can contain.
Simultaneously, in this specification, quote as " on ", the term such as " ", " first ", " second ", " surface ", " bottom surface " and " end face ", also only for ease of understanding of narrating, but not in order to limit the enforceable scope of the present invention, the change of its relativeness or adjustment, changing under technology contents, when being also considered as the enforceable category of the present invention without essence.
Fig. 2 A to Fig. 2 I is the cross-sectional schematic that illustrates the method for making of semiconductor package part of the present invention, and wherein, Fig. 2 B' is the schematic top plan view of Fig. 2 B.
As shown in Figure 2 A, first provide first bearing part 21 with first surface 214.
In the present embodiment, this first bearing part 21 can be wafer form (wafer form) or panel-form (panel form), and has the first carrier 211, the first peel ply 212 and the first adhesion coating 213, but not as limit.In other embodiments, this first bearing part 21 also can have various structure.
This first peel ply 212 is sequentially formed on this first carrier 211 with this first adhesion coating 213, and namely this first peel ply 212 is first with coating (coating) or chemical vapour deposition (CVD) (Chemical Vapor Deposition; Etc. CVD) mode is formed on this first carrier 211, and this first adhesion coating 213 is formed on this first peel ply 212 in modes such as coatings again.This first surface 214 is the surface of this first adhesion coating 213.
As shown in Fig. 2 B and Fig. 2 B', the first reinforced structure 22 of for example square or ring-type is provided, and be arranged at the first surface 214 of this first bearing part 21 or its around on.
In the present embodiment, this first reinforced structure 22 can be metal frame or other stiffener (stiffener), be arranged at the surface of this first adhesion coating 213 or its around on.
As shown in Figure 2 C, provide there are multiple weld pads 231, relative acting surface 23a and the semiconductor subassembly 23 of non-acting surface 23b, it is upper that this weld pad 231 is arranged at this acting surface 23a, this semiconductor subassembly 23 is more than one.Meanwhile, with this acting surface 23a, this semiconductor subassembly 23 is arranged on the first surface 214 of this first bearing part 21.
In the present embodiment, this semiconductor subassembly 23 is two or more, and is arranged on the surface of this first adhesion coating 213 with this acting surface 23a.
In addition, in other embodiments, the processing procedure of above-mentioned Fig. 2 B and Fig. 2 C can be exchanged, namely first the semiconductor subassembly of Fig. 2 C 23 is arranged on the first surface 214 of this first bearing part 21, then by the first reinforced structure 22 of Fig. 2 B be arranged at the first surface 214 of this first bearing part 21 or its around on.
As shown in Figure 2 D, form encapsulating material 24 on the part first surface 214 of this first bearing part 21, to be coated this semiconductor subassembly 23 and to expose outside this first reinforced structure 22, make this first reinforced structure 22 be surrounded on this encapsulating material 24 around.Then, this first bearing part 21, encapsulating material 24 and the first reinforced structure 22 etc. are toasted.
In the present embodiment, this encapsulating material 24 can be packing colloid or laminated film (lamination film) etc., be formed on the part surface of this first adhesion coating 213, and in order to coated this semiconductor subassembly 23, but not coated this first reinforced structure 22.
As shown in Figure 2 E, second reinforced structure 26 with the second bearing part 25 of second surface 254 and for example square or ring-type is provided, this second bearing part 25 can be wafer form or panel-form, this second reinforced structure 26 can be arranged at the second surface 254 of this second bearing part 25 or its around on.Meanwhile, with this second surface 254, this second bearing part 25 is arranged on the end face 24b of this encapsulating material 24.
In the present embodiment, this second bearing part 25 has Second support 251, the second peel ply 252 and the second adhesion coating 253, but not as limit.In other embodiments, this second bearing part 25 also can have various structure.
This second peel ply 252 is sequentially formed on this Second support 251 with this second adhesion coating 253, namely this second peel ply 252 is first formed on this Second support 251 in modes such as coating or chemical vapour deposition (CVD)s (CVD), and this second adhesion coating 253 is formed on this second peel ply 252 in modes such as coatings again.This second surface 254 is the surface of this second adhesion coating 253.
This second reinforced structure 26 can be metal frame or other stiffener, its be arranged at the surface of this second adhesion coating 253 or its around on.This second bearing part 25 is arranged on the end face 24b of this encapsulating material 24 with this second adhesion coating 253.
As shown in Figure 2 F, remove this first bearing part 21 and this first reinforced structure 22, to expose outside the bottom surface 24a of this encapsulating material 24 and the weld pad 231 of this semiconductor subassembly 23, this weld pad 231 is arranged on the acting surface 23a of this semiconductor subassembly 23.
As shown in Figure 2 G, form line layer 27 or circuit rerouting layer (Redistribution Layer; RDL) go up in the bottom surface of this encapsulating material 24 24a, and be electrically connected the weld pad 231 of this semiconductor subassembly 23.Then, formation has the layer 28 of refusing of multiple openings 281 goes up in the bottom surface of this encapsulating material 24 24a, to be coated the weld pad 231 and acting surface 23a of this line layer 27, this semiconductor subassembly 23, and exposes outside this line layer 27 of part by those openings 281.Then, connect put multiple soldered balls 29 in those openings 281 to be electrically connected this line layer 27.
As shown in Fig. 2 H, remove this second bearing part 25 and this second reinforced structure 26, to expose outside the end face 24b of this encapsulating material 24.Afterwards, cut list (singulation) operation along line of cut SS, to form multiple semiconductor package parts.
As shown in Fig. 2 I, it is for showing the semiconductor package part 2 of cutting after list.
As from the foregoing, the method for making of semiconductor package part of the present invention, mainly by the first reinforced structure is first arranged on the first bearing part, again this first bearing part, encapsulating material and the first reinforced structure etc. are toasted, can avoid this first bearing part and this encapsulating material etc. to produce the situation of warpage, carry out circuit rerouting and cut single processing procedure in order to follow-up., the second reinforced structure is arranged on the second bearing part meanwhile, then this second bearing part is arranged to the end face of encapsulating material, can make the end face of this encapsulating material remain smooth, and make line layer and refuse layer etc. to be easy to be formed on the bottom surface of this encapsulating material.By this, the present invention can promote the yield of this semiconductor package part.
Above-described embodiment is only in order to illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all can, under spirit of the present invention and category, modify to above-described embodiment.Therefore the scope of the present invention, should be as listed in claims.
Claims (15)
1. a method for making for semiconductor package part, it comprises:
Provide and there is the first bearing part of first surface, the semiconductor subassembly with acting surface and the first reinforced structure, this semiconductor subassembly is arranged at this acting surface on the first surface of this first bearing part, and this first reinforced structure is arranged on the first surface of this first bearing part;
Form encapsulating material on the first surface of this first bearing part, to be coated this semiconductor subassembly and to expose outside this first reinforced structure; And
This first bearing part, encapsulating material and the first reinforced structure are toasted.
2. the method for making of semiconductor package part according to claim 1, it is characterized in that, this first bearing part has the first carrier, the first peel ply and the first adhesion coating, this first peel ply and this first adhesion coating are sequentially formed on this first carrier, this semiconductor subassembly and this first reinforced structure are arranged on this first adhesion coating, and this encapsulating material is formed on this first adhesion coating of part.
3. the method for making of semiconductor package part according to claim 1, is characterized in that, this first reinforced structure is arranged in the surrounding of first surface of this first bearing part.
4. the method for making of semiconductor package part according to claim 1, is characterized in that, this first reinforced structure is metal frame.
5. the method for making of semiconductor package part according to claim 1, is characterized in that, this encapsulating material is packing colloid or laminated film.
6. the method for making of semiconductor package part according to claim 1, is characterized in that, this method for making also comprises:
The second bearing part and second reinforced structure with second surface are provided, and this second reinforced structure is arranged on the second surface of this second bearing part; And
With this second surface, this second bearing part is arranged on the end face of this encapsulating material.
7. the method for making of semiconductor package part according to claim 6, it is characterized in that, this second bearing part has Second support, the second peel ply and the second adhesion coating, this second peel ply and this second adhesion coating are sequentially formed on this Second support, this second reinforced structure is arranged on this second adhesion coating, and this second bearing part is arranged on the end face of this encapsulating material with this second adhesion coating.
8. the method for making of semiconductor package part according to claim 6, is characterized in that, this second reinforced structure is arranged in the surrounding of second surface of this second bearing part.
9. the method for making of semiconductor package part according to claim 6, is characterized in that, this second reinforced structure is metal frame.
10. the method for making of semiconductor package part according to claim 6, it is characterized in that, this method for making also comprises and removes this first bearing part and this first reinforced structure, to expose outside the weld pad on bottom surface and multiple acting surface that is arranged at this semiconductor subassembly of this encapsulating material.
The method for making of 11. semiconductor package parts according to claim 10, is characterized in that, this method for making also comprises that formation line layer is on the bottom surface of this encapsulating material, and is electrically connected the weld pad of this semiconductor subassembly.
The method for making of 12. semiconductor package parts according to claim 11, it is characterized in that, this method for making also comprise form there are multiple openings refuse layer on the bottom surface of this encapsulating material, to be coated weld pad and the acting surface of this line layer, this semiconductor subassembly, and expose outside this line layer of part by those openings.
The method for making of 13. semiconductor package parts according to claim 12, is characterized in that, this method for making also comprise connect put multiple soldered balls in those openings to be electrically connected this line layer.
The method for making of 14. semiconductor package parts according to claim 13, is characterized in that, this method for making also comprises and removes this second bearing part and this second reinforced structure, to expose outside the end face of this encapsulating material.
The method for making of 15. semiconductor package parts according to claim 14, is characterized in that, this method for making also comprises cuts single job to form semiconductor package part.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102118395A TW201445644A (en) | 2013-05-24 | 2013-05-24 | Method for manufacturing semiconductor package |
| TW102118395 | 2013-05-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104183509A true CN104183509A (en) | 2014-12-03 |
| CN104183509B CN104183509B (en) | 2017-11-21 |
Family
ID=51964462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310222505.8A Active CN104183509B (en) | 2013-05-24 | 2013-06-06 | Method for manufacturing semiconductor package |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104183509B (en) |
| TW (1) | TW201445644A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108172561A (en) * | 2016-12-07 | 2018-06-15 | 矽品精密工业股份有限公司 | Bearing substrate for semiconductor package, package structure thereof and manufacturing method of semiconductor package element |
| CN108242404A (en) * | 2016-12-27 | 2018-07-03 | 冠宝科技股份有限公司 | A kind of no substrate semiconductor encapsulation making method |
| CN109003946A (en) * | 2017-06-06 | 2018-12-14 | 力成科技股份有限公司 | Encapsulating structure and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5953589A (en) * | 1996-12-30 | 1999-09-14 | Anam Semiconductor Inc. | Ball grid array semiconductor package with solder balls fused on printed circuit board and method for fabricating the same |
| US6118183A (en) * | 1996-12-19 | 2000-09-12 | Texas Instruments Incorporated | Semiconductor device, manufacturing method thereof, and insulating substrate for same |
| CN1337739A (en) * | 2000-08-03 | 2002-02-27 | 三洋电机株式会社 | Method for producing semi-conductor device |
| TW200910471A (en) * | 2007-08-17 | 2009-03-01 | Chipmos Technologies Inc | A dice rearrangement package method |
| CN102439704A (en) * | 2009-05-06 | 2012-05-02 | 马维尔国际贸易有限公司 | Packaging techniques and configurations |
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2013
- 2013-05-24 TW TW102118395A patent/TW201445644A/en unknown
- 2013-06-06 CN CN201310222505.8A patent/CN104183509B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6118183A (en) * | 1996-12-19 | 2000-09-12 | Texas Instruments Incorporated | Semiconductor device, manufacturing method thereof, and insulating substrate for same |
| US5953589A (en) * | 1996-12-30 | 1999-09-14 | Anam Semiconductor Inc. | Ball grid array semiconductor package with solder balls fused on printed circuit board and method for fabricating the same |
| CN1337739A (en) * | 2000-08-03 | 2002-02-27 | 三洋电机株式会社 | Method for producing semi-conductor device |
| TW200910471A (en) * | 2007-08-17 | 2009-03-01 | Chipmos Technologies Inc | A dice rearrangement package method |
| CN102439704A (en) * | 2009-05-06 | 2012-05-02 | 马维尔国际贸易有限公司 | Packaging techniques and configurations |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108172561A (en) * | 2016-12-07 | 2018-06-15 | 矽品精密工业股份有限公司 | Bearing substrate for semiconductor package, package structure thereof and manufacturing method of semiconductor package element |
| CN108172561B (en) * | 2016-12-07 | 2020-09-08 | 矽品精密工业股份有限公司 | Bearing substrate, packaging structure thereof and manufacturing method of semiconductor packaging element |
| CN108242404A (en) * | 2016-12-27 | 2018-07-03 | 冠宝科技股份有限公司 | A kind of no substrate semiconductor encapsulation making method |
| CN109003946A (en) * | 2017-06-06 | 2018-12-14 | 力成科技股份有限公司 | Encapsulating structure and its manufacturing method |
| CN109003946B (en) * | 2017-06-06 | 2020-12-15 | 力成科技股份有限公司 | Package structure and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201445644A (en) | 2014-12-01 |
| CN104183509B (en) | 2017-11-21 |
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