CN104517911A - Semiconductor package and fabrication method thereof - Google Patents
Semiconductor package and fabrication method thereof Download PDFInfo
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- CN104517911A CN104517911A CN201310487209.0A CN201310487209A CN104517911A CN 104517911 A CN104517911 A CN 104517911A CN 201310487209 A CN201310487209 A CN 201310487209A CN 104517911 A CN104517911 A CN 104517911A
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- semiconductor package
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- packing colloid
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 110
- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000000084 colloidal system Substances 0.000 claims abstract description 92
- 238000012856 packing Methods 0.000 claims description 88
- 239000011248 coating agent Substances 0.000 claims description 48
- 238000000576 coating method Methods 0.000 claims description 48
- 238000003825 pressing Methods 0.000 claims description 6
- 229920000620 organic polymer Polymers 0.000 claims description 5
- 238000010422 painting Methods 0.000 claims description 5
- 238000009747 press moulding Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 abstract 5
- 230000000712 assembly Effects 0.000 abstract 2
- 238000000429 assembly Methods 0.000 abstract 2
- 238000003466 welding Methods 0.000 abstract 2
- 239000008393 encapsulating agent Substances 0.000 abstract 1
- 238000012545 processing Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A semiconductor package and a method for fabricating the same, the method comprising: providing a first bearing piece and a plurality of semiconductor assemblies, wherein each semiconductor assembly is provided with an action surface and a plurality of welding pads formed on the action surface; arranging the semiconductor assembly on the first bearing piece by the action surface; forming a packaging colloid on the first bearing piece to respectively coat the semiconductor assemblies, and enabling gaps to be formed among the packaging colloids; forming a buffer layer on the first carrier to cover the encapsulant and fill the gap; and removing the first bearing piece to expose the action surface, the welding pad, the packaging colloid and the buffer layer of the semiconductor component. Therefore, the invention can prevent the packaging colloid from warping and improve the yield of the semiconductor packaging piece.
Description
Technical field
The present invention relates to a kind of semiconductor package part and method for making thereof, refer to a kind of semiconductor package part and the method for making thereof that promote yield especially.
Background technology
Current fan-out (Fan-Out) type semiconductor package part mainly through forming packing colloid to encapsulate multiple chip on the whole surface of carrier; but because the contact area of this packing colloid and this carrier is excessive, and the thermal coefficient of expansion of this packing colloid (Coefficient ofThermal Expansion; CTE) higher than the thermal coefficient of expansion of this carrier, so that this packing colloid easily produces excessive stresses and causes the situation of warpage (warpage), thus causes follow-uply being difficult in the enterprising row line rerouting of this packing colloid and cutting the processing procedures such as single.
Figure 1A and Figure 1B is the cross-sectional schematic of the method for making of the semiconductor package part illustrating prior art.
As shown in Figure 1A, first form peel ply (release layer) 11 on carrier 10, and multiple chip 12 with weld pad 121 is set on this peel ply 11, then form packing colloid 13 on this peel ply 11 with those chips 12 coated.
Then, baking operation is carried out to this carrier 10, peel ply 11 and packing colloid 13, and remove this carrier 10 and this peel ply 11.
The shortcoming of the method for making of above-mentioned semiconductor package part, be that this packing colloid 13 is excessive with the contact area of the peel ply 11 on this carrier 10, and the thermal coefficient of expansion of this packing colloid 13 and young's modulus (Young ' s Modulus) also respectively higher than thermal coefficient of expansion and the young's modulus of this carrier 10, this packing colloid 13 is made easily to produce the situation of warpage as shown in Figure 1B, thus cause follow-uply being difficult in the enterprising row line rerouting of this packing colloid 13 and cutting the processing procedures such as single, and reduce the yield of this semiconductor package part.
Therefore, how to overcome the problem of above-mentioned prior art, become the problem of desiring most ardently solution at present in fact.
Summary of the invention
Main purpose of the present invention, for providing a kind of semiconductor package part and method for making thereof, can prevent those packing colloids from producing the situation of warpage, and promote the yield of this semiconductor package part.
Semiconductor package part of the present invention, it comprises: semiconductor subassembly, and it has acting surface and the multiple weld pads being formed at this acting surface; Packing colloid, it has relative first surface and second surface, and this semiconductor subassembly coated, and the first surface of this packing colloid exposes outside acting surface and the weld pad of this semiconductor subassembly; And resilient coating, it is formed on the second surface of this packing colloid.
This packing colloid can have the side of this first surface adjacent and this second surface, on the second surface that this resilient coating is formed at this packing colloid and side.
This semiconductor package part can comprise line layer, to be electrically connected those weld pads on its acting surface being formed at this semiconductor subassembly.
The present invention also provides a kind of method for making of semiconductor package part, and it comprises: provide one first bearing part and multiple semiconductor subassembly, and this semiconductor subassembly has acting surface and the multiple weld pads being formed at this acting surface; With this acting surface, this semiconductor subassembly is arranged on this first bearing part; Form packing colloid with difference those semiconductor subassemblies coated on this first bearing part, and make, between those packing colloids, there is gap; Form resilient coating on this first bearing part with those packing colloids coated and insert this gap; And remove this first bearing part to expose outside the acting surface of this semiconductor subassembly, weld pad, packing colloid and resilient coating.
This first bearing part can have the first carrier and the first peel ply be formed on this first carrier, and this semiconductor subassembly is arranged on this first peel ply with this acting surface, and those packing colloids and this resilient coating are sequentially formed on this first peel ply.
The method for making of this semiconductor package part can comprise the first carrier removing this first bearing part by this first peel ply.
The method for making of this semiconductor package part can comprise to be provided one to have Second support and forms the second bearing part of the second peel ply on this Second support, and after this resilient coating of formation, is formed on this resilient coating with this second peel ply by this second bearing part; And form line layer on the first surface of this packing colloid and the acting surface of this semiconductor subassembly to be electrically connected those weld pads.
The method for making of this semiconductor package part can comprise the Second support removing this second bearing part by this second peel ply; And carry out cutting single job to form multiple semiconductor package part.This is cut single job and can carry out cutting or cutting, to form those semiconductor package parts according to the gap of those packing colloids or the resilient coating of surrounding according to the side of those packing colloids.
In above-mentioned semiconductor package part and method for making thereof, this packing colloid can be coated on this semiconductor subassembly by screen painting, pressing or press moulding mode.The thermal coefficient of expansion of this resilient coating can lower than the thermal coefficient of expansion of this packing colloid, and the young's modulus of this resilient coating also can lower than the young's modulus of this packing colloid.This resilient coating can be thermal coefficient of expansion between 3 to 20ppm/ DEG C or the young's modulus organic polymer between 1 to 1000MPa (Megapascal).
As from the foregoing, semiconductor package part of the present invention and method for making thereof, mainly multiple semiconductor subassembly is set on the first bearing part, and form packing colloid on this first bearing part with difference those semiconductor subassemblies coated, to make, between those packing colloids, there is gap, form resilient coating again on this first bearing part with those packing colloids coated and insert this gap, and the thermal coefficient of expansion of this resilient coating can lower than the thermal coefficient of expansion of this packing colloid, or the young's modulus of this resilient coating can lower than the young's modulus of this packing colloid.
By this, the present invention can make those packing colloids and this resilient coating form composite structure, and reduce the contact area of single packing colloid and this first bearing part, be released in order to do the stress made between those packing colloids and this first bearing part, also the reliability of those packing colloids can be possessed, can also prevent those packing colloids from producing the situation of warpage, in order to follow-up in the enterprising row line rerouting of those packing colloids and cut the processing procedures such as single, and then promote the yield of this semiconductor package part.
Accompanying drawing explanation
Figure 1A and Figure 1B is the cross-sectional schematic of the method for making of the semiconductor package part illustrating prior art; And
Fig. 2 A to Fig. 2 I ' is for illustrating the cross-sectional schematic of semiconductor package part of the present invention and method for making thereof, wherein, Fig. 2 A ' and Fig. 2 C ' are respectively the schematic top plan view of Fig. 2 A and Fig. 2 C, and Fig. 2 I and Fig. 2 I ' is respectively and carries out the schematic diagram after cutting list along the line of cut S of Fig. 2 H and the line of cut S ' of Fig. 2 H '.
Symbol description
Embodiment
By particular specific embodiment, embodiments of the present invention are described below, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.
Notice, structure, ratio, size etc. that this specification institute accompanying drawings illustrates, content all only in order to coordinate specification to disclose, for understanding and the reading of those skilled in the art, and be not used to limit the enforceable qualifications of the present invention, therefore the not technical essential meaning of tool, the adjustment of the modification of any structure, the change of proportionate relationship or size, do not affecting under effect that the present invention can produce and the object that can reach, still all should drop on disclosed technology contents and obtain in the scope that can contain.
Simultaneously, quote in this specification as " on ", " one ", " first ", " second ", " surface ", the term such as " acting surface " and " non-active face ", be also only be convenient to describe understand, and be not used to limit the enforceable scope of the present invention, the change of its relativeness or adjustment, under changing technology contents without essence, when being also considered as the enforceable category of the present invention.
Fig. 2 A to Fig. 2 I ' is for illustrating the cross-sectional schematic of semiconductor package part of the present invention and method for making thereof, wherein, Fig. 2 A ' and Fig. 2 C ' are respectively the schematic top plan view of Fig. 2 A and Fig. 2 C, and Fig. 2 I and Fig. 2 I ' is respectively and carries out the schematic diagram after cutting list along the line of cut S of Fig. 2 H and the line of cut S ' of Fig. 2 H '.
As shown in Fig. 2 A and Fig. 2 A ', first provide the first bearing part 20, and it has the first carrier 201, is formed at the first peel ply 202 on this first carrier 201 and multiple encapsulation unit 203.
As shown in Figure 2 B, provide multiple semiconductor subassembly 21 as semiconductor chip, and respectively this semiconductor subassembly 21 have relative acting surface 211 and non-active face 212 and the multiple weld pads 213 being formed at this acting surface 211.Meanwhile, with this acting surface 211, this semiconductor subassembly 21 is arranged on the first peel ply 202 of the encapsulation unit 203 of this first bearing part 20.
As shown in Fig. 2 C and Fig. 2 C ', by screen painting, pressing (lamination) or mold pressing (molding) mode, form packing colloid 22 respectively with those semiconductor subassemblies 21 coated on the first peel ply 202 of those encapsulation units 203, and make, between those packing colloids 22, there is gap 224.
As shown in Figure 2 D, formed there is relative 3rd surface 231 and the 4th surface 232 resilient coating 23 on the first peel ply 202 of this first bearing part 20, with those packing colloids 22 coated and insert this gap 224.The thermal coefficient of expansion of this resilient coating 23 can lower than the thermal coefficient of expansion of this packing colloid 22, and the young's modulus of this resilient coating 23 can lower than the young's modulus of this packing colloid 22, and this resilient coating 23 can be thermal coefficient of expansion between 3 to 20ppm/ DEG C or the young's modulus organic polymer between 1 to 1000MPa.
As shown in Figure 2 E, provide the second bearing part 24 and its second peel ply 242 that there is Second support 241 and formed on this Second support 241, and with this second peel ply 242, this second bearing part 24 is formed on the 4th surface 232 of this resilient coating 23.
As shown in Figure 2 F, remove the first carrier 201 of this first bearing part 20 by this first peel ply 202, to expose outside the acting surface 211 of this semiconductor subassembly 21, weld pad 213, the first surface 221 of packing colloid 22 and the 3rd surface 231 of resilient coating 23.
As shown in Figure 2 G, line layer 25 is formed on the first surface 221 of this packing colloid 22 and the acting surface 211 of this semiconductor subassembly 21 to be electrically connected those weld pads 213.
Then, formed there is multiple opening 261 refuse layer 26 on the 3rd surface 231 and line layer 25 of the first surface 221 of the acting surface 211 of this semiconductor subassembly 21, packing colloid 22, resilient coating 23, and expose outside this line layer 25 of part by those openings 261.
Then, plant and connect multiple soldered ball 27 in those openings 261 to be electrically connected this line layer 25.
As illustrated in figure 2h, remove the Second support 241 of this second bearing part 24 by this second peel ply 242, to expose outside the 4th surface 232 of this resilient coating 23.Afterwards, according to those packing colloids 22 side 223 and carry out cutting list (singulation) operation along each line of cut S, to form multiple semiconductor package part 2 as shown in figure 2i.
In another embodiment, the present invention also can carry out cutting single job along each line of cut S ', to form multiple the semiconductor package parts 2 ' as shown in Fig. 2 I ' according to the gap 224 of packing colloid 22 Fig. 2 H ' Suo Shi or resilient coating 23 around.
The present invention also provides a kind of semiconductor package part, as shown in figure 2i.Semiconductor package part 2 comprises semiconductor subassembly 21, packing colloid 22 and resilient coating 23.
This semiconductor subassembly 21 has relative acting surface 211 and non-active face 212 and the multiple weld pads 213 being formed at this acting surface 211.
This packing colloid 22 has relative first surface 221 and second surface 222, and be coated on this semiconductor subassembly 21 by screen painting, pressing or press moulding mode, and the first surface 221 of this packing colloid 22 exposes outside acting surface 211 and the weld pad 213 of this semiconductor subassembly 21.
This resilient coating 23 is formed on the second surface 222 of this packing colloid 22, and the thermal coefficient of expansion of this resilient coating 23 can lower than the thermal coefficient of expansion of this packing colloid 22, and the young's modulus of this resilient coating 23 also can lower than the young's modulus of this packing colloid 22, this resilient coating 23 can be thermal coefficient of expansion between 3 to 20ppm/ DEG C or the young's modulus organic polymer between 1 to 1000MPa.
Above-mentioned semiconductor package part 2 also can comprise line layer 25, and it is formed on the first surface 221 of this packing colloid 22 and the acting surface 211 of this semiconductor subassembly 21 to be electrically connected those weld pads 213.
This semiconductor package part 2 also can comprise there is multiple opening 261 refuse layer 26, it is formed on the acting surface 211 of this semiconductor subassembly 21, the first surface 221 of packing colloid 22 and line layer 25, and exposes outside this line layer 25 of part by those openings 261.
This semiconductor package part 2 also can comprise multiple soldered ball 27, and it is planted respectively and is connected in those openings 261 to be electrically connected this line layer 25.
The present invention separately provides a kind of semiconductor package part, as shown in Fig. 2 I '.Semiconductor package part 2 ' is roughly the same with the semiconductor package part 2 of above-mentioned Fig. 2 I, and its Main Differences is as follows:
In Fig. 2 I ', the packing colloid 22 of semiconductor package part 2 ' can have the side 223 of this first surface 221 adjacent and this second surface 222, on the second surface 222 that this resilient coating 23 can be formed at this packing colloid 22 and side 223.
As from the foregoing, semiconductor package part of the present invention and method for making thereof, mainly through arranging multiple semiconductor subassembly on the first bearing part, and form packing colloid on this first bearing part with difference those semiconductor subassemblies coated, between those packing colloids, there is gap in order to do making, form resilient coating again on this first bearing part with those packing colloids coated and insert this gap, and the thermal coefficient of expansion of this resilient coating can lower than the thermal coefficient of expansion of this packing colloid, or the young's modulus of this resilient coating can lower than the young's modulus of this packing colloid.
By this, the present invention can make those packing colloids and this resilient coating form composite structure, and reduce the contact area of single packing colloid and this first bearing part, be released in order to do the stress made between those packing colloids and this first bearing part, also the reliability of those packing colloids can be possessed, can also prevent those packing colloids from producing the situation of warpage, in order to follow-up in the enterprising row line rerouting of those packing colloids and cut the processing procedures such as single, and then promote the yield of this semiconductor package part.
Above-described embodiment only in order to illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can modify to above-described embodiment.Therefore the scope of the present invention, should listed by claims.
Claims (20)
1. a semiconductor package part, it comprises:
Semiconductor subassembly, it has acting surface and the multiple weld pads being formed at this acting surface;
Packing colloid, it has relative first surface and second surface, and this semiconductor subassembly coated, and the first surface of this packing colloid exposes outside acting surface and the weld pad of this semiconductor subassembly; And
Resilient coating, it is formed on the second surface of this packing colloid.
2. semiconductor package part according to claim 1, is characterized in that, this packing colloid also has the side of this first surface adjacent and this second surface, on the second surface that this resilient coating is formed at this packing colloid and side.
3. semiconductor package part according to claim 1, also comprises line layer, to be electrically connected those weld pads on the acting surface being formed at this semiconductor subassembly.
4. semiconductor package part according to claim 1, wherein, this packing colloid is coated on this semiconductor subassembly by screen painting, pressing or press moulding mode.
5. semiconductor package part according to claim 1, wherein, the thermal coefficient of expansion of this resilient coating is lower than the thermal coefficient of expansion of this packing colloid.
6. semiconductor package part according to claim 1, wherein, the young's modulus of this resilient coating is lower than the young's modulus of this packing colloid.
7. semiconductor package part according to claim 1, wherein, this resilient coating is thermal coefficient of expansion between 3 to 20ppm/ DEG C or the young's modulus organic polymer between 1 to 1000MPa.
8. a method for making for semiconductor package part, it comprises:
There is provided one first bearing part and multiple semiconductor subassembly, this semiconductor subassembly has acting surface and the multiple weld pads being formed at this acting surface;
With this acting surface, this semiconductor subassembly is arranged on this first bearing part;
Form packing colloid with difference those semiconductor subassemblies coated on this first bearing part, and make, between those packing colloids, there is gap;
Form resilient coating on this first bearing part with those packing colloids coated and insert this gap; And
Remove this first bearing part to expose outside the acting surface of this semiconductor subassembly, weld pad, packing colloid and resilient coating.
9. the method for making of semiconductor package part according to claim 8, wherein, this first bearing part also has the first carrier and the first peel ply be formed on this first carrier, this semiconductor subassembly is arranged on this first peel ply with this acting surface, and those packing colloids and this resilient coating are sequentially formed on this first peel ply.
10. the method for making of semiconductor package part according to claim 9, also comprises the first carrier removing this first bearing part by this first peel ply.
The method for making of 11. semiconductor package parts according to claim 8, also comprise and provide one to have Second support and form the second bearing part of the second peel ply on this Second support, and after this resilient coating of formation, with this second peel ply, this second bearing part is formed on this resilient coating.
The method for making of 12. semiconductor package parts according to claim 11, also comprises and forms line layer on the acting surface of this semiconductor subassembly to be electrically connected those weld pads.
The method for making of 13. semiconductor package parts according to claim 11, also comprises the Second support removing this second bearing part by this second peel ply.
The method for making of 14. semiconductor package parts according to claim 13, also comprises and carries out cutting single job to form multiple semiconductor package part.
The method for making of 15. semiconductor package parts according to claim 14, wherein, this is cut single job and carries out cutting to form those semiconductor package parts according to the side of those packing colloids.
The method for making of 16. semiconductor package parts according to claim 14, wherein, this is cut single job and carries out cutting to form those semiconductor package parts according to the gap of those packing colloids or resilient coating around.
The method for making of 17. semiconductor package parts according to claim 8, wherein, this packing colloid is coated on this semiconductor subassembly by screen painting, pressing or press moulding mode.
The method for making of 18. semiconductor package parts according to claim 8, wherein, the thermal coefficient of expansion of this resilient coating is lower than the thermal coefficient of expansion of this packing colloid.
The method for making of 19. semiconductor package parts according to claim 8, wherein, the young's modulus of this resilient coating is lower than the young's modulus of this packing colloid.
The method for making of 20. semiconductor package parts according to claim 8, wherein, this resilient coating is thermal coefficient of expansion between 3 to 20ppm/ DEG C or the young's modulus organic polymer between 1 to 1000MPa.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102135635A TWI518852B (en) | 2013-10-02 | 2013-10-02 | Semiconductor package and manufacturing method thereof |
| TW102135635 | 2013-10-02 |
Publications (2)
| Publication Number | Publication Date |
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| CN104517911A true CN104517911A (en) | 2015-04-15 |
| CN104517911B CN104517911B (en) | 2018-03-27 |
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| CN201310487209.0A Active CN104517911B (en) | 2013-10-02 | 2013-10-17 | Semiconductor package and fabrication method thereof |
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| TW (1) | TWI518852B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106206469A (en) * | 2015-05-29 | 2016-12-07 | 爱思开海力士有限公司 | Semiconductor packages and manufacture method thereof |
| JP2017108120A (en) * | 2015-12-10 | 2017-06-15 | パロ アルト リサーチ センター インコーポレイテッド | Integration with components by printing of bare die in flexible substrate not requiring laser cutting |
| CN107527895A (en) * | 2016-06-22 | 2017-12-29 | 3D加公司 | Collective's manufacture is configured in the method higher than the 3D electronic building bricks to be worked under 1GHz |
| US10206288B2 (en) | 2015-08-13 | 2019-02-12 | Palo Alto Research Center Incorporated | Bare die integration with printed components on flexible substrate |
| US10847384B2 (en) | 2017-05-31 | 2020-11-24 | Palo Alto Research Center Incorporated | Method and fixture for chip attachment to physical objects |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI573231B (en) * | 2015-07-17 | 2017-03-01 | 矽品精密工業股份有限公司 | Package substrate and method of manufacture thereof |
| TWI710094B (en) * | 2019-09-10 | 2020-11-11 | 矽品精密工業股份有限公司 | Electronic package and method of manufacture |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106206469A (en) * | 2015-05-29 | 2016-12-07 | 爱思开海力士有限公司 | Semiconductor packages and manufacture method thereof |
| CN106206469B (en) * | 2015-05-29 | 2019-10-25 | 爱思开海力士有限公司 | Semiconductor packages and its manufacturing method |
| TWI695455B (en) * | 2015-05-29 | 2020-06-01 | 南韓商愛思開海力士有限公司 | Semiconductor packages and methods of fabricating the same |
| US10206288B2 (en) | 2015-08-13 | 2019-02-12 | Palo Alto Research Center Incorporated | Bare die integration with printed components on flexible substrate |
| JP2017108120A (en) * | 2015-12-10 | 2017-06-15 | パロ アルト リサーチ センター インコーポレイテッド | Integration with components by printing of bare die in flexible substrate not requiring laser cutting |
| EP3188220A3 (en) * | 2015-12-10 | 2017-12-13 | Palo Alto Research Center, Incorporated | Bare die integration with printed components |
| US10165677B2 (en) | 2015-12-10 | 2018-12-25 | Palo Alto Research Center Incorporated | Bare die integration with printed components on flexible substrate without laser cut |
| US11122683B2 (en) | 2015-12-10 | 2021-09-14 | Palo Alto Research Center Incorporated | Bare die integration with printed components on flexible substrate without laser cut |
| CN107527895A (en) * | 2016-06-22 | 2017-12-29 | 3D加公司 | Collective's manufacture is configured in the method higher than the 3D electronic building bricks to be worked under 1GHz |
| CN107527895B (en) * | 2016-06-22 | 2023-05-12 | 3D加公司 | Method of collective fabrication of 3D electronic components configured to operate above 1GHz |
| US10847384B2 (en) | 2017-05-31 | 2020-11-24 | Palo Alto Research Center Incorporated | Method and fixture for chip attachment to physical objects |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104517911B (en) | 2018-03-27 |
| TW201515163A (en) | 2015-04-16 |
| TWI518852B (en) | 2016-01-21 |
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