CN104517911B - Semiconductor package and fabrication method thereof - Google Patents
Semiconductor package and fabrication method thereof Download PDFInfo
- Publication number
- CN104517911B CN104517911B CN201310487209.0A CN201310487209A CN104517911B CN 104517911 B CN104517911 B CN 104517911B CN 201310487209 A CN201310487209 A CN 201310487209A CN 104517911 B CN104517911 B CN 104517911B
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- semiconductor package
- cushion
- semiconductor
- package part
- packing colloid
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 105
- 238000000034 method Methods 0.000 title abstract description 7
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000000084 colloidal system Substances 0.000 claims abstract description 93
- 238000004806 packaging method and process Methods 0.000 claims abstract description 10
- 238000012856 packing Methods 0.000 claims description 81
- 238000002360 preparation method Methods 0.000 claims description 29
- 238000005538 encapsulation Methods 0.000 claims description 8
- 229920000620 organic polymer Polymers 0.000 claims description 7
- 238000010422 painting Methods 0.000 claims description 5
- 238000003825 pressing Methods 0.000 claims description 5
- 238000000465 moulding Methods 0.000 claims description 3
- 238000009747 press moulding Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 230000000712 assembly Effects 0.000 abstract 2
- 238000000429 assembly Methods 0.000 abstract 2
- 238000003466 welding Methods 0.000 abstract 2
- 239000008393 encapsulating agent Substances 0.000 abstract 1
- 239000004744 fabric Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229920003023 plastic Polymers 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- 241000196324 Embryophyta Species 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 241000219000 Populus Species 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A semiconductor package and a method for fabricating the same, the method comprising: providing a first bearing piece and a plurality of semiconductor assemblies, wherein each semiconductor assembly is provided with an action surface and a plurality of welding pads formed on the action surface; arranging the semiconductor assembly on the first bearing piece by the action surface; forming a packaging colloid on the first bearing piece to respectively coat the semiconductor assemblies, and enabling gaps to be formed among the packaging colloids; forming a buffer layer on the first carrier to cover the encapsulant and fill the gap; and removing the first bearing piece to expose the action surface, the welding pad, the packaging colloid and the buffer layer of the semiconductor component. Therefore, the invention can prevent the packaging colloid from warping and improve the yield of the semiconductor packaging piece.
Description
Technical field
The present invention relates to a kind of semiconductor package part and its preparation method, particularly relates to a kind of semiconductor packages for lifting yield
Part and its preparation method.
Background technology
It is current to be fanned out to (Fan-Out) type semiconductor package part mainly by forming packaging plastic in the whole surface of carrier
Body to multiple chips to be packaged, but because the contact area of the packing colloid and the carrier is excessive, and the heat of the packing colloid
The coefficient of expansion (Coefficient of Thermal Expansion;CTE) it is higher than the thermal coefficient of expansion of the carrier, so that the envelope
Dress colloid easily produces excessive stresses and causes warpage (warpage) situation, thus causes subsequently to be difficult in the packing colloid
The enterprising row line weight processing procedure such as cloth and singulation.
Figure 1A and Figure 1B is the schematic cross-sectional view of the preparation method for the semiconductor package part for illustrating prior art.
As shown in Figure 1A, peel ply (release layer) 11 is initially formed on carrier 10, and sets and multiple there is weld pad
121 chip 12 on the peel ply 11, re-form packing colloid 13 on the peel ply 11 to coat those chips 12.
Then, baking operation is carried out to the carrier 10, peel ply 11 and packing colloid 13, and removes the carrier 10 and the stripping
Absciss layer 11.
The shortcomings that preparation method of above-mentioned semiconductor package part, it is the packing colloid 13 and the peel ply 11 on the carrier 10
Contact area is excessive, and the thermal coefficient of expansion of the packing colloid 13 is also respectively higher than with young's modulus (Young ' s Modulus)
The thermal coefficient of expansion and young's modulus of the carrier 10 so that the packing colloid 13 easily produces the situation of warpage as shown in Figure 1B,
Thus cause subsequently to be difficult in 13 enterprising row line of the packing colloid weight processing procedure such as cloth and singulation, and reduce the semiconductor package part
Yield.
Therefore, above-mentioned problem of the prior art how is overcome, it is real into the problem for desiring most ardently solution at present.
The content of the invention
The main object of the present invention can prevent those packing colloids from producing to provide a kind of semiconductor package part and its preparation method
The situation of warpage, and lift the yield of the semiconductor package part.
The semiconductor package part of the present invention, it includes：Semiconductor subassembly, it has acting surface and is formed at the acting surface
Multiple weld pads；Packing colloid, it has relative first surface and second surface, and coats the semiconductor subassembly, and the encapsulation
The first surface of colloid exposes outside the acting surface and weld pad of the semiconductor subassembly；And cushion, it is formed at the packing colloid
Second surface on.
The packing colloid can have the side of the adjacent first surface and the second surface, and the cushion is formed at the encapsulation
On the second surface of colloid and side.
The semiconductor package part may include line layer, and it is formed on the acting surface of the semiconductor subassembly is somebody's turn to do with being electrically connected with
A little weld pads.
The present invention also provides a kind of preparation method of semiconductor package part, and it includes：One first bearing part is provided partly to lead with multiple
Body component, the semiconductor subassembly have acting surface and are formed at multiple weld pads of the acting surface；With the acting surface by the semiconductor
Component is arranged on first bearing part；Formed packing colloid on first bearing part to be respectively coated by those semiconductor groups
Part, and make that there is gap between those packing colloids；Formed cushion on first bearing part to coat those packing colloids
And insert the gap；And remove first bearing part with expose outside the acting surface of the semiconductor subassembly, weld pad, packing colloid and
Cushion.
First bearing part can have first vector and the first peel ply being formed in the first vector, the semiconductor group
Part is arranged on first peel ply with the acting surface, and those packing colloids are sequentially formed at first peel ply with the cushion
On.
The preparation method of the semiconductor package part may include the first vector that first bearing part is removed by first peel ply.
The preparation method of the semiconductor package part may include that providing one has Second support with forming second on the Second support
Second bearing part of peel ply, and after the cushion is formed, second bearing part is formed at by this with second peel ply and delayed
Rush on layer；And formed line layer on the acting surface of the first surface of the packing colloid and the semiconductor subassembly be electrically connected with
Those weld pads.
The preparation method of the semiconductor package part may include the Second support that second bearing part is removed by second peel ply；
And singulation operation is carried out to form multiple semiconductor package parts.The singulation operation can be carried out according to the side of those packing colloids
Cutting or the cushion of the gap according to those packing colloids or surrounding are cut, to form those semiconductor package parts.
In above-mentioned semiconductor package part and its preparation method, the packing colloid can be by screen painting, pressing or press moulding mode bag
It is overlying on the semiconductor subassembly.The thermal coefficient of expansion of the cushion can be less than the thermal coefficient of expansion of the packing colloid, and the buffering
The young's modulus of layer may be lower than the young's modulus of the packing colloid.The cushion can be thermal coefficient of expansion between 3 to 20ppm/
DEG C or young's modulus between 1 to 1000MPa (Megapascal) organic polymer.
From the foregoing, it will be observed that the semiconductor package part and its preparation method of the present invention, mainly set on the first bearing part and multiple partly lead
Body component, and formed packing colloid on first bearing part to be respectively coated by those semiconductor subassemblies so that those packaging plastics
There is gap between body, re-form cushion on first bearing part to coat those packing colloids and insert the gap, and
The thermal coefficient of expansion of the cushion can be less than the thermal coefficient of expansion of the packing colloid, or the young's modulus of the cushion can be less than this
The young's modulus of packing colloid.
Thereby, the present invention can make those packing colloids form composite structure with the cushion, and reduce single encapsulation
The contact area of colloid and first bearing part, so that the stress between those packing colloids and first bearing part is released,
Also the reliability of those packing colloids can be possessed, moreover it is possible to prevent those packing colloids from producing the situation of warpage, with profit subsequently at this
A little enterprising row line weight processing procedures such as cloth and singulation of packing colloid, and then lift the yield of the semiconductor package part.
Brief description of the drawings
Figure 1A and Figure 1B is the schematic cross-sectional view of the preparation method for the semiconductor package part for illustrating prior art；And
Fig. 2A to Fig. 2 I ' is the schematic cross-sectional view for the semiconductor package part and its preparation method for illustrating the present invention, wherein, Fig. 2A '
It is respectively Fig. 2A and Fig. 2 C schematic top plan view with Fig. 2 C ', Fig. 2 I and Fig. 2 I ' are respectively line of cut S and Fig. 2 H ' along Fig. 2 H
Line of cut S ' carry out singulation after schematic diagram.
Symbol description
Embodiment
Illustrate embodiments of the present invention by particular specific embodiment below, those skilled in the art can be by this explanation
Content disclosed in book understands the further advantage and effect of the present invention easily.
It should be clear that structure, ratio, size depicted in this specification institute accompanying drawings etc., only coordinating specification to be taken off
The content shown, for the understanding and reading of those skilled in the art, the enforceable qualifications of the present invention are not limited to, therefore
Do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or the adjustment of size, do not influenceing the present invention
Under the effect of can be generated and the purpose that can reach, it all should still fall and obtain the model that can cover in disclosed technology contents
In enclosing.
Meanwhile in this specification it is cited as " on ", " one ", " first ", " second ", " surface ", " acting surface " and " non-
The terms such as acting surface ", it is also only and is easy to understanding for narration, and is not used to limit the enforceable scope of the present invention, its relativeness
Be altered or modified, in the case where changing technology contents without essence, when being also considered as the enforceable category of the present invention.
Fig. 2A to Fig. 2 I ' is the schematic cross-sectional view for the semiconductor package part and its preparation method for illustrating the present invention, wherein, Fig. 2A '
It is respectively Fig. 2A and Fig. 2 C schematic top plan view with Fig. 2 C ', Fig. 2 I and Fig. 2 I ' are respectively line of cut S and Fig. 2 H ' along Fig. 2 H
Line of cut S ' carry out singulation after schematic diagram.
Such as Fig. 2A and Fig. 2A ' shown in, the first bearing part 20 is first provided, and its have first vector 201, be formed at this first
The first peel ply 202 and multiple encapsulation units 203 on carrier 201.
As shown in Figure 2 B, there is provided the semiconductor subassembly 21 of multiple such as semiconductor chips, and respectively the semiconductor subassembly 21 has
Relative acting surface 211 and non-active face 212 and the multiple weld pads 213 for being formed at the acting surface 211.Meanwhile with the acting surface
211 are arranged at the semiconductor subassembly 21 on first peel ply 202 of the encapsulation unit 203 of first bearing part 20.
As shown in Fig. 2 C and Fig. 2 C ', by screen painting, pressing (lamination) or molding (molding) mode, divide
Not Xing Cheng packing colloid 22 in, to coat those semiconductor subassemblies 21, and making on the first peel ply 202 of those encapsulation units 203
There is gap 224 between those packing colloids 22.
As shown in Figure 2 D, the cushion 23 with the 3rd relative surface 231 and the 4th surface 232 is formed first to hold in this
On first peel ply 202 of holder 20, to coat those packing colloids 22 and insert the gap 224.The cushion 23 it is hot swollen
Swollen coefficient can be less than the thermal coefficient of expansion of the packing colloid 22, and the young's modulus of the cushion 23 can be less than the packing colloid 22
Young's modulus, and the cushion 23 can be thermal coefficient of expansion between 3 to 20ppm/ DEG C or young's modulus between 1 to 1000MPa
Organic polymer.
As shown in Figure 2 E, there is provided the second bearing part 24 and its have Second support 241 with formed the Second support 241 on
Second peel ply 242, and second bearing part 24 is formed to second peel ply 242 the 4th surface of the cushion 23
On 232.
As shown in Figure 2 F, the first vector 201 of first bearing part 20 is removed by first peel ply 202, with exposed
Go out the 3rd table of the acting surface 211 of the semiconductor subassembly 21, weld pad 213, the first surface 221 of packing colloid 22 and cushion 23
Face 231.
As shown in Figure 2 G, line layer 25 is formed in the first surface 221 and the semiconductor subassembly 21 of the packing colloid 22
To be electrically connected with those weld pads 213 on acting surface 211.
Then, formed and refuse layer 26 in acting surface 211, the packaging plastic of the semiconductor subassembly 21 with multiple openings 261
On the first surface 221 of body 22, the 3rd surface 231 of cushion 23 and line layer 25, and portion is exposed outside by those openings 261
Divide the line layer 25.
Then, plant and connect multiple soldered balls 27 in those openings 261 to be electrically connected with the line layer 25.
As illustrated in figure 2h, the Second support 241 of second bearing part 24 is removed by second peel ply 242, with exposed
Go out the 4th surface 232 of the cushion 23.Afterwards, according to those packing colloids 22 side 223 and along each line of cut S carry out
Singulation (singulation) operation, to form multiple semiconductor package parts 2 as shown in figure 2i.
In another embodiment, the present invention also can be according to the gap 224 of packing colloid 22 shown in Fig. 2 H ' or the buffering of surrounding
Layer 23 simultaneously carries out singulation operation along each line of cut S ', to form each and every one more semiconductor package parts 2 ' as shown in Fig. 2 I '.
The present invention also provides a kind of semiconductor package part, as shown in figure 2i.Semiconductor package part 2 includes semiconductor subassembly
21st, packing colloid 22 and cushion 23.
The semiconductor subassembly 21 has relative acting surface 211 and non-active face 212 and is formed at the more of the acting surface 211
Individual weld pad 213.
The packing colloid 22 has relative first surface 221 and a second surface 222, and by screen painting, pressing or
Press moulding mode is coated on the semiconductor subassembly 21, and the first surface 221 of the packing colloid 22 exposes outside the semiconductor subassembly
21 acting surface 211 and weld pad 213.
The cushion 23 is formed on the second surface 222 of the packing colloid 22, and the thermal coefficient of expansion of the cushion 23
The thermal coefficient of expansion of the packing colloid 22 can be less than, and the young's modulus of the cushion 23 may be lower than the poplar of the packing colloid 22
Family name's coefficient, the cushion 23 can be thermal coefficient of expansion between 3 to 20ppm/ DEG C or young's modulus between 1 to 1000MPa it is organic
Polymer.
Above-mentioned semiconductor package part 2 may also comprise line layer 25, and it is formed at the first surface 221 of the packing colloid 22
And to be electrically connected with those weld pads 213 on the acting surface 211 of the semiconductor subassembly 21.
The semiconductor package part 2 may also comprise refuses layer 26 with multiple openings 261, and it is formed at the semiconductor subassembly
On 21 acting surface 211, the first surface 221 of packing colloid 22 and line layer 25, and part is exposed outside by those openings 261
The line layer 25.
The semiconductor package part 2 may also comprise multiple soldered balls 27, and it plants respectively is connected in those openings 261 to be electrically connected with
The line layer 25.
The present invention separately provides a kind of semiconductor package part, as shown in Fig. 2 I '.The half of semiconductor package part 2 ' and above-mentioned Fig. 2 I
Conductor packaging part 2 is roughly the same, and its Main Differences is as follows：
In Fig. 2 I ', the packing colloid 22 of semiconductor package part 2 ' can have the adjacent first surface 221 and second table
The side 223 in face 222, the cushion 23 can be formed on the second surface 222 and side 223 of the packing colloid 22.
From the foregoing, it will be observed that the semiconductor package part and its preparation method of the present invention, mainly multiple by being set on the first bearing part
Semiconductor subassembly, and formed packing colloid on first bearing part to be respectively coated by those semiconductor subassemblies so that those envelopes
There is gap between dress colloid, re-form cushion on first bearing part to coat those packing colloids and insert between this
Gap, and the thermal coefficient of expansion of the cushion can be less than the thermal coefficient of expansion of the packing colloid, or the young's modulus of the cushion can
Less than the young's modulus of the packing colloid.
Thereby, the present invention can make those packing colloids form composite structure with the cushion, and reduce single encapsulation
The contact area of colloid and first bearing part, so that the stress between those packing colloids and first bearing part is released,
Also the reliability of those packing colloids can be possessed, moreover it is possible to prevent those packing colloids from producing the situation of warpage, with profit subsequently at this
A little enterprising row line weight processing procedures such as cloth and singulation of packing colloid, and then lift the yield of the semiconductor package part.
Above-described embodiment is only to the principle and its effect of the illustrative present invention, not for the limitation present invention.Appoint
What those skilled in the art can modify under the spirit and scope without prejudice to the present invention to above-described embodiment.Therefore originally
The rights protection scope of invention, should be as listed by claims.
Claims (19)
1. a kind of semiconductor package part, it includes：
Semiconductor subassembly, it has acting surface and is formed at multiple weld pads of the acting surface；
Packing colloid, it has the side of relative first surface and second surface and the adjacent first surface and the second surface
Face, and the semiconductor subassembly is coated, and the first surface of the packing colloid exposes outside the acting surface and weld pad of the semiconductor subassembly；
And
The cushion of individual layer, it is formed on the second surface and side of the packing colloid to coat the packing colloid, and the list
Layer cushion for organic polymer to prevent the packing colloid produce warpage.
2. semiconductor package part according to claim 1, in addition to line layer, it is formed at the acting surface of the semiconductor subassembly
On to be electrically connected with those weld pads.
3. semiconductor package part according to claim 1, wherein, the packing colloid passes through screen painting, pressing or molding
Mode is coated on the semiconductor subassembly.
4. semiconductor package part according to claim 1, wherein, the thermal coefficient of expansion of the cushion of the individual layer is less than the envelope
Fill the thermal coefficient of expansion of colloid.
5. semiconductor package part according to claim 1, wherein, the young's modulus of the cushion of the individual layer is less than the encapsulation
The young's modulus of colloid.
6. semiconductor package part according to claim 1, wherein, the cushion of the individual layer for thermal coefficient of expansion between 3 to
20ppm/ DEG C or young's modulus between 1 to 1000MPa the organic polymer.
7. a kind of preparation method of semiconductor package part, it includes：
One first bearing part and multiple semiconductor subassemblies are provided, the semiconductor subassembly has acting surface and is formed at the acting surface
Multiple weld pads；
The semiconductor subassembly is arranged on first bearing part with the acting surface；
Packing colloid is formed in, to be respectively coated by those semiconductor subassemblies, and making on first bearing part between those packing colloids
With gap, the packing colloid has relative first surface and second surface and the adjacent first surface and the second surface
Side；
Formed individual layer cushion on first bearing part to coat those packing colloids and insert the gap, wherein, the list
The cushion of layer is formed on the second surface and side of the packing colloid to coat the packing colloid, and the cushion of the individual layer
For organic polymer to prevent the packing colloid produce warpage；And
First bearing part is removed to expose outside the acting surface of the semiconductor subassembly, weld pad, packing colloid and the cushion of individual layer.
8. the preparation method of semiconductor package part according to claim 7, wherein, first bearing part also have first vector with
The first peel ply being formed in the first vector, the semiconductor subassembly are arranged on first peel ply with the acting surface, should
The cushion of a little packing colloids and the individual layer is sequentially formed on first peel ply.
9. the preparation method of semiconductor package part according to claim 8, in addition to by first peel ply remove this first
The first vector of bearing part.
10. the preparation method of semiconductor package part according to claim 7, in addition to providing one has Second support should with being formed
Second bearing part of the second peel ply on Second support, and after the cushion of the individual layer is formed, will with second peel ply
Second bearing part is formed on the cushion of the individual layer.
11. the preparation method of semiconductor package part according to claim 10, in addition to line layer is formed in the semiconductor subassembly
Acting surface on to be electrically connected with those weld pads.
12. the preparation method of semiconductor package part according to claim 10, in addition to by second peel ply remove this
The Second support of two bearing parts.
13. the preparation method of semiconductor package part according to claim 12, in addition to singulation operation is carried out to form multiple half
Conductor packaging part.
14. the preparation method of semiconductor package part according to claim 13, wherein, the singulation operation is according to those packing colloids
Side carry out being cut to those semiconductor package parts.
15. the preparation method of semiconductor package part according to claim 13, wherein, the singulation operation is according to those packing colloids
Gap or the cushion of individual layer of surrounding carry out being cut to those semiconductor package parts.
16. the preparation method of semiconductor package part according to claim 7, wherein, the packing colloid passes through screen painting, pressing
Or press moulding mode is coated on the semiconductor subassembly.
17. the preparation method of semiconductor package part according to claim 7, wherein, the thermal coefficient of expansion of the cushion of the individual layer
Less than the thermal coefficient of expansion of the packing colloid.
18. the preparation method of semiconductor package part according to claim 7, wherein, the young's modulus of the cushion of the individual layer is low
In the young's modulus of the packing colloid.
19. the preparation method of semiconductor package part according to claim 7, wherein, the cushion of the individual layer is thermal coefficient of expansion
Between 3 to 20ppm/ DEG C or young's modulus between 1 to 1000MPa the organic polymer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102135635A TWI518852B (en) | 2013-10-02 | 2013-10-02 | Semiconductor package and manufacturing method thereof |
| TW102135635 | 2013-10-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104517911A CN104517911A (en) | 2015-04-15 |
| CN104517911B true CN104517911B (en) | 2018-03-27 |
Family
ID=52793007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310487209.0A Active CN104517911B (en) | 2013-10-02 | 2013-10-17 | Semiconductor package and fabrication method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104517911B (en) |
| TW (1) | TWI518852B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160141278A (en) * | 2015-05-29 | 2016-12-08 | 에스케이하이닉스 주식회사 | Semiconductor package and method of fabricating the same |
| TWI573231B (en) * | 2015-07-17 | 2017-03-01 | 矽品精密工業股份有限公司 | Package substrate and method of manufacture thereof |
| US10206288B2 (en) | 2015-08-13 | 2019-02-12 | Palo Alto Research Center Incorporated | Bare die integration with printed components on flexible substrate |
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| CN102543905A (en) * | 2010-12-22 | 2012-07-04 | 矽品精密工业股份有限公司 | Semiconductor package and method of manufacturing the same |
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| TW201515163A (en) | 2015-04-16 |
| TWI518852B (en) | 2016-01-21 |
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