CN203165882U - Stacked package structure - Google Patents
Stacked package structure Download PDFInfo
- Publication number
- CN203165882U CN203165882U CN 201220733943 CN201220733943U CN203165882U CN 203165882 U CN203165882 U CN 203165882U CN 201220733943 CN201220733943 CN 201220733943 CN 201220733943 U CN201220733943 U CN 201220733943U CN 203165882 U CN203165882 U CN 203165882U
- Authority
- CN
- China
- Prior art keywords
- substrate
- crystal grain
- package structure
- pin group
- stack package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A stacked package structure comprises a first substrate, a second substrate, a first crystalline grain and a second crystalline grain. The first substrate can be combined with the second substrate through a lead frame arranged in the first substrate. Thus, a packaged and finished chip can be thoroughly protected and has great heat dissipation ability; the reliability of packaged and finished products can be enhanced; a part of packaging process can be carried out separately; the thickness of an entire packaged and finished product is not increased; and at the same time, package time and cost can be controlled.
Description
Technical field
The utility model relates to a kind of encapsulating structure, particularly relevant for a kind of encapsulating structure that the stacked type semiconductor package structure is improved.
Background technology
In today, electronic product is with human life interwoveness, and market wishes that always electronic product can dwindle as much as possible, lightweight, for the size of electronic product can be accorded with the demands of the market, certainly will will continue electronic component is dwindled.
Present state-of-the-art semiconductor technology has all reached the level of calculating size with nanometer, the encapsulation that will carry out electronic component under this kind size is not a simple thing, and the quality of electronic package has very big influence to the quality of electronic product, therefore operation or the worker's method in encapsulation has any breakthrough, improvement, all is huge contribution to whole industry circle.
For encapsulating structure is dwindled as far as possible, sometimes may be at two crystal grain of same substrate encapsulation, shown in Figure 1A, it is a kind of laminate packaging structure that US Patent No. 6365963 discloses, the middle section of first substrate 92 has a groove 95, configuration first crystal grain 91 in the groove 95, and groove 95 tops dispose second crystal grain 90, and in groove 95, fill encapsulated layer 97, the first crystal grain 91 and second crystal grain 90 all has and substrate lead 93 electrically connects.
And in order to dwindle the laminate packaging thickness of structure more, as shown in Figure 1B, US Patent No. 6365963 has disclosed another kind of laminate packaging structure again, be with last structure difference, first crystal grain 91 is disposed on second substrate 94, again in conjunction with first substrate 92 and second substrate 94, and first crystal grain 91 is positioned among the base openings 96 of first substrate 92, and among base openings 96, fills encapsulated layer 97.
Above laminate packaging structure after improvement; because of first crystal grain 91 (for example: a kind of control chip of memory chip) and second crystal grain 90 (for example: be not to be disposed on the same substrate a kind of memory chip); so can be with this two procedures separately; reach the effect of saving encapsulation time and cost; and can obtain thinner encapsulation finished product; but this kind laminate packaging structure still has shortcoming; for example: the crystal grain of finishing when encapsulation be a kind of memory chip (for example: NAND FLASH); and memory chip regular meeting produces high heat when running; if with memory chip package in encapsulated layer 97; chip may descend because of the relatively poor reliability that causes of dispelling the heat, and the heat-sinking capability of first crystal grain 91 also can become poorer because of the same side that is positioned at first substrate 92 and second substrate 94 with second crystal grain 90.
According to above shortcoming, the utility model proposes a kind of stack package structure, this kind encapsulating structure has encapsulated layer, but does not increase the thickness of whole encapsulation finished product, and has improved the heat-sinking capability of encapsulation back chip, further can promote the reliability of encapsulation finished product.
The utility model content
In order to solve above-mentioned relevant problem; a main purpose of the present utility model is to provide a kind of laminate packaging structure; by two different substrates are piled up; and form an encapsulating structure that makes chip have heat-sinking capability and be protected, and the thickness of whole encapsulating structure does not increase to some extent compared to the known package thickness of structure.
The utility model provides a kind of stack package structure, comprise: one first substrate, have a first surface and a relative second surface, and in two groups of last pin groups that are relative arrangement of upward configuration of first surface, and on each the pin group by a plurality of to be spaced and to be formed to first metal wire of both sides fan-out, and dispose two groups of following pin groups that are relative arrangement in going up of second surface, and the pin group is formed with spaced second metal wire by a plurality of under each, and wherein going up between pin group and the following pin group is to be electrically connected by a plurality of substrate leads that are arranged in first substrate; One first crystal grain has a lower surface, a plurality of first weld pads of configuration on the lower surface, and first crystal grain electrically connects each first wire ends among each first weld pad and the last pin group to cover crystal type; One second crystal grain has a upper surface, a plurality of second weld pads of configuration on the upper surface, and second crystal grain electrically connects each second metal end among each second weld pad and the following pin group to cover crystal type; One second substrate has one the 3rd surface, and has a base openings to be positioned at second substrate center zone and run through second substrate, and the 3rd surface engages with the second surface of first substrate, and second chip is placed among the base openings; And a plurality of metal couplings, be disposed on the fan out of each first metal wire of first surface, and electrically connect with each first metal wire among the last pin group.
Wherein this first substrate is a kind of printed circuit board (PCB).
Wherein the material of this first substrate is pi.
Wherein said pin group, described pin group down and the described substrate lead gone up formed by a lead frame.
Wherein the material of this second substrate is pi.
Wherein this first crystal grain is a kind of memory chip.
Wherein this memory chip is a kind of flash chip.
This second crystal grain control chip that is a kind of memory wherein.
Wherein the height of this metal coupling is higher than this first upper surface of this first crystal grain.
Wherein further dispose a macromolecular material in this base openings, in order to coat this second crystal grain.
Carried out the encapsulation work of twin crystal grain by stack package structure provided by the utility model, by the improvement to encapsulating structure, make the chip after the encapsulation have preferable heat-sinking capability, and be not vulnerable to damage because excessively exposing to the open air, further promote the reliability of encapsulation finished product; In addition, stack package structure that the utility model proposes, wherein each packaging process can separately carry out, and after each operation is finished, only need through simple combination, can finish whole encapsulation finished product, so can additionally not increase the thickness of packaging body, also can control time and the cost of encapsulation simultaneously.
Description of drawings
For making the auditor can further understand structure of the present utility model, feature and purpose thereof, below in conjunction with accompanying drawing and preferred embodiment describes in detail as after, wherein:
Figure 1A is known laminate encapsulating structure generalized section;
Figure 1B is known laminate encapsulating structure generalized section;
Fig. 2 is board structure profile of the present utility model;
Fig. 3 is board structure array top view of the present utility model;
Fig. 4 is view under the board structure array of the present utility model;
Fig. 5 is the second substrate top view of the present utility model;
Fig. 6 is stack package structure generalized section of the present utility model.
Embodiment
The utility model is a kind of stack package structure, and by the improvement to structure, the efficient of raising encapsulation also reduces cost, and encapsulation worker method or the operation wherein mentioned are all the known semiconductor correlation technique, so in following explanation, and imperfect description.In addition, the accompanying drawing in following in the literary composition, not according to the actual complete drafting of relative dimensions, its effect is only being expressed the schematic diagram relevant with the utility model feature.
At first, seeing also Fig. 2, is board structure profile of the present utility model.As shown in Figure 2, board structure 2 comprises a substrate 12 and a plurality of metal coupling 19, and wherein, substrate 12 is made up of macromolecular material, for example: printed circuit board (PCB) or poly-inferior acyl ammonium (Polyimide); Substrate 12 has first surface 122 and opposing second surface 123, two groups of last pin groups 126 that are relative arrangement of configuration on first surface 122, it is to be spaced and to be formed to the metal wire 1262 of first surface 122 both sides fan-outs (Fan out) by a plurality of that each group goes up pin group 126, pin group 126 and form the first crystal grain configuring area 1260 on two groups on the first surface 122, and two groups of following pin groups 128 that are relative arrangement of configuration on second surface 123, each group pin group 128 is down formed with spaced metal wire 1282 by a plurality of, pin group 128 and form the second crystal grain configuring area 1280 at the middle section of second surface 123 under two groups on the second surface 123, last pin group 126 and down 128 of pin groups electrically connect by the many substrate leads 124 that are arranged in first substrate 12; A plurality of metal couplings 19 are disposed at the both sides of first surface 122, and with last pin group 126 in the fan out of each metal wire 1262 electrically connect; In addition, last pin group 126, following pin group 128 and substrate lead 124 are made up of lead frame (Lead frame).
Then, seeing also Fig. 3 and Fig. 4, is view under board structure array top view of the present utility model and the board structure array of the present utility model.As shown in Figure 3, many groups board structure 2 as shown in Figure 2 can be formed an array, look in top by substrate 12, can see that pin group 126 and metal coupling 19 are disposed at the left and right sides of first surface 122 on two groups on the first surface 122 of every group substrate structure 2, and be the first crystal grain configuring area 1260 on the left and right sides between the pin group 126; As shown in Figure 3, looked by the below of substrate 12, can see that pin group 128 is disposed at the middle section of first surface under two groups on the second surface of every group substrate structure 2, and be the second crystal grain configuring area 1280 under the left and right sides between the pin group 128.
Then, seeing also Fig. 5, is the second substrate top view of the present utility model.As shown in Figure 5, the material of second substrate 14 is macromolecular material, for example: poly-inferior acyl ammonium; Second substrate 14 has one the 3rd surface 142, and the middle section of second substrate 14 has many group substrates opening 140 to run through second substrate 14 from the 3rd surface 142, and the position of each base openings 140 and size all can be corresponding with the second crystal grain configuring area 1280 on each board structure 2 shown in Figure 4.
Following, see also Fig. 6, is stack package structure generalized section of the present utility model.As shown in Figure 6, first crystal grain 16 is a kind of memory chip, a kind of flash chip (NANDFLASH) particularly, the lower surface 160 that first crystal grain 16 has a upper surface 164 to reach with respect to upper surface 164, a plurality of first weld pads 162 of configuration on the lower surface 160, first crystal grain 16 is disposed on the first surface 122 by the last pin group 126 formed first crystal grain configuring area 1260, first crystal grain 16 electrically connects each metal wire 1262 among each first weld pad 162 and the last pin group 126 to cover crystal type (Flip chip), the height of metal coupling 19 also is higher than the upper surface 164 of first crystal grain 16, when avoiding stack package structure 1 to place in first surface 122 mode down, first crystal grain 16 damages because being squeezed; Second crystal grain 18 is a kind of control chip of memory, and a upper surface 180 arranged, a plurality of second weld pads 182 of configuration on the upper surface 180, second crystal grain 18 is disposed on the second surface 123 and each metal wire 1282 among each second weld pad 182 and the following pin group 128 is electrically connected to cover crystal type by the following pin group 128 formed second crystal grain configuring area, 1280, the second crystal grain 18; Make the 3rd surface 142 of second substrate 14 and the second surface 123 relative and joints of first substrate 12, and second crystal grain 18 is placed in the base openings 140 of second substrate 14, the height of second crystal grain 18 is less than or equal to the thickness of substrate 14, make second crystal grain 18 can be subjected to excellent protection, and directly contact external environment because of second crystal grain 18, and first crystal grain 16 and second crystal grain 18 lay respectively at first surface 122 and the second surface 123 of first substrate 12, San Re process can not interfere with each other each other, and makes first crystal grain 16 and second crystal grain 18 that enough heat-sinking capabilities can both be arranged; The configuration mode of all the other elements is all identical with the described board structure of Fig. 22, so repeat no more.
In addition, if need be to second crystal grain 18 during with isolated from atmosphere, also can be chosen in the base openings 140 of second substrate 14 and inject macromolecular material (not being shown in figure), for example: epoxy resin (epoxy); Macromolecular material (not being shown among the figure) can coat whole second crystal grain 18, makes crystal grain 18 energy and atmospheric isolations.
Carried out the encapsulation work of first crystal grain 16 and second crystal grain 18 by stack package structure 1 provided by the utility model, by the improvement to encapsulating structure, be the following of thick situation at the more known encapsulating structure of the thickness that does not make stack package structure 1, and make first crystal grain 16 and second crystal grain 18 after the encapsulation that heat dissipation capability be arranged, and be not vulnerable to damage because excessively exposing to the open air, further promote the reliability of encapsulation finished product; And the production process of first substrate 12 and second substrate 14 also can separate synchronously and carries out, and has effectively controlled and has encapsulated required time and cost.
Though the utility model discloses as above with aforesaid preferred embodiment; so it is not in order to limit the utility model; anyly have the knack of alike operator; in not breaking away from spirit and scope of the present utility model; when can doing a little change and retouching, therefore scope of patent protection of the present utility model must be looked being as the criterion that claim scope of the present utility model defines.
Claims (10)
1. a stack package structure is characterized in that, comprising:
One first substrate, have a first surface and a relative second surface, and in two groups of last pin groups that are relative arrangement of upward configuration of this first surface, and each should go up pin group by many to be spaced and to be formed to first metal wire of both sides fan-out, and dispose two groups of following pin groups that are relative arrangement in going up of this second surface, and each this time pin group is formed with spaced second metal wire by many, is to be electrically connected by a plurality of substrate leads that are arranged in this first substrate between wherein said last pin group and the described following pin group;
One first crystal grain has one first upper surface and with respect to the lower surface of this first upper surface, a plurality of first weld pads of configuration on this lower surface, this first crystal grain with cover crystal type with each first weld pad with should go up that each this first metal wire electrically connects among the pin group;
One second crystal grain has one second upper surface, a plurality of second weld pads of configuration on this second upper surface, and this second crystal grain is to cover crystal type each this second metal wire electric connection among this second weld pad and this time pin group with each;
One second substrate has one the 3rd surface, and has a base openings to be positioned at this second substrate center zone and run through this second substrate, and the 3rd surface engages with this second surface of this first substrate, and this second chip is placed among this base openings; And
A plurality of metal couplings are disposed on the fan out of each this first metal wire of this first surface, and with this on each this first metal wire among the pin group electrically connect.
2. stack package structure according to claim 1, wherein this first substrate is a kind of printed circuit board (PCB).
3. stack package structure according to claim 1, wherein the material of this first substrate is pi.
4. stack package structure according to claim 1, wherein said pin group, described pin group down and the described substrate lead gone up formed by a lead frame.
5. stack package structure according to claim 1, wherein the material of this second substrate is pi.
6. stack package structure according to claim 1, wherein this first crystal grain is a kind of memory chip.
7. stack package structure according to claim 6, wherein this memory chip is a kind of flash chip.
8. stack package structure according to claim 1, wherein this second crystal grain control chip that is a kind of memory.
9. stack package structure according to claim 1, wherein the height of this metal coupling is higher than this first upper surface of this first crystal grain.
10. stack package structure according to claim 1 wherein further disposes a macromolecular material in this base openings, in order to coat this second crystal grain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220733943 CN203165882U (en) | 2012-12-27 | 2012-12-27 | Stacked package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220733943 CN203165882U (en) | 2012-12-27 | 2012-12-27 | Stacked package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203165882U true CN203165882U (en) | 2013-08-28 |
Family
ID=49027047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220733943 Expired - Fee Related CN203165882U (en) | 2012-12-27 | 2012-12-27 | Stacked package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203165882U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104183554A (en) * | 2013-05-21 | 2014-12-03 | 三星电机株式会社 | electronic device module and manufacturing method thereof |
| CN110707051A (en) * | 2019-10-14 | 2020-01-17 | 华天科技（西安）有限公司 | SSD storage chip packaging structure with heat dissipation cover and manufacturing method |
| CN110767615A (en) * | 2019-10-14 | 2020-02-07 | 华天科技（西安）有限公司 | SSD storage chip packaging structure and manufacturing method |
| WO2020125309A1 (en) * | 2018-12-20 | 2020-06-25 | 惠州Tcl移动通信有限公司 | Storage device with multiple storage crystal grains, and identification method |
-
2012
- 2012-12-27 CN CN 201220733943 patent/CN203165882U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104183554A (en) * | 2013-05-21 | 2014-12-03 | 三星电机株式会社 | electronic device module and manufacturing method thereof |
| WO2020125309A1 (en) * | 2018-12-20 | 2020-06-25 | 惠州Tcl移动通信有限公司 | Storage device with multiple storage crystal grains, and identification method |
| US11869621B2 (en) | 2018-12-20 | 2024-01-09 | Huizhou Tcl Mobile Communication Co., Ltd. | Storage device having multiple storage dies and identification method |
| CN110707051A (en) * | 2019-10-14 | 2020-01-17 | 华天科技（西安）有限公司 | SSD storage chip packaging structure with heat dissipation cover and manufacturing method |
| CN110767615A (en) * | 2019-10-14 | 2020-02-07 | 华天科技（西安）有限公司 | SSD storage chip packaging structure and manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11171120B2 (en) | Integrated circuit package assembly | |
| US7655503B2 (en) | Method for fabricating semiconductor package with stacked chips | |
| TWI390645B (en) | Back-to-back chip assembly stacked packaging method and structure | |
| CN103311230A (en) | Chip stacking structure and manufacturing method thereof | |
| JP2011086943A (en) | Semiconductor package, and electronic device and memory storage apparatus using the semiconductor package | |
| CN102903691A (en) | Semiconductor devices, packaging methods and structures | |
| CN203165882U (en) | Stacked package structure | |
| CN202549824U (en) | Chip packaging structure | |
| CN102376676A (en) | Package substrate embedded with semiconductor chip | |
| KR101219484B1 (en) | Semiconductor chip module and semiconductor package having the same and package module | |
| US20150214192A1 (en) | Structure and formation method of chip package structure | |
| CN105990304A (en) | Chip packaging structure and manufacture method thereof | |
| CN101211792A (en) | Semi-conductor package and its manufacture method and stacking structure | |
| CN101131992A (en) | Multi-chip stacking type packaging structure | |
| KR20110138788A (en) | Stack type semiconductor package | |
| US20140118978A1 (en) | Package substrate and chip package using the same | |
| KR100668858B1 (en) | Stack type package module and manufacture method thereof | |
| TWI474411B (en) | Semiconductor device structure and method for fabricating the same | |
| CN102556938B (en) | Stacked die package structure and manufacturing method thereof | |
| CN102751203A (en) | Semiconductor encapsulation structure and manufacture method of semiconductor encapsulation structure | |
| CN102176448A (en) | Fan-out system-in-package structure | |
| CN202977406U (en) | A multi-wafer stacking encapsulating structure preventing wafer fracture caused by wire bonding | |
| CN101315921B (en) | Chip stack packaging structure and method of producing the same | |
| CN103354225A (en) | Stack packaging device | |
| KR101133137B1 (en) | Semiconductor package substrate being folded |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130828 Termination date: 20151227 |
|
| EXPY | Termination of patent right or utility model |