CN202977406U - A multi-wafer stacking encapsulating structure preventing wafer fracture caused by wire bonding - Google Patents

A multi-wafer stacking encapsulating structure preventing wafer fracture caused by wire bonding Download PDF

Info

Publication number
CN202977406U
CN202977406U CN2012205994876U CN201220599487U CN202977406U CN 202977406 U CN202977406 U CN 202977406U CN 2012205994876 U CN2012205994876 U CN 2012205994876U CN 201220599487 U CN201220599487 U CN 201220599487U CN 202977406 U CN202977406 U CN 202977406U
Authority
CN
China
Prior art keywords
wafer
routing
rubber cushion
substrate
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN2012205994876U
Other languages
Chinese (zh)
Inventor
陈永祥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Walton Advanced Engineering Inc
Original Assignee
Walton Advanced Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Walton Advanced Engineering Inc filed Critical Walton Advanced Engineering Inc
Priority to CN2012205994876U priority Critical patent/CN202977406U/en
Application granted granted Critical
Publication of CN202977406U publication Critical patent/CN202977406U/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512Aligning
    • H01L2224/85148Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518Translational movements
    • H01L2224/85181Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Packaging Frangible Articles (AREA)
  • Buffer Packaging (AREA)

Abstract

The utility model discloses a multi-wafer stacking encapsulating structure preventing wafer fracture caused by wire bonding. The structure comprises a first substrate, a first wafer, wire-bonding supporting adhesive pads, a second wafer, multiple first soldering wires, and multiple second soldering wires. The first wafer is disposed on the substrate and comprises first wire-bonding side edges on which multiple first soldering pads are arranged and first non wire-bonding side edges. The wire-bonding supporting adhesive pads are disposed on the substrate and close to the first non wire-bonding side edges. The second wafer disposed on the first wafer and the wire-bonding supporting adhesive pads does not cover the first wafer and forms unoverlapped parts. The second wafer comprises second wire-bonding side edges on which multiple second soldering pads on the wire-bonding supporting adhesive pads are arranged. The multiple first soldering wires are electrically connected with the substrate via the first soldering pads. The multiple second soldering wires are electrically connected with the substrate via the second soldering pads. The wire-bonding supporting adhesive pads comprise non-conducting viscose glue. After the wire-bonding supporting adhesive pads are pasted on the second wafer, adhesive surfaces formed by solidifying the wire-bonding supporting adhesive pads are same high as the first wafer. The structure resolves problems of fracture of the bonded second wafer and infirm soldered wires.

Description

Avoid routing to cause the multi-wafer stack package structure of wafer fracture
Technical field
The utility model is relevant for semiconductor package, particularly relevant for a kind of multi-wafer stack package structure of avoiding routing to cause the wafer fracture.
Background technology
In semiconductor package, the set-up mode that replaces wafer side offside (side-by-side), the multi-wafer stack package structure of wafer stacking on wafer more can be saved package dimension, common wafer stacking process wherein all needs to make the heating process of adhesive curing for wafer, routing connection, erection bay partition being installed, again the repeating step such as wafer being installed in each installation steps.Yet, use at present the multi-wafer stack package structure that routing connects to produce the problem that repetitive process is too many, the yield reduction is even made in the package thickness increase along with the increase of wafer stacking quantity.
Fig. 1 has illustrated the schematic cross-section that existing routing causes the multi-wafer stack package structure 300 of wafer fracture, and Fig. 2 has illustrated the schematic diagram of wafer fracture above this multi-wafer stack package structure 300 causes in the routing process.this multi-wafer stack package structure 300 comprises that mainly one has the substrate 310 of line construction, in order to carry one first wafer 320, after this first wafer 320 is installed on this substrate 310, routing forms a plurality of the first bonding wires 351, refer to 311 with the first weld pad 323 to the connecing of this substrate 310 that is electrically connected this first wafer 320, install again just like adhesive tape, empty wafer uniformly-spaced sheet 330 on this first wafer 320, one second wafer 340 is installed afterwards on this distance piece 330, routing forms a plurality of the second bonding wires 352, refer to 311 with the second weld pad 343 to the connecing of this substrate 310 that is electrically connected this second wafer 340.After all wafers all was arranged on this substrate 310 and successively completes the routing operation of individual wafer, the mould envelope formed an adhesive body 360 in this substrate 310, with sealing wafer 320,340 and bonding wire 351,352.The external terminal 370 of a plurality of for example soldered balls is set at the lower surface of this substrate 310 at last.As shown in Figure 2; after this second wafer 340 is installed; when utilizing one can provide the routing capillary 10 of the second bonding wire to carry out the routing operation of this second wafer 340; because this second wafer 340 has laterally projecting hanging part in this distance piece 330 and this a plurality of the second weld pads 343 are positioned at this hanging part; this routing capillary 10 puts on the fracture (as the wafer breaking part 344 of Fig. 2) that weld force often can cause this second wafer 340 that presses down of these a plurality of the second weld pads 343, also has the second bonding wire 352 welderings not firm in the problem of the second weld pad 343.Particularly, during this second wafer 340 thinner (as wafer thickness less than 10 Mills), the problems referred to above are with even more serious.
The utility model content
In order to address the above problem, the utility model provides a kind of multi-wafer stack package structure of avoiding routing to cause the wafer fracture, can carry out the routing operation of a plurality of chip thinnings and not have the wafer fracture welding not firm problem with bonding wire.
The routing of avoiding that the utility model provides causes the multi-wafer stack package structure of wafer fracture, comprises that mainly a substrate, one first wafer, a routing support rubber cushion (wire-bonding supporting adhesive pad), one second wafer, a plurality of the first bonding wire and a plurality of the second bonding wire.This first wafer is arranged on this substrate, and this first wafer has one first routing side and one first without the routing side, and wherein this first routing side is arranged with a plurality of the first weld pads.This routing support that rubber cushion is arranged on this substrate and contiguous this first without the routing side.This second wafer is arranged at this first wafer and this routing and supports on rubber cushion and do not cover these a plurality of first weld pads and be formed with a not overlapping part that is not overlapped in this first wafer, this second wafer has one second routing side, wherein this second routing side is arranged with a plurality of the second weld pads, and these a plurality of second weld pads are positioned at this routing to be supported on rubber cushion.These a plurality of first bonding wires are electrically connected these a plurality of first weld pads to this substrate.These a plurality of second bonding wires are electrically connected these a plurality of second weld pads to this substrate.Wherein, this routing supports rubber cushion and comprises non-conductive viscose glue, and it is contour that this routing support rubber cushion is bonded to the bonding plane and this first wafer that solidify to form after this second wafer.This routing support that rubber cushion is bonded to this second wafer this do not solidify that this routing supports rubber cushion after overlapping part and the bonding plane and this first wafer that form are contour.
Preferably, the back side of this second wafer is formed with an insulating barrier, and this routing supports rubber cushion and is bonded to this insulating barrier.Even therefore this second wafer is still had suitable structural strength and this routing to support rubber cushion under the obstruct of this insulating barrier by thinning, the glue that can not overflow is climbed to the side of this second wafer.
Preferably, this first wafer and this second wafer are that cross is staggeredly stacked.The stacking more wafer take two wafers as the mode of a group.
Preferably, this routing supports rubber cushion and coordinates the shape of this first wafer to be modified to arbitrary shape in bar shaped, agglomerate shape, square, L shaped and U-shaped.
Preferably, the non-conductive viscose glue of this routing support rubber cushion is thermosetting.
Preferably, the non-conductive viscose glue of this routing support rubber cushion is thermoplasticity.
Preferably, this routing support that rubber cushion is bonded to this first wafer simultaneously this first without routing side and this substrate, make this first wafer, this second wafer and this substrate become the combination of stronger adhesion, the mould with opposing when this adhesive body of formation flows impact.
Preferably, this second wafer is as distance piece, and the camber of these a plurality of the first bonding wires is no more than these a plurality of second weld pads to the height of this substrate, so that the wafer of greater number to be set in limited stacks as high.
Preferably, also comprise one the 3rd wafer and one the 4th wafer, the 3rd wafer is arranged on this second wafer and is provided with a plurality of the 3rd weld pads, the 4th wafer is arranged on the 3rd wafer and does not cover these a plurality of the 3rd weld pads and be provided with a plurality of the 4th weld pads, one second routing supports rubber cushion and is arranged on this second wafer, so that being positioned at this second routing, support on rubber cushion these a plurality of the 4th weld pads, this second routing supports rubber cushion and comprises non-conductive viscose glue, and this second routing supports rubber cushion and comprises a bonding plane contour with the 3rd wafer.
Preferably, comprise that also one covers the line colloid, be arranged on this first wafer, coat the first local bonding wire and bonding the 3rd wafer.
In aforesaid multi-wafer stack package structure, can also include an adhesive body, be formed on this substrate, to seal this first wafer, this second wafer, these a plurality of first bonding wires and this a plurality of the second bonding wires.Utilize this routing to support the setting of rubber cushion, can avoid first being difficult to mould joint material place without routing side etc. and forming mould envelope air pocket (molding air trap) at this of this first wafer.
In aforesaid multi-wafer stack package structure, can also comprise a plurality of external terminals, be arranged at a lower surface of this substrate, be provided as this multi-wafer stack package structure to outer engagement.
The utlity model has following beneficial effect:
The multi-wafer stack package structure of avoiding routing to cause the wafer fracture of the present utility model, sequence is sorted on the non-complete overlapping stacking and substrate of the common carrying of rubber cushion for the wafer of odd number and routing support be the wafer of even number (or odd number), and the wafer take sequence as even number is the sept between the wafer of odd number as sequence, to reach the effect of ultrathin routing wafer stacking.
Description of drawings
Fig. 1: existing routing causes the schematic cross-section of the multi-wafer stack package structure of wafer fracture.
Fig. 2: existing routing causes the schematic cross-section of multi-wafer stack package structure in the routing operation of wafer fracture.
Fig. 3: according to a kind of schematic cross-section of avoiding routing to cause the multi-wafer stack package structure of wafer fracture of the first specific embodiment of the present utility model.
Fig. 4: this multi-wafer stack package structure according to the first specific embodiment of the present utility model is looked schematic diagram on routing is preoperative.
Fig. 5: according to the schematic cross-section of this multi-wafer stack package structure when routing operates of the first specific embodiment of the present utility model.
Fig. 6: according to looking schematic diagram on routing support rubber cushion variable shape in this multi-wafer stack package structure of the first specific embodiment of the present utility model.
Fig. 7: avoid routing to cause the schematic cross-section of the multi-wafer stack package structure of wafer fracture according to the another kind of the second specific embodiment of the present utility model.
Fig. 8: the schematic cross-section of this multi-wafer stack package structure of foundation the second specific embodiment of the present utility model its first wafer of crosscut before routing operation for the second time.
Fig. 9: the schematic cross-section that supports rubber cushion according to this multi-wafer stack package structure its routing of crosscut before routing operation for the second time of the second specific embodiment of the present utility model.
The main element symbol description:
10 routing capillaries;
100 multi-wafer stack package structures; 110 substrates;
111 first connect finger; 112 second connect finger;
120 first wafers; 121 first routing sides;
122 first without the routing side; 123 first weld pads;
130 routings support rubber cushion; 131 bonding planes;
140 second wafers; 141 overlapping parts not;
142 second routing sides; 143 second weld pads;
144 insulating barriers;
151 first bonding wires; 152 second bonding wires;
160 adhesive bodies; 170 external terminals;
200 multi-wafer stack package structures;
232 second routings support rubber cushion; 233 bonding planes;
234 cover the line colloid;
253 the 3rd bonding wires; 254 the 4th bonding wires;
280 the 3rd wafers; 281 the 3rd weld pads;
290 the 4th wafers; 291 the 4th weld pads;
300 multi-wafer stack package structures;
310 substrates; 311 connect finger;
320 first wafers; 323 first weld pads;
330 distance pieces;
340 second wafers; 343 second weld pads;
344 wafer breaking parts;
351 first bonding wires; 352 second bonding wires;
360 adhesive bodies; 370 external terminals.
Embodiment
Below will coordinate appended diagram to describe embodiment of the present utility model in detail, and it should be noted, this diagram is the product schematic diagram, and shown person is shape and the dimension scale of actual enforcement, only as a kind of specific design of putting property of choosing, so that clearer description to be provided.In the equivalence embodiment of different application, the shape of element, size and quantity all can dwindle, amplify or simplify.
According to the first specific embodiment of the present utility model, schematic cross-section, Fig. 4 that a kind of multi-wafer stack package structure of avoiding routing to cause the wafer fracture is illustrated in Fig. 3 look schematic diagram and the schematic cross-section of Fig. 5 when routing operates on routing is preoperative.This multi-wafer stack package structure 100 comprises that mainly a substrate 110, one first wafer 120, a routing support rubber cushion 130 (wire-bonding supporting adhesive pad), one second wafer 140, a plurality of the first bonding wire 151 and a plurality of the second bonding wire 152.This substrate 110 can be a miniature printed circuit board with single/multiple layer line construction, and the upper surface of this substrate 110 is provided with a plurality of first and connects and refer to that 111 and a plurality of second connect finger 112.
This first wafer 120 is arranged on this substrate 110, and this first wafer 120 has one first routing side 121 and one first without routing side 122 (as shown in Figure 4), and wherein this first routing side 121 is arranged with a plurality of the first weld pads 123.The surface that this first wafer 120 has these a plurality of the first weld pads 123 can be the active surface that is formed with integrated circuit, can be memory, logic element, controller or Application Specific Integrated Circuit.This routing support that rubber cushion 130 is arranged on this substrate 110 and contiguous this first without routing side 122.This routing supports rubber cushion 130 and comprises non-conductive viscose glue, for example crystal grain patch material (DAM, Die Attach Material), epoxy resin or the two-sided pi adhesive tape that is provided with suitable thickness thermosetting viscose glue.This non-conductive viscose glue can be thermosetting for better, and in different embodiment, this non-conductive viscose glue can be thermoplasticity.Preferably, it is B rank viscose glue bodies (B-stage adhesive) that this routing supports rubber cushion 130, be that the A stage is liquid when being coated with when imposing on this substrate 110, before this second wafer 140 is set, be the thick attitude of semi-solid preparation B rank glue through the part baking, before routing forms these a plurality of second bonding wires 152, first solidify C rank solid-state.
This second wafer 140 is arranged at this first wafer 120 and this routing and supports on rubber cushion 130 and do not cover these a plurality of first weld pads 123 and be formed with a not overlapping part 141 that is not overlapped in this first wafer 120, this second wafer 140 has one second routing side 142, wherein this second routing side 142 is arranged with a plurality of the second weld pads 143, and these a plurality of second weld pads 143 are positioned at this routing to be supported on rubber cushion 130 and obtain the support effect below wafer when routing.This second wafer 140 can be the wafer identical with these the first wafer 120 essence, or the wafer of identical function not.Preferably, the back side of this second wafer 140 can be formed with an insulating barrier 144, and this routing supports rubber cushion 130 and is bonded to this insulating barrier 144.Even therefore this second wafer 140 is still had suitable structural strength and this routing to support rubber cushion 130 under the obstruct of this insulating barrier 144 by thinning, the glue that can not overflow is climbed to the side of this second wafer 140.
These a plurality of first bonding wires 151 are formed by routing with these a plurality of second bonding wires 152.This a plurality of first weld pads 123 that these a plurality of first bonding wires 151 are electrically connected these the first wafers 120 to this of this substrate 110 a plurality of first connects finger 111.This a plurality of second weld pads 143 that these a plurality of second bonding wires 152 are electrically connected these the second wafers 140 to this of this substrate 110 a plurality of second connects finger 112.
Wherein, this that supports that rubber cushion 130 is bonded to this second wafer 140 when this routing not overlapping part 141 sides solidifies this routing and supports rubber cushion 130, has a bonding plane 131 contour with this first wafer 120 and make this routing support rubber cushion 130.
As shown in Figure 5, routing is to form this a plurality of the first bonding wires 151 and these a plurality of second bonding wires 152 at the same time, when a dozen wire bonding pin 10 pressure weldings therein during second weld pad 143, this routing supports glue and provides and coplanar sticking brilliant support of this first wafer 120, can not cause the fracture of this second wafer 140 to weld the problems such as not firm, empty weldering, dry joint with these a plurality of second bonding wires 152 on the second weld pad 143.Therefore, the routing of avoiding that the utility model provides causes the multi-wafer stack package structure 100 of wafer fracture, can carry out the routing operation of a plurality of chip thinnings and not have the wafer fracture welding not firm problem with bonding wire.In the present embodiment, as shown in Figure 4, this first wafer 120 can be cross with this second wafer 140 and is staggeredly stacked, the stacking more wafer take two wafers as the mode of a group.
More specifically, this multi-wafer stack package structure 100 can separately include an adhesive body 160, is formed on this substrate 110, to seal this first wafer 120, this second wafer 140, these a plurality of first bonding wires 151 and this a plurality of the second bonding wires 152.Utilize this routing to support the setting of rubber cushion 130, can avoid being difficult to mould joint material place's formation mould envelope air pocket (molding air trap) at first of this first wafer 120 without routing side 122 grades.In addition, this multi-wafer stack package structure 100 can separately comprise a plurality of external terminals 170, and soldered ball for example is arranged at a lower surface of this substrate 110, be provided as this multi-wafer stack package structure 100 to outer engagement.
Preferably, this routing support rubber cushion 130 can be bonded to simultaneously this first wafer 120 first without routing side 122 and this substrate 110, make this first wafer 120, this second wafer 140 and this substrate 110 become the combination of stronger adhesion, the mould stream with opposing when forming this adhesive body 160 impacts.
As shown in Figure 6, what this routing supported that rubber cushion 130 can coordinate this first wafer 120 is modified to the bar shaped as Fig. 6 (A), the agglomerate shape of Fig. 6 (B) without the routing side, as the approximate square of Fig. 6 (C), as the L shaped of Fig. 6 (D) and as the arbitrary shape in the U-shaped of Fig. 6 (E).
According to the second specific embodiment of the present utility model, another kind avoids routing to cause the multi-wafer stack package structure 200 of wafer fracture to be illustrated in the schematic cross-section of Fig. 7, the schematic cross-section of Fig. 8 its first wafer 120 of crosscut before routing operation for the second time and the schematic cross-section that Fig. 9 its routing of crosscut before routing operation for the second time supports rubber cushion 130.This multi-wafer stack package structure 200 comprises that mainly a substrate 110, one first wafer 120, a routing support rubber cushion 130, one second wafer 140, a plurality of the first bonding wire 151 and a plurality of the second bonding wire 152.To continue to use same reference numbers with element identical in the first specific embodiment, and repeat no more its thin section structure.
This first wafer 120 is arranged on this substrate 110, and this first wafer 120 has one first routing side and one first without the routing side, and wherein this first routing side is arranged with a plurality of the first weld pads 123.This routing support that rubber cushion 130 is arranged on this substrate 110 and contiguous this first without the routing side.This second wafer 140 is arranged at this first wafer 120 and this routing and supports on rubber cushion 130 and do not cover these a plurality of first weld pads 123 and be formed with a position (being positioned at the position that this routing supports rubber cushion 130 tops as this second wafer 140 in Fig. 7) that is not overlapped in this first wafer 120, this second wafer 140 has one second routing side, wherein this second routing side is arranged with a plurality of the second weld pads 143, and these a plurality of second weld pads 143 are positioned at this routing to be supported on rubber cushion 130.The first weld pad 123 to first of this substrate 110 that these a plurality of first bonding wires 151 are electrically connected this first wafer 120 connects and refers to 111.The second weld pad 143 to second of this substrate 110 that these a plurality of second bonding wires 152 are electrically connected this second wafer 140 connects and refers to 112.Wherein, this routing supports rubber cushion 130 and comprises the non-conductive viscose glue of thermosetting, solidify this routing and support rubber cushion 130 after this routing supports this position that rubber cushion 130 is bonded to this second wafer 140, have a bonding plane 131 contour with this first wafer 120 and make this routing support rubber cushion 130.
Preferably, this second wafer 140 can be used as distance piece, and the camber of these a plurality of the first bonding wires 151 is no more than the second weld pad 143 to the height of this substrate 110, so that the wafer of greater number to be set in limited stacks as high.
in the present embodiment, this multi-wafer stack package structure 200 can separately include one the 3rd wafer 280 and one the 4th wafer 290, the 3rd wafer 280 is arranged on this second wafer 140 and is provided with a plurality of the 3rd weld pads 281, the 4th wafer 290 is arranged on the 3rd wafer 280 and does not cover these a plurality of the 3rd weld pads 281 and have a plurality of the 4th weld pads 291, one second routing supports rubber cushion 232 and is arranged on this second wafer 140, so that being positioned at this second routing, support on rubber cushion 232 these a plurality of the 4th weld pads 291, this second routing supports rubber cushion 232 and also comprises the non-conductive viscose glue of thermosetting, this second routing supports rubber cushion 232 and has a bonding plane 131 contour with the 3rd wafer 280.Therefore in routing operation for the second time, routing forms a plurality of the 3rd bonding wires 253 and a plurality of the 4th bonding wires 254 simultaneously, and the 3rd weld pad 281 to first of this substrate 110 that these a plurality of the 3rd bonding wires 253 are electrically connected the 3rd wafer 280 connects and refers to 111.The 4th weld pad 291 to second of this substrate 110 that these a plurality of the 4th bonding wires 354 are electrically connected the 4th wafer 290 connects and refers to 112.
As shown in Figure 8, in the present embodiment, this multi-wafer stack package structure 200 can comprise separately that one covers line colloid 234, is arranged on this first wafer 120, to coat the first local bonding wire 151 and bonding the 3rd wafer 280.
Therefore, this multi-wafer stack package structure can make on substrate sequence sort on the non-complete overlapping stacking and substrate of the common carrying of rubber cushion for the wafer of odd number and routing support to be the wafer of even number, and the wafer take sequence as even number is the sept between the wafer of odd number as sequence, to reach the effect of ultrathin routing wafer stacking.
The above embodiment is the preferred embodiment that proves absolutely that the utility model is lifted, and protection range of the present utility model is not limited to this.Being equal to that those skilled in the art do on the utility model basis substitutes or conversion, all within protection range of the present utility model.Protection range of the present utility model is as the criterion with claims.

Claims (10)

1. a multi-wafer stack package structure of avoiding routing to cause the wafer fracture, is characterized in that, mainly comprises:
One substrate;
One first wafer is arranged on this substrate, and this first wafer has one first routing side and one first without the routing side, and wherein this first routing side is arranged with a plurality of the first weld pads;
One routing supports rubber cushion, be arranged on this substrate and contiguous this first without the routing side;
One second wafer, being arranged at this first wafer and this routing supports on rubber cushion and does not cover these a plurality of first weld pads and be formed with a not overlapping part that is not overlapped in this first wafer, this second wafer has one second routing side, wherein this second routing side is arranged with a plurality of the second weld pads, and these a plurality of second weld pads are positioned at this routing to be supported on rubber cushion;
A plurality of the first bonding wires are electrically connected these a plurality of first weld pads to this substrate; And
A plurality of the second bonding wires are electrically connected these a plurality of second weld pads to this substrate;
Wherein, this routing supports rubber cushion and comprises non-conductive viscose glue, this routing support that rubber cushion is bonded to this second wafer this do not solidify that this routing supports rubber cushion after overlapping part and the bonding plane and this first wafer that form are contour.
2. the multi-wafer stack package structure of avoiding routing to cause the wafer fracture according to claim 1, is characterized in that, the back side of this second wafer is formed with an insulating barrier, and this routing supports rubber cushion and is bonded to this insulating barrier.
3. the multi-wafer stack package structure of avoiding routing to cause the wafer fracture according to claim 1, is characterized in that, this first wafer and this second wafer are that cross is staggeredly stacked.
4. the multi-wafer stack package structure of avoiding routing to cause wafer fracture according to claim 1, is characterized in that, this routing supports rubber cushion and coordinates the shape of this first wafer to be modified to arbitrary shape in bar shaped, agglomerate shape, square, L shaped and U-shaped.
5. the multi-wafer stack package structure of avoiding routing to cause the wafer fracture according to claim 1, is characterized in that, the non-conductive viscose glue that this routing supports rubber cushion is thermosetting.
6. the multi-wafer stack package structure of avoiding routing to cause the wafer fracture according to claim 1, is characterized in that, the non-conductive viscose glue that this routing supports rubber cushion is thermoplasticity.
7. the multi-wafer stack package structure of avoiding routing to cause wafer fracture according to claim 1, is characterized in that, this routing support that rubber cushion is bonded to this first wafer simultaneously this first without routing side and this substrate.
8. the multi-wafer stack package structure of avoiding routing to cause the wafer fracture according to claim 1, is characterized in that, this second wafer is as distance piece, and the camber of these a plurality of the first bonding wires is no more than these a plurality of second weld pads to the height of this substrate.
9. the multi-wafer stack package structure of avoiding routing to cause wafer fracture according to claim 1, it is characterized in that, also comprise one the 3rd wafer and one the 4th wafer, the 3rd wafer is arranged on this second wafer and is provided with a plurality of the 3rd weld pads, the 4th wafer is arranged on the 3rd wafer and does not cover these a plurality of the 3rd weld pads and be provided with a plurality of the 4th weld pads, one second routing supports rubber cushion and is arranged on this second wafer, so that being positioned at this second routing, support on rubber cushion these a plurality of the 4th weld pads, this second routing supports rubber cushion and comprises non-conductive viscose glue, this second routing supports rubber cushion and comprises a bonding plane contour with the 3rd wafer.
10. the multi-wafer stack package structure of avoiding routing to cause the wafer fracture according to claim 9, is characterized in that, comprises that also one covers the line colloid, is arranged on this first wafer, coats the first local bonding wire and bonding the 3rd wafer.
CN2012205994876U 2012-11-14 2012-11-14 A multi-wafer stacking encapsulating structure preventing wafer fracture caused by wire bonding Expired - Lifetime CN202977406U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2012205994876U CN202977406U (en) 2012-11-14 2012-11-14 A multi-wafer stacking encapsulating structure preventing wafer fracture caused by wire bonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2012205994876U CN202977406U (en) 2012-11-14 2012-11-14 A multi-wafer stacking encapsulating structure preventing wafer fracture caused by wire bonding

Publications (1)

Publication Number Publication Date
CN202977406U true CN202977406U (en) 2013-06-05

Family

ID=48518448

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2012205994876U Expired - Lifetime CN202977406U (en) 2012-11-14 2012-11-14 A multi-wafer stacking encapsulating structure preventing wafer fracture caused by wire bonding

Country Status (1)

Country Link
CN (1) CN202977406U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015149462A1 (en) * 2014-04-04 2015-10-08 利亚德光电股份有限公司 Wafer circuit
WO2016044993A1 (en) * 2014-09-23 2016-03-31 华为技术有限公司 Radio frequency power assembly and transceiver device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015149462A1 (en) * 2014-04-04 2015-10-08 利亚德光电股份有限公司 Wafer circuit
WO2016044993A1 (en) * 2014-09-23 2016-03-31 华为技术有限公司 Radio frequency power assembly and transceiver device
US10347596B2 (en) 2014-09-23 2019-07-09 Huawei Technologies Co., Ltd. Radio frequency power component and radio frequency signal transceiving device

Similar Documents

Publication Publication Date Title
CN100570871C (en) Semiconductor device and manufacture method thereof
CN103946976A (en) Two level leadframe with upset ball bonding surface and device package
US8093104B1 (en) Multi-chip stacking method to reduce voids between stacked chips
CN101656248A (en) Chip-stacked package structure of substrate with groove and packaging method thereof
CN103250246A (en) Method and system for thin multi chip stack package with film on wire and copper wire
WO2013007029A1 (en) Chip-on-package structure for multiple die stacks
CN202977406U (en) A multi-wafer stacking encapsulating structure preventing wafer fracture caused by wire bonding
CN203165882U (en) Stacked package structure
CN101131992A (en) Multi-chip stacking type packaging structure
CN206584961U (en) A kind of LED support, LED support array, LED component and LED display
CN204118064U (en) The wafer level packaging unit that a kind of chip tilts stacking
CN104008982B (en) Chip packaging process and chip package
CN103208467B (en) Package module with embedded package and method for manufacturing the same
CN100559582C (en) Chip stack package structure and manufacture method thereof
CN107492534A (en) Pitch list IC chip packaging part and preparation method thereof
CN101378048A (en) Packaging structure for stacking multiple chips
CN102556938B (en) Stacked die package structure and manufacturing method thereof
TWI321349B (en) Multi-chip stack package
CN100356533C (en) Central welding pad memory body stacking encapsulating assembly and encapsulating process thereof
CN101236962A (en) Multi-chip stacking structure and its making method
CN104201168A (en) Wafer level package unit with chips stacked obliquely and package method
CN105590904A (en) Fingerprint identification multi-chip package structure and preparation method thereof
CN101303985B (en) Stack type chip packaging structure production method
CN101388380A (en) Multi-chip stacking construction for lead frame on chip and chip on lead frame
CN101853845B (en) Multichip stacking encapsulation

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20130605