CN107492534A - Pitch list IC chip packaging part and preparation method thereof - Google Patents

Pitch list IC chip packaging part and preparation method thereof Download PDF

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Publication number
CN107492534A
CN107492534A CN201710656820.XA CN201710656820A CN107492534A CN 107492534 A CN107492534 A CN 107492534A CN 201710656820 A CN201710656820 A CN 201710656820A CN 107492534 A CN107492534 A CN 107492534A
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China
Prior art keywords
pad
aluminum layer
bronze medal
chip
electroplated aluminum
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CN201710656820.XA
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Chinese (zh)
Inventor
朱文辉
杨辉
李军辉
何虎
陈卓
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Changsha Anmuquan Intelligent Technology Co., Ltd.
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Central South University
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Priority to CN201710656820.XA priority Critical patent/CN107492534A/en
Publication of CN107492534A publication Critical patent/CN107492534A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49107Connecting at different heights on the semiconductor or solid-state body
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85007Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the wire connector during or after the bonding process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009Pre-treatment of the connector or the bonding area
    • H01L2224/85051Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

The invention discloses a kind of pitch list IC chip packaging part and preparation method thereof, wherein, packaging part includes plastic-sealed body, pin in lead frame carrier and multiple support leads is provided with plastic-sealed body, the upper surface of lead frame carrier is connected with IC chip, the upper surface of IC chip is provided with multiple pads, multiple pads are arranged in parallel in two rows, form the first pad group and the second pad group, each pad is connected respectively pin in a support lead by copper bonding line, the upper surface of multiple pads in each pad group is arranged at intervals with electroplated aluminum layer, the pad that electroplated aluminum layer is provided with one pad group is corresponding with the pad that electroplated aluminum layer is not provided with another pad group.Adjacent welds are not easy short circuit in the packaging part, and product yield is high, quality is good, and preparation method cost of the invention is low, production efficiency is high.

Description

Pitch list IC chip packaging part and preparation method thereof
Technical field
The present invention relates to electronic component manufacturing technology field, and in particular to a kind of pitch list IC chip packaging part and its Preparation method.
Background technology
In the present age, manufacture of microchips has also quickly marched toward nanometer era, chip manufacturing with the high speed development of electronics industry Process from the 90nm of beginning to reduce 13nm till now even lower.Therefore the physical dimension of chip also reduces till now 0.15mm × 0.15mm.And it is corresponding, pad pitch, the road plan used in chip manufacturing also progressively narrows down to 45 μ m.So that pad size is also gradually reduced as 38 μm present of 38 μ m.The change of this size brings a series of to bonding technology Problem and challenge.
Under normal circumstances, in ball bonding technique, the criterion of acceptability of soldered ball is more than or equal to 2 times of line footpath for diameter, Less than 5 times of line footpath.The controlled diameter system of general gold thread soldered ball exists in 2~2.3 times of line footpaths, the controlled diameter system of copper cash soldered ball 2.5~3 times of line footpaths.For 38 μ m, 38 μm of pad, 41 μm~43 μm of adjacent pad spacing, 15 μm~Φ of Φ 16 can only be used μm bonding wire, and the diameter for being bonded soldered ball must be controlled within 37 μm.So gold thread no matter 15 μm of (2.3 × 15=of Φ 34.5 < 37) or 16 μm of Φ (16 × 2.3=36.8 < 37), meet pressure welding requirement.And no matter 15 μm of Φ (removes the limit 15 to copper cash × 2.5=37.5 > 37), or 16 μm of Φ (16 × 2.5=40 of capping > 37), do not comply with pressure welding requirement.
Also, said from the angle of pressure welding quality inspection, the space between adjacent bondwires should be equal to 2 times of bonding wire diameter.It is real On border, line footpath is removed, 1.69~1.86 times of space line footpath between adjacent bonding wire, adjacent two bonding lines spacing can not meet general matter Amount requires.But with the raising of bonding wire quality, the increasing of line footpath specification, the development of encapsulation technology and high-density packages form And the increase of product, on the premise of ensureing that the plastic packaging rate of breasting the tape meets technological requirement, not short-circuit between bonding wire and bonding wire, adjacent legs Between space more than 1 times line footpath also by industry generally acknowledge can meet bonding wire craft requirement.
But for the bonding to pitch pad, the diameter of bond ball is difficult control, is not paid attention to slightly, bond ball will Beyond pad, cause adjacent welds short-circuit, cause product rejection.Further, since line spacing is too small, can encounter when playing second line Preceding single line, the damage of single line before causing.Therefore, pitch pad (38 38 μm of μ m) copper wire bonding of pitch≤43 μm Maximum difficulty be the control of bonding point Diameter of Solder Ball and damage adjacent bonding wire the problem of.
The content of the invention
It is an object of the present invention to overcome the shortcomings of to mention in background above technology and defect, there is provided a kind of adjacent welds The pitch list IC chip packaging part of short circuit is not easy, and accordingly provides a kind of above-mentioned pitch list IC chip packaging part Preparation method.
In order to solve the above technical problems, technical scheme proposed by the present invention is:
A kind of pitch list IC chip packaging part, including plastic-sealed body, the plastic-sealed body are interior provided with lead frame carrier and more Pin in individual support lead, the upper surface of the lead frame carrier are connected with IC chip, and the upper surface of the IC chip is provided with Multiple pads, multiple pads are arranged in parallel in two rows, form the first pad group and the second pad group, each pad pass through copper Bonding line is connected respectively pin in a support lead, and the upper surface of multiple pads in each pad group is arranged at intervals with Electroplated aluminum layer, pad phase of the pad of electroplated aluminum layer with being not provided with electroplated aluminum layer in another pad group is provided with a pad group It is corresponding.
Above-mentioned pitch list IC chip packaging part, it is preferred that the thickness of the electroplated aluminum layer is 28 μm~32 μm, aluminium electricity The appearance and size of coating is 35 μm of 35 μ m.
Above-mentioned pitch list IC chip packaging part, it is preferred that pitch≤43 μm of the pad, the appearance and size of pad For 38 μm of 38 μ m.
Above-mentioned pitch list IC chip packaging part, it is preferred that the copper bonding line includes the first bronze medal bonding line and second Copper bonding line, one end of the first bronze medal bonding line is by the first bronze medal bond ball for being welded on electroplated aluminum layer and is provided with electroplated aluminum The pad of layer is connected, and the other end looping arcing of the first bronze medal bonding line is welded with pin in corresponding support lead, and described the One end of two bronze medal bonding lines is connected by the second bronze medal bond ball being directly welded on pad with being not provided with the pad of electroplated aluminum layer Connect, the other end looping arcing of the second bronze medal bonding line is welded with pin in corresponding support lead.
Above-mentioned pitch list IC chip packaging part, it is furthermore preferred that a diameter of 35 μm~38 μ of the first bronze medal bond ball M, a diameter of 34 μm~37 μm of the second bronze medal bond ball.
The technical concept total as one, another aspect of the present invention provide a kind of above-mentioned pitch list IC chip packaging part Preparation method, comprise the following steps:
S1, mask plate is covered and electroplated in the upper surface of IC chip, in the multiple of the first pad group and the second pad group Interval forms electroplated aluminum layer on pad, is corresponded on the mask plate and is provided with electroplating hole at the electroplated aluminum layer;
S2, the wafer of IC chip is thinned to 290 μm~310 μm and scribing;
S3, lead frame carrier is taken, IC chips of the step S2 after reduction scribing is fixed in lead frame carrier, Toasted under inert atmosphere;
S4, copper cash axle is fixed on pressure welding platform, penetrates copper cash, the lead frame of IC chip will be connected with obtained by step S3 It is sent to after carrier preheating on pressure welding platform, a first bronze medal bond ball, then up looping arcing is stacked on each electroplated aluminum layer Pin in the support lead corresponding with the pad provided with electroplated aluminum layer, and a brazing is played on pin in the support lead Point, form the first bronze medal bonding line;
S5, on the pad of electroplated aluminum layer is not provided with copper ball bonding formed the second bronze medal bond ball, looping arcing to this Pin in the corresponding support lead of pad, and a brazing point is made a call on pin in the support lead, form the second bronze medal bonding line;
S6, carry out plastic packaging successively to the lead frame carrier that the first bronze medal bonding line and the second bronze medal bonding line is welded, be rear solid Change, print and separate, produce pitch list IC chip packaging part.
Above-mentioned preparation method, it is preferred that in the step S3, inert atmosphere specifically refers to nitrogen atmosphere, nitrogen flow For 25mL/min~30mL/min, the time of baking is 2.5h~3.5h, and baking temperature is 140 DEG C~160 DEG C.
Above-mentioned preparation method, it is preferred that in the step S4, the lead frame carrier for being connected with IC chip is first preheated It is then sent through after to 200 DEG C~210 DEG C on pressure welding platform.
Compared with prior art, the advantage of the invention is that:The present invention using special mask plate in the first pad group and Electroplated aluminum layer is arranged at intervals on the pad of second pad group, the first bronze medal bond ball is then welded on electroplated aluminum layer, is not had at remaining Have and the second bronze medal bond ball is directly welded on the pad of electroplated aluminum layer.Adjacent pad is set to form difference in height using electroplated aluminum layer, not only Avoid and crater is produced on pad, and avoid adjacent welds short circuit.When both having solved the bonding of pitch small pad high density Easily damage before single line and cause plastic packaging breast the tape open circuit the problem of, turn avoid adjacent welds short circuit problem.In addition, this hair Bright to be bonded from copper wire, its bond strength be better than gold thread, is breasted the tape rate so as to reduce plastic packaging, improves product quality, section About bonding wire cost.The package structure advantages of simple of the present invention, can be applied to more pin packages and stacked package.The present invention adopts Difference in height is formed between adjacent pad with electroplated aluminum layer, compared to by the way of gold goal is bonded, although adding one of plating Technique, but reduce one of bonding technology, comparatively speaking, advantageously in saving production cost, raising production efficiency.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are the present invention Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis These accompanying drawings obtain other accompanying drawings.
Fig. 1 is the structural representation of pitch list IC chip packaging part of the present invention.
Fig. 2 is the partial enlarged drawing at A in Fig. 1.
Fig. 3 is the internal structure schematic top plan view of pitch list IC chip packaging part of the present invention.
Fig. 4 is the structural representation of mask plate.
Marginal data:
1st, plastic-sealed body;2nd, lead frame carrier;3rd, pin in support lead;4th, IC chip;5th, pad;6th, electroplated aluminum layer; 7th, the first bronze medal bonding line;8th, the second bronze medal bonding line;9th, the first bronze medal bond ball;10th, the second bronze medal bond ball;11st, mask plate;12nd, it is electric Plated hole.
Embodiment
For the ease of understanding the present invention, the present invention is made below in conjunction with Figure of description and preferred embodiment more complete Face, meticulously describe, but protection scope of the present invention is not limited to embodiment in detail below.
It should be strongly noted that when a certain element, to be described as " be fixed on, be fixed in, be connected to or be communicated in " another When on element, it can be directly fixed, affixed, connection or connect on another element or by connecting among other Fitting is indirectly fixed, affixed, connection or connection are on another element.
Unless otherwise defined, the implication that all technical terms used hereinafter are generally understood that with those skilled in the art It is identical.Technical term used herein is intended merely to describe the purpose of specific embodiment, is not intended to the limitation present invention Protection domain.
Embodiment:
A kind of pitch list IC chip packaging part of the invention, its structure as shown in Figures 1 to 4, from Fig. 1 to Fig. 4, It mainly includes plastic-sealed body 1, and pin 3 in lead frame carrier 2 and multiple support leads, lead frame are provided with plastic-sealed body 1 The upper surface of carrier 2 is connected with IC chip 4 by bonding die glue, and the upper surface of the IC chip 4 is provided with multiple pads 5.The plurality of weldering Disk 5 is arranged in parallel in two rows, forms the first pad group and the second pad group.Each pad 5 is corresponded to respectively by copper bonding line Connect pin 3 in a support lead.The upper surface of multiple pads 5 in each pad group is arranged at intervals with electroplated aluminum layer 6.One The pad 5 of electroplated aluminum layer 6 is provided with individual pad group with being not provided with the position phase of pad 5 of electroplated aluminum layer 6 in another pad group It is corresponding.Electroplated aluminum layer 6 is arranged at intervals with by the upper surface of multiple pads 5 in pad group, makes to be formed between adjacent pad 5 Difference in height, the situation of adjacent welds short circuit, improves product yield when avoiding pitch list IC chip copper wire bonding, also, It is simpler using the one side technique of electroplated aluminum layer 6, be advantageous to improve production efficiency, on the other hand compared to gold bonding ball cost more It is low.
In the present embodiment, the thickness of electroplated aluminum layer 6 is preferably 28 μm~32 μm, and the appearance and size of electroplated aluminum layer 6 is 35 μm ×35μm.Pitch≤43 μm of pad 5, the appearance and size of pad 5 is 38 μm of 38 μ m.
In the present embodiment, copper bonding line includes the first bronze medal bonding line 7 and the second bronze medal bonding line 8.Wherein, the first bronze medal bonding line 7 one end is connected by the first bronze medal bond ball 9 being welded on electroplated aluminum layer 6 with the pad 5 provided with electroplated aluminum layer 6, and first The other end looping arcing of copper bonding line 7 is welded with pin 3 in corresponding support lead.One end of second bronze medal bonding line 8 passes through The second bronze medal bond ball 10 being directly welded on pad 5 is connected with being not provided with the pad 5 of electroplated aluminum layer 6, the second bronze medal bonding line 8 The arcing of other end looping welded with pin 3 in corresponding support lead.The diameter of first bronze medal bond ball 9 is preferably 35 μm~38 μm, the diameter of the second bronze medal bond ball 10 is preferably 34 μm~37 μm.
The preparation method of the pitch list IC chip packaging part is as follows:
The first step, mask plate 11 is covered and electroplated in the upper surface of IC chip 4, in the first pad group and the second pad group Multiple pads 5 on interval form electroplated aluminum layer 6, corresponded on mask plate 11 and electroplating hole 12 be provided with electroplated aluminum layer 6, the electroplating hole 12 size is consistent with electroplated aluminum layer 6, and mask plate 11 uses glass material, its size and the IC chip 4 in lead frame carrier 2 Unanimously;
Second step, the wafer of IC chip 4 is thinned to 290 μm~310 μm and scribing;
3rd step, lead frame carrier 2 is taken, the IC chip 4 after reduction scribing is fixed in lead frame carrier 2, Toasted in a nitrogen atmosphere, nitrogen flow control is in 25mL/min~30mL/min, baking 2.5h~3.5h, baking temperature Control is at 140 DEG C~160 DEG C.
4th step, copper cash axle is fixed on pressure welding platform, penetrates copper cash, the lead frame carrier 2 of IC chip 4 will be connected with It is sent to after being preheated to 200 DEG C~210 DEG C on pressure welding platform, a first bronze medal bond ball 9 is stacked on each electroplated aluminum layer 6, then Upward looping arcing pin 3 extremely in the support lead corresponding with the pad 5 provided with electroplated aluminum layer 6, and in the support lead A brazing point is made a call on pin 3, forms the first bronze medal bonding line 7;
5th step, the second bronze medal bond ball 10 is formed with copper ball bonding on the pad 5 for be not provided with electroplated aluminum layer 6, looping is drawn Arc makes a call to a brazing point to pin 3 in the support lead corresponding with the pad 5 in the support lead on pin 3, formation the Two bronze medal bonding lines 8;
6th step, the lead frame carrier 2 that the first bronze medal bonding line 7 and the second bronze medal bonding line 8 is welded is moulded successively Envelope, solidify afterwards, printing and punching separation or cutting separation, produce pitch list IC chip packaging part.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for the skill of this area For art personnel, the present invention can have various modifications and variations.Within the spirit and principles of the invention, that is made any repaiies Change, equivalent substitution, improvement etc., should be included in the scope of the protection.

Claims (8)

1. a kind of pitch list IC chip packaging part, including plastic-sealed body (1), the plastic-sealed body (1) is interior to be provided with lead frame carrier (2) and in multiple support leads pin (3), the upper surface of the lead frame carrier (2) are connected with IC chip (4), the IC The upper surface of chip (4) is provided with multiple pads (5), and multiple pads (5) are arranged in parallel in two rows, formed the first pad group and Second pad group, each pad (5) are connected respectively pin (3) in a support lead by copper bonding line, it is characterised in that: The upper surface of multiple pads (5) in each pad group is arranged at intervals with electroplated aluminum layer (6), and aluminium electricity is provided with a pad group The pad (5) of coating (6) is corresponding with the pad (5) that electroplated aluminum layer (6) are not provided with another pad group.
2. pitch list IC chip packaging part according to claim 1, it is characterised in that:The thickness of the electroplated aluminum layer (6) Spend for 28 μm~32 μm, the appearance and size of electroplated aluminum layer (6) is 35 μm of 35 μ m.
3. pitch list IC chip packaging part according to claim 1, it is characterised in that:The pitch of the pad (5)≤ 43 μm, the appearance and size of pad (5) is 38 μm of 38 μ m.
4. pitch list IC chip packaging part according to claim 1, it is characterised in that:The copper bonding line includes first Copper bonding line (7) and the second bronze medal bonding line (8), one end of the first bronze medal bonding line (7) is by being welded on electroplated aluminum layer (6) The first bronze medal bond ball (9) be connected with provided with the pad (5) of electroplated aluminum layer (6), the other end looping of the first bronze medal bonding line (7) Arcing is welded with pin (3) in corresponding support lead, and one end of the second bronze medal bonding line (8) is by being directly welded at pad (5) the second bronze medal bond ball (10) on is connected with being not provided with the pad (5) of electroplated aluminum layer (6), the second bronze medal bonding line (8) it is another One end looping arcing is welded with pin (3) in corresponding support lead.
5. pitch list IC chip packaging part according to claim 4, it is characterised in that:The first bronze medal bond ball (9) A diameter of 35 μm~38 μm, a diameter of 34 μm~37 μm of the second bronze medal bond ball (10).
6. such as the preparation method of pitch list IC chip packaging part according to any one of claims 1 to 5, including following step Suddenly:
S1, mask plate (11) is covered and electroplated in the upper surface of IC chip (4), in the more of the first pad group and the second pad group Interval forms electroplated aluminum layer (6) on individual pad (5), and electroplated aluminum layer (6) place is corresponded on the mask plate (11) and is provided with plating Hole (12);
S2, the wafer of IC chip (4) is thinned to 290 μm~310 μm and scribing;
S3, lead frame carrier (2) is taken, IC chips (4) of the step S2 after reduction scribing is fixed in lead frame carrier (2) On, toasted under an inert atmosphere;
S4, copper cash axle is fixed on pressure welding platform, penetrates copper cash, the lead frame of IC chip (4) will be connected with obtained by step S3 It is sent to after carrier (2) preheating on pressure welding platform, a first bronze medal bond ball (9) is stacked on each electroplated aluminum layer (6), then up Pin (3) in looping arcing to the support lead corresponding with the pad (5) provided with electroplated aluminum layer (6), and in the support lead A brazing point is made a call on interior pin (3), forms the first bronze medal bonding line (7);
S5, form the second bronze medal bond ball (10), looping arcing with copper ball bonding on the pad (5) for be not provided with electroplated aluminum layer (6) Pin (3) in the support lead corresponding with the pad (5), and a brazing point, shape are made a call on pin (3) in the support lead Into the second bronze medal bonding line (8);
S6, the lead frame carrier (2) that the first bronze medal bonding line (7) and the second bronze medal bonding line (8) is welded is carried out successively plastic packaging, Solidify afterwards, printing and separation, produce pitch list IC chip packaging part.
7. preparation method according to claim 6, it is characterised in that:In the step S3, inert atmosphere specifically refers to nitrogen Gas atmosphere, nitrogen flow are 25mL/min~30mL/min, and time of baking is 2.5h~3.5h, baking temperature is 140 DEG C~ 160℃。
8. the preparation method according to claim 6 or 7, it is characterised in that:In the step S4, IC chip will be connected with (4) lead frame carrier (2) is then sent through on pressure welding platform after being first preheated to 200 DEG C~210 DEG C.
CN201710656820.XA 2017-08-03 2017-08-03 Pitch list IC chip packaging part and preparation method thereof Pending CN107492534A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108206640A (en) * 2017-12-28 2018-06-26 重庆平伟实业股份有限公司 A kind of synchronous rectification module, method for rectifying and its manufacturing method
CN109699129A (en) * 2019-01-22 2019-04-30 广东气派科技有限公司 Solve method and SMD component that SMD component crosses wave-soldering bridge

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101217124A (en) * 2008-01-18 2008-07-09 清华大学 A low temperature flip chip method of macromolecule electric conducting material of template printing
CN102437141A (en) * 2011-12-09 2012-05-02 天水华天科技股份有限公司 Dense-pitch small-pad copper-wire bonded single intelligent card (IC) chip packing piece and preparation method thereof
CN102437147A (en) * 2011-12-09 2012-05-02 天水华天科技股份有限公司 Dense-pitch small-pad copper-line bonded intelligent card (IC) chip stacking packing piece and preparation method thereof
CN103107155A (en) * 2013-01-29 2013-05-15 福州瑞芯微电子有限公司 Double aluminum pad structure and achieving method thereof
CN106373930A (en) * 2015-07-20 2017-02-01 台湾积体电路制造股份有限公司 Wafer level package and method for forming the same
CN106684053A (en) * 2017-03-10 2017-05-17 中芯长电半导体(江阴)有限公司 Silicon wafer stage chip scale packaging structure and manufacturing method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101217124A (en) * 2008-01-18 2008-07-09 清华大学 A low temperature flip chip method of macromolecule electric conducting material of template printing
CN102437141A (en) * 2011-12-09 2012-05-02 天水华天科技股份有限公司 Dense-pitch small-pad copper-wire bonded single intelligent card (IC) chip packing piece and preparation method thereof
CN102437147A (en) * 2011-12-09 2012-05-02 天水华天科技股份有限公司 Dense-pitch small-pad copper-line bonded intelligent card (IC) chip stacking packing piece and preparation method thereof
CN103107155A (en) * 2013-01-29 2013-05-15 福州瑞芯微电子有限公司 Double aluminum pad structure and achieving method thereof
CN106373930A (en) * 2015-07-20 2017-02-01 台湾积体电路制造股份有限公司 Wafer level package and method for forming the same
CN106684053A (en) * 2017-03-10 2017-05-17 中芯长电半导体(江阴)有限公司 Silicon wafer stage chip scale packaging structure and manufacturing method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
孙承松: "《薄膜技术及应用》", 30 August 1998 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108206640A (en) * 2017-12-28 2018-06-26 重庆平伟实业股份有限公司 A kind of synchronous rectification module, method for rectifying and its manufacturing method
CN109699129A (en) * 2019-01-22 2019-04-30 广东气派科技有限公司 Solve method and SMD component that SMD component crosses wave-soldering bridge

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