CN105575911A - Semiconductor package and fabrication method thereof - Google Patents
Semiconductor package and fabrication method thereof Download PDFInfo
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- CN105575911A CN105575911A CN201410537603.5A CN201410537603A CN105575911A CN 105575911 A CN105575911 A CN 105575911A CN 201410537603 A CN201410537603 A CN 201410537603A CN 105575911 A CN105575911 A CN 105575911A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 115
- 238000000034 method Methods 0.000 title claims description 50
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 239000000084 colloidal system Substances 0.000 claims abstract description 101
- 239000010410 layer Substances 0.000 claims description 154
- 238000012856 packing Methods 0.000 claims description 96
- 239000011241 protective layer Substances 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 9
- 238000012545 processing Methods 0.000 claims description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- 239000011135 tin Substances 0.000 claims description 4
- 229910001316 Ag alloy Inorganic materials 0.000 claims description 2
- 229910001020 Au alloy Inorganic materials 0.000 claims description 2
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 2
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 2
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 abstract 4
- 239000008393 encapsulating agent Substances 0.000 abstract 2
- 235000012431 wafers Nutrition 0.000 description 11
- 239000013078 crystal Substances 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A semiconductor package and a manufacturing method thereof are provided, wherein the semiconductor package comprises a package colloid, a semiconductor element, a plurality of conductive columns and a build-up structure. The encapsulant has opposite first and second surfaces. The semiconductor element is embedded in the packaging colloid and is provided with an active surface and a passive surface which are opposite, and the active surface is arranged at the same side of the first surface of the packaging colloid. The conductive column is embedded in the packaging colloid and is provided with a first end part and a second end part which are opposite to each other so as to be respectively exposed out of the first surface and the second surface of the packaging colloid. The build-up structure is formed on the first surface of the encapsulant and electrically connected to the semiconductor element and the first end of the conductive pillar. Therefore, the invention can electrically connect the layer-adding structure to the conductive post without precise alignment.
Description
Technical field
The present invention, about a kind of semiconductor package part and method for making thereof, refers to a kind of semiconductor package part and the method for making thereof that are electrically connected layer reinforced structure with conductive pole especially.
Background technology
Have in the semiconductor package part of increasing layer (build-up) structure or fan-out (fan-out) structure at present, be common in packing colloid and form multiple through hole, and form line layer to be electrically connected the conductive blind hole of layer reinforced structure on this packing colloid with in those through holes, but accurate contraposition need be carried out to those through holes and those conductive blind holes.
Figure 1A to Fig. 1 H illustrates the semiconductor package part 1 of prior art and the cross-sectional schematic of method for making thereof.
As shown in Figure 1A, first provide the first loading plate 10, and setting has the wafer 11 of multiple weld pad 111 and relative active surface 11a and passive 11b on this first loading plate 10.
Then, formed there is relative first surface 12a and second surface 12b packing colloid 12 on this first loading plate 10, expose outside passive 11b of this wafer 11 with this wafer 11 coated.
As shown in Figure 1B, the second loading plate 13 is set on passive 11b of this wafer 11, and by the overall structure turned upside down of Figure 1B, and remove this first loading plate 10.
As shown in Figure 1 C, layer reinforced structure 14 is formed on the active surface 11a of this wafer 11 and the first surface 12a of this packing colloid 12.This layer reinforced structure 14 has at least one dielectric layer 141, is multiplely formed at conductive blind hole 142 in this dielectric layer 141 and at least one first line layer 143 be formed on this dielectric layer 141, and this first line layer 143 has multiple electric contact mat 144.
Then, form the first insulating protective layer 15 on this layer reinforced structure 14, and form multiple projection underlying metal layer 151 on this first insulating protective layer 15 to be electrically connected those electric contact mats 144 respectively.
As shown in figure ip, the 3rd loading plate 16 with peel ply 161 is formed on this first insulating protective layer 15.
As referring to figure 1e, by the overall structure turned upside down of Fig. 1 D, and remove this second loading plate 13.
As shown in fig. 1f, in this packing colloid 12, form the through hole 121 of the accurate contraposition of multiple difference to the end 122 of those conductive blind holes 142 by laser, and those through holes 121 run through this packing colloid 12 to expose outside the end 122 of those conductive blind holes 142 respectively.
As shown in Figure 1 G, form crystal seed layer (seedlayer) 17 on passive 11b, the second surface 12b of this packing colloid 12 and the wall of those through holes 121 of this wafer 11, and form the second line layer 171 on this crystal seed layer 17 of part to be electrically connected the end 122 of those conductive blind holes 142.Afterwards, remove corresponding to the crystal seed layer 17 beyond this second line layer 171.
As shown in fig. 1h, form the second insulating protective layer 18 on passive 11b of this wafer 11 and the second surface 12b of this packing colloid 12, this second insulating protective layer 18 has multiple perforate 181 to expose outside this second line layer 171.Afterwards, form multiple soldered ball 19 on those projection underlying metal layer 151, form semiconductor package part 1 by this.
The shortcoming of above-mentioned prior art is: when wish forms the through hole 121 shown in Fig. 1 F, conductive blind hole 142 because of this layer reinforced structure 14 is hidden in below the first surface 12a of this packing colloid 12, make this laser cannot from the accurate contraposition of second surface 12b of this packing colloid 12 to the end 122 of those conductive blind holes 142, so that the through hole 121 that formed of this laser easily departs from the end 122 of those conductive blind holes 142 and contraposition on this dielectric layer 141, and easily cause the aperture 123 of those through holes 121 to be greater than the sectional area of the end 122 of those conductive blind holes 142, thus the dielectric layer 141 destroyed around those conductive blind holes 142.
Meanwhile, crystal seed layer in the through hole 121 of Fig. 1 G 17 is too little with the contact area of the end 122 of conductive blind hole 142, thus the second line layer 171 on this crystal seed layer 17 and the conductive capability between the end 122 of those conductive blind holes 142 not good.In addition, the 3rd loading plate 16 of Fig. 1 D need be set up on this first insulating protective layer 15, so that material cost and the processing procedure of the 3rd loading plate 16 need be increased, and the processing procedure of this semiconductor package part 1 too very complicated and be unfavorable for implementation.
Therefore, how to overcome the problem of above-mentioned prior art, become the problem of desiring most ardently solution at present in fact.
Summary of the invention
The invention provides a kind of semiconductor package part and method for making thereof, need not precisely contraposition, just layer reinforced structure can be electrically connected to conductive pole.
Semiconductor package part of the present invention comprises: packing colloid, and it has relative first surface and second surface; Semiconductor element, it to be embedded in this packing colloid and to have relative active surface and passive, and this active surface exposes to the first surface of this packing colloid; Multiple conductive pole, it is embedded in this packing colloid, and this conductive pole has relative first end and the second end to expose to first surface and the second surface of this packing colloid respectively; And layer reinforced structure, it is formed on the first surface of this packing colloid, and is electrically connected the first end of this semiconductor element and those conductive poles.
The present invention separately provides a kind of method for making of semiconductor package part, it comprises: embedded semi-conductor element and multiple conductive pole are in the packing colloid that has relative first surface and second surface, wherein, this semiconductor element has relative active surface and passive, and this active surface exposes to the first surface of this packing colloid, this conductive pole has relative first end and the second end, and makes the first end of those conductive poles expose to the first surface of this packing colloid; And form layer reinforced structure on the first surface of this packing colloid, and this layer reinforced structure is electrically connected the first end of this semiconductor element and those conductive poles.
Above-mentioned conductive pole can be cylinder, Elliptic Cylinder, square cylinder, polygon cylinder or spherical cylinder, and the material of this conductive pole can be the alloy of gold, silver, copper, tin, nickel or its combination in any.
The method for making of above-mentioned semiconductor package part can comprise: provide the first loading plate and be provided with this semiconductor element, and this active surface is towards this first loading plate; Arrange those conductive poles on this first loading plate, this first end is towards this first loading plate; Form this packing colloid to be embedded into this semiconductor element and those conductive poles in this packing colloid on this first loading plate, and expose outside the second end of those conductive poles from the second surface of this packing colloid; And remove this first loading plate, to expose outside the active surface of this semiconductor element and the first end of those conductive poles from the first surface of this packing colloid.
Above-mentioned first loading plate can have peel ply, and this semiconductor element, conductive pole and packing colloid are positioned on this peel ply.
The method for making of above-mentioned semiconductor package part can comprise: from this this packing colloid of second surface thinning and those conductive poles to expose outside passive of this semiconductor element.
The method for making of above-mentioned semiconductor package part can comprise: before removing this first loading plate, first arranges the second loading plate on the second surface of this packing colloid.
Above-mentioned semiconductor package part and method for making thereof can comprise: form first line layer on the second surface of this packing colloid to be electrically connected the second end of those conductive poles.
Above-mentioned semiconductor package part and method for making thereof can comprise: be embedded into those conductive poles in this packing colloid before, first form first line layer on the second surface of this packing colloid; Or, be embedded into those conductive poles in this packing colloid while, form first line layer in the lump on the second surface of this packing colloid.
Above-mentioned semiconductor package part and method for making thereof can comprise: form the first insulating protective layer with this first line layer coated on passive of this semiconductor element with the second surface of this packing colloid, this first insulating protective layer has this first line layer of exposed portion beyond multiple first perforate.
Above-mentioned layer reinforced structure can have at least one dielectric layer, is multiplely formed at conductive blind hole in this dielectric layer and is at least onely formed on this dielectric layer and is electrically connected the second line layer of those conductive blind holes, and this second line layer has multiple electric contact mat.
Above-mentioned semiconductor package part and method for making thereof can comprise: form the second insulating protective layer on this dielectric layer outermost and this second line layer, and this second insulating protective layer has multiple second perforate to expose outside the electric contact mat of this second line layer outermost.
Above-mentioned semiconductor package part can comprise multiple projection underlying metal layer and multiple soldered ball, and those projection underlying metal layer are formed on the electric contact mat that those second perforates expose respectively, and those soldered balls are formed on those projection underlying metal layer respectively.
The method for making of above-mentioned semiconductor package part can comprise: formed on electric contact mat that multiple projection underlying metal layer exposes in those second perforates; Carry out cutting single job; And form multiple soldered ball on those projection underlying metal layer.
As from the foregoing, in semiconductor package part of the present invention and method for making thereof, mainly embedded semi-conductor element and multiple conductive pole expose outside the end of those conductive poles in packing colloid, and be formed on this packing colloid by layer reinforced structure, then the conductive blind hole of this layer reinforced structure is electrically connected to the end of this semiconductor element and those conductive poles.
Therefore, the present invention without the need to forming the through hole of multiple accurate contraposition to the conductive blind hole of this layer reinforced structure with the laser of prior art in this packing colloid, and change the conductive pole conductive blind hole of this layer reinforced structure being electrically connected to this packing colloid and exposing, the through hole exempting prior art by this easily departs from the end of conductive blind hole and contraposition to dielectric layer so that impaired situation, also can save accurate for those through holes contraposition to the operation of those conductive blind holes and relevant tool (as laser aid).
In addition, the sectional area of conductive pole of the present invention can strengthen, and amasss without the need to the small cross sections being limited to those conductive blind holes, therefore can increase the end of those conductive poles and the contact area of those conductive blind holes and the conductive capability strengthened each other.
In addition, the present invention, without the need to arranging the 3rd loading plate of prior art to reduce material and to reduce costs, also can simplify the processing procedure of the semiconductor package part of prior art and be beneficial to implementation.
Accompanying drawing explanation
Figure 1A to Fig. 1 H illustrates the semiconductor package part of prior art and the cross-sectional schematic of method for making thereof;
Fig. 2 A to Fig. 2 F is the cross-sectional schematic illustrating semiconductor package part of the present invention and method for making thereof, and wherein, Fig. 2 A' and Fig. 2 B' is another embodiment of Fig. 2 A and Fig. 2 B; And
Fig. 3 A to Fig. 3 C is the cross-sectional schematic of the method for making illustrating Fig. 2 A.
Symbol description
1,2 semiconductor package parts
10,20 first loading plates
11 wafers
11a, 21a active surface
Passive of 11b, 21b
111,211 weld pads
12,23 packing colloids
12a, 23a first surface
12b, 23b second surface
121,231 through holes
122 ends
123 apertures
13,26 second loading plates
14,27 layer reinforced structures
141,271 dielectric layers
142,272 conductive blind holes
143,24 first line layers
144,274 electric contact mats
15,25 first insulating protective layers
151,282 projection underlying metal layer
16 the 3rd loading plates
161,201 peel plies
17 crystal seed layers
171,273 second line layers
18,28 second insulating protective layers
181 perforates
19,29 soldered balls
21 semiconductor elements
22 conductive poles
22a first end
22b the second end
251 first perforates
281 second perforates
H1, H2 height
SS line of cut.
Embodiment
By particular specific embodiment, embodiments of the present invention are described below, those skilled in the art can understand other advantages of the present invention and effect easily by content disclosed in the present specification.
Notice, structure, ratio, size etc. that this specification institute accompanying drawings illustrates, content all only for coordinating specification to disclose, for understanding and the reading of those skilled in the art, be not intended to limit the enforceable qualifications of the present invention, therefore the not technical essential meaning of tool, the adjustment of the modification of any structure, the change of proportionate relationship or size, do not affecting under effect that the present invention can produce and the object that can reach, still all should drop on disclosed technology contents and obtain in the scope that can contain.
Simultaneously, quote in this specification as " on ", " one ", " first ", " second ", " surface ", " active surface ", " passive face ", the term such as " end ", also only for ease of understanding of describing, but not for limiting the enforceable scope of the present invention, the change of its relativeness or adjustment, under changing technology contents without essence, when being also considered as the enforceable category of the present invention.
Fig. 2 A to Fig. 2 F is the cross-sectional schematic illustrating semiconductor package part 2 of the present invention and method for making thereof, and wherein, Fig. 2 A' and Fig. 2 B' is another embodiment of Fig. 2 A and Fig. 2 B.
As shown in Figure 2 A, one first loading plate 20 arranges the semiconductor element 21 (as wafer) and conductive pole 22 with height H 1, and formed there is relative first surface 23a and second surface 23b packing colloid 23 on this first loading plate 20, to be embedded into this semiconductor element 21 and those conductive poles 22 in this packing colloid 23.
In the present embodiment, the processing procedure of the structure shown in Fig. 2 A can with reference to figure 3A to Fig. 3 C.
As shown in Figure 3A, the first loading plate 20 and the semiconductor element 21 (as wafer) with height H 1 are first provided, and this semiconductor element 21 is arranged on this first loading plate 20.This semiconductor element 21 has multiple weld pad 211, relative active surface 21a and passive 21b, and those weld pads 211 and this active surface 21a are towards this first loading plate 20.
In the present embodiment, this first loading plate 20 also can have peel ply 201, and this semiconductor element 21 is positioned on this peel ply 201, and this peel ply 201 can be release film or adhesion coating etc.
As shown in Figure 3 B, multiple conductive pole 22 with height H 2 is provided, and those conductive poles 22 are arranged on the peel ply 201 of this first loading plate 20.This conductive pole 22 has relative first end 22a and the second end 22b, and this first end 22a is towards this first loading plate 20.
This conductive pole 22 can be cylinder, Elliptic Cylinder, square cylinder, polygon cylinder or spherical cylinder etc., and the material of this conductive pole 22 can be the alloy etc. of gold, silver, copper, tin, nickel or its combination in any.In the present embodiment, the height H 2 of this conductive pole 22 higher than the height H 1 of this semiconductor element 21, but not as limit.
As shown in Figure 3 C, formation has the packing colloid 23 of relative first surface 23a and second surface 23b on the peel ply 201 of this first loading plate 20, to be embedded into this semiconductor element 21 and those conductive poles 22 in this packing colloid 23, and expose outside the second end 22b of those conductive poles 22 from the second surface 23b of this packing colloid 23, and the active surface 21b homonymy of the first surface 23a of this packing colloid 23 and this semiconductor element 21.This packing colloid 23 can have the height H 2 being same as this conductive pole 22, but not as limit.
Afterwards, carry out the processing procedure of thinning thickness (highly), this packing colloid 23 of part and those conductive poles 22 are removed in the lump from this second surface 23b, use this packing colloid of thinning 23 and height H 2 to the height H1 of those conductive poles 22 and expose outside passive 21b of this semiconductor element 21, passive the 21b in this semiconductor element 21 is flushed, as shown in Figure 2 A with the second end 22b of the second surface 23b with those conductive poles 22 that make this packing colloid 23.
In other embodiments, in the processing procedure of above-mentioned Fig. 3 B to Fig. 3 C, also directly can adopt semiconductor element 21, conductive pole 22 and the packing colloid 23 as shown in Figure 2 A with identical height H 1, thus omit this thinning processing procedure.
As shown in Figure 2 B, first line layer 24 is formed on the second surface 23b of this packing colloid 23 to be electrically connected the second end 22b of those conductive poles 22.
Then; form the first insulating protective layer 25 with this first line layer 24 coated on passive 21b of this semiconductor element 21 and the second surface 23b of this packing colloid 23, this first insulating protective layer 25 has this first line layer 24 of exposed portion beyond multiple first perforate 251.
In addition, as shown in Fig. 2 A' and Fig. 2 B', for another embodiment of Fig. 2 A and Fig. 2 B, and be with the Main Differences of Fig. 2 A and Fig. 2 B: can be embedded into those conductive poles 22 in this packing colloid 23 before, first form first line layer 24 on the second surface 23b of this packing colloid 23.
As shown in Figure 2 C, continue above-mentioned Fig. 2 B, and arrange the second loading plate 26 on this first insulating protective layer 25.Then, by the overall structure turned upside down of Fig. 2 C, and by this peel ply 201 of removal to remove this first loading plate 20, thus expose outside the active surface 21a of this semiconductor element 21 and first end 22a of those conductive poles 22 from the first surface 23a of this packing colloid 23.
Fig. 2 C also can continue above-mentioned Fig. 2 B', and after removing this first loading plate 20, form the multiple first surface 23a of this packing colloid 23 and through hole 231 of second surface 23b of running through to expose outside this first line layer 24 of part respectively, recharge electric conducting material (as copper material or tin material) to form multiple conductive pole 22 with first end 22a and the second end 22b in those through holes 231, and those conductive poles 22 are electrically connected the first line layer 24 that those through holes 231 expose respectively.
In addition, in other embodiments, the present invention also can be embedded into those conductive poles 22 in this packing colloid 23 while, form this first line layer 24 in the lump on the second surface 23b of this packing colloid 23.
As shown in Figure 2 D, form layer reinforced structure 27 on the active surface 21a of this semiconductor element 21 and the first surface 23a of this packing colloid 23, and be electrically connected the weld pad 211 of this layer reinforced structure 27 to this semiconductor element 21 and the first end 22a of those conductive poles 22.
This layer reinforced structure 27 can be fan-out structure, and there is at least one dielectric layer 271, be multiplely formed at conductive blind hole 272 in this dielectric layer 271 and be at least onely formed on this dielectric layer 271 and be electrically connected the second line layer 273 of those conductive blind holes 272, conductive blind hole 272 in this dielectric layer 271 of innermost layer is electrically connected the weld pad 211 of this semiconductor element 21 and the first end 22a of those conductive poles 22, and this second line layer 273 has multiple electric contact mat 274.In the present embodiment, this layer reinforced structure 27 is made up of the conductive blind hole 272 of dielectric layer 271, three layers of three layers and second line layer 273 of three layers, but not as limit.
Then, form the second insulating protective layer 28 in this dielectric layer 271 outermost with on this second line layer 273, this second insulating protective layer 28 has multiple second perforate 281 to expose outside the electric contact mat 274 of this second line layer 273 outermost.
As shown in Figure 2 E, remove this second loading plate 26 to expose outside the first line layer 24 of this first insulating protective layer 25 and those the first perforates 251, and formed on electric contact mat 274 that multiple projection underlying metal layer 282 exposes in those second perforates 281.
As shown in Figure 2 F, the multiple line of cut SS according to Fig. 2 E cut list (singulation) operation to its overall structure, and form multiple soldered ball 29 on those projection underlying metal layer 282, form multiple semiconductor package part 2 by this.
The present invention separately provides a kind of semiconductor package part 2, and as shown in Figure 2 F, it comprises packing colloid 23, semiconductor element 21, multiple conductive pole 22 and layer reinforced structure 27.
This packing colloid 23 has relative first surface 23a and second surface 23b.This semiconductor element 21 (as wafer) is embedded in this packing colloid 23, and has multiple weld pad 211, relative active surface 21a and passive 21b, the first surface 23a homonymy of this active surface 21a and this packing colloid 23.
Those conductive poles 22 are embedded in this packing colloid 23, and this conductive pole 22 has relative first end 22a and the second end 22b to expose to first surface 23a and the second surface 23b of this packing colloid 23 respectively.Meanwhile, this conductive pole 22 is cylinder, Elliptic Cylinder, square cylinder, polygon cylinder or spherical cylinder etc., and the material of this conductive pole 22 is the alloy etc. of gold, silver, copper, tin, nickel or its combination in any.
This layer reinforced structure 27 can be fan-out structure, and it is formed on the active surface 21a of this semiconductor element 21 and first surface 23a of this packing colloid 23, and is electrically connected the weld pad 211 of this semiconductor element 212 and the first end 22a of those conductive poles 22.
This semiconductor package part 2 can comprise first line layer 24, to be electrically connected the second end 22b of those conductive poles 22 on its second surface 23b being formed at this packing colloid 23.
This semiconductor package part 2 can comprise the first insulating protective layer 25; it is formed at this first line layer 24 coated on passive 21b of this semiconductor element 21 and second surface 23b of this packing colloid 23, and this first insulating protective layer 25 has this first line layer 24 of exposed portion beyond multiple first perforate 251.
This layer reinforced structure 27 can have at least one dielectric layer 271, is multiplely formed at conductive blind hole 272 in this dielectric layer 271 and is at least onely formed on this dielectric layer 271 and is electrically connected the second line layer 273 of those conductive blind holes 272, conductive blind hole 272 in this dielectric layer 271 of innermost layer is electrically connected the weld pad 211 of this semiconductor element 21 and the first end 22a of those conductive poles 22, and this second line layer 273 has multiple electric contact mat 274.In the present embodiment, this layer reinforced structure 27 is made up of the conductive blind hole 272 of dielectric layer 271, three layers of three layers and second line layer 273 of three layers, but not as limit.
This semiconductor package part 2 can comprise the second insulating protective layer 28; it is formed at this dielectric layer 271 outermost with on this second line layer 273, and this second insulating protective layer 28 has multiple second perforate 281 to expose outside the electric contact mat 274 of this second line layer 273 outermost.
This semiconductor package part 2 can comprise multiple projection underlying metal layer 282 and multiple soldered ball 29, those projection underlying metal layer 282 are formed on the electric contact mat 274 that those second perforates 281 expose respectively, and those soldered balls 29 are formed on those projection underlying metal layer 282 respectively.
As from the foregoing, in semiconductor package part of the present invention and method for making thereof, mainly embedded semi-conductor element and multiple conductive pole expose outside the end of those conductive poles in packing colloid, and be formed on this packing colloid by layer reinforced structure, then the conductive blind hole of this layer reinforced structure is electrically connected to the end of this semiconductor element and those conductive poles.
Therefore, the present invention without the need to forming the through hole of multiple accurate contraposition to the conductive blind hole of this layer reinforced structure with the laser of prior art in this packing colloid, and change the conductive pole conductive blind hole of this layer reinforced structure being electrically connected to this packing colloid and exposing, the through hole exempting prior art by this easily departs from the end of conductive blind hole and contraposition to dielectric layer so that impaired situation, also can save accurate for those through holes contraposition to the operation of those conductive blind holes and relevant tool (as laser aid).
In addition, the sectional area of conductive pole of the present invention can strengthen, and amasss without the need to the small cross sections being limited to those conductive blind holes, therefore can increase the end of those conductive poles and the contact area of those conductive blind holes and the conductive capability strengthened each other.
In addition, the present invention, without the need to arranging the 3rd loading plate of prior art to reduce material and to reduce costs, also can simplify the processing procedure of the semiconductor package part of prior art and be beneficial to implementation.
Above-described embodiment only for illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can modify to above-described embodiment.Therefore, the scope of the present invention, should listed by claims.
Claims (21)
1. a semiconductor package part, it comprises:
Packing colloid, it has relative first surface and second surface;
Semiconductor element, it to be embedded in this packing colloid and to have relative active surface and passive, and this active surface exposes to the first surface of this packing colloid;
Multiple conductive pole, it is embedded in this packing colloid, and this conductive pole has relative first end and the second end to expose to first surface and the second surface of this packing colloid respectively; And
Layer reinforced structure, it is formed on the first surface of this packing colloid, and is electrically connected the first end of this semiconductor element and those conductive poles.
2. semiconductor package part as claimed in claim 1, it is characterized by, this conductive pole is cylinder, Elliptic Cylinder, square cylinder, polygon cylinder or spherical cylinder.
3. semiconductor package part as claimed in claim 1, it is characterized by, the material of this conductive pole is the alloy of gold, silver, copper, tin, nickel or its combination in any.
4. semiconductor package part as claimed in claim 1, it is characterized by, this semiconductor package part also comprises first line layer, to be electrically connected the second end of those conductive poles on its second surface being formed at this packing colloid.
5. semiconductor package part as claimed in claim 1; it is characterized by; this semiconductor package part also comprises the first insulating protective layer; its be formed at passive of this semiconductor element with the second surface of this packing colloid on this first line layer coated, and this first insulating protective layer has this first line layer of exposed portion beyond multiple first perforate.
6. semiconductor package part as claimed in claim 1, it is characterized by, this layer reinforced structure has at least one dielectric layer, is multiplely formed at conductive blind hole in this dielectric layer and is at least onely formed on this dielectric layer and is electrically connected the second line layer of those conductive blind holes, and this second line layer has multiple electric contact mat.
7. semiconductor package part as claimed in claim 6; it is characterized by; this semiconductor package part also comprises the second insulating protective layer; it is formed on this dielectric layer outermost and this second line layer, and this second insulating protective layer has multiple second perforate to expose outside the electric contact mat of this second line layer outermost.
8. semiconductor package part as claimed in claim 7, it is characterized by, this semiconductor package part also comprises multiple projection underlying metal layer and multiple soldered ball, those projection underlying metal layer are formed on the electric contact mat that those second perforates expose respectively, and those soldered balls are formed on those projection underlying metal layer respectively.
9. a method for making for semiconductor package part, it comprises:
Embedded semi-conductor element and multiple conductive pole are in the packing colloid that has relative first surface and second surface, wherein, this semiconductor element has relative active surface and passive, and this active surface exposes to the first surface of this packing colloid, this conductive pole has relative first end and the second end, and makes the first end of those conductive poles expose to the first surface of this packing colloid; And
Form layer reinforced structure on the first surface of this packing colloid, and this layer reinforced structure is electrically connected the first end of this semiconductor element and those conductive poles.
10. the method for making of semiconductor package part as claimed in claim 9, it is characterized by, this conductive pole is cylinder, Elliptic Cylinder, square cylinder, polygon cylinder or spherical cylinder.
The method for making of 11. semiconductor package parts as claimed in claim 9, it is characterized by, the processing procedure formed before this layer reinforced structure also comprises:
There is provided the first loading plate and be provided with this semiconductor element, this active surface is towards this first loading plate;
Arrange those conductive poles on this first loading plate, this first end is towards this first loading plate;
Form this packing colloid to be embedded into this semiconductor element and those conductive poles in this packing colloid on this first loading plate, and expose outside the second end of those conductive poles from the second surface of this packing colloid; And
Remove this first loading plate, to expose outside the active surface of this semiconductor element and the first end of those conductive poles from the first surface of this packing colloid.
The method for making of 12. semiconductor package parts as claimed in claim 11, it is characterized by, this first loading plate has peel ply, and this semiconductor element, conductive pole and packing colloid are positioned on this peel ply.
The method for making of 13. semiconductor package parts as claimed in claim 11, is characterized by, and this method for making also comprises from this this packing colloid of second surface thinning and those conductive poles to expose outside passive of this semiconductor element.
The method for making of 14. semiconductor package parts as claimed in claim 11, is characterized by, and before removing this first loading plate, first arranges the second loading plate on the second surface of this packing colloid.
The method for making of 15. semiconductor package parts as claimed in claim 9, is characterized by, and this method for making also comprises formation first line layer on the second surface of this packing colloid to be electrically connected the second end of those conductive poles.
The method for making of 16. semiconductor package parts as claimed in claim 9, is characterized by, this method for making be also included in be embedded into those conductive poles in this packing colloid before, first form first line layer on the second surface of this packing colloid.
The method for making of 17. semiconductor package parts as claimed in claim 9, is characterized by, this method for making be also included in be embedded into those conductive poles in this packing colloid while, form first line layer in the lump on the second surface of this packing colloid.
The method for making of 18. semiconductor package parts as described in claim 15,16 or 17; it is characterized by; this method for making also comprises formation first insulating protective layer with this first line layer coated on passive of this semiconductor element with the second surface of this packing colloid, and this first insulating protective layer has this first line layer of exposed portion beyond multiple first perforate.
The method for making of 19. semiconductor package parts as claimed in claim 9, it is characterized by, this layer reinforced structure has at least one dielectric layer, is multiplely formed at conductive blind hole in this dielectric layer and is at least onely formed on this dielectric layer and is electrically connected the second line layer of those conductive blind holes, and this second line layer has multiple electric contact mat.
The method for making of 20. semiconductor package parts as claimed in claim 19; it is characterized by; this method for making also comprises formation second insulating protective layer on this dielectric layer outermost and this second line layer, and this second insulating protective layer has multiple second perforate to expose outside the electric contact mat of this second line layer outermost.
The method for making of 21. semiconductor package parts as claimed in claim 20, it is characterized by, this method for making also comprises:
Formed on electric contact mat that multiple projection underlying metal layer exposes in those second perforates;
Carry out cutting single job; And
Form multiple soldered ball on those projection underlying metal layer.
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| Application Number | Priority Date | Filing Date | Title |
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| TW103131509 | 2014-09-12 | ||
| TW103131509A TWI596715B (en) | 2014-09-12 | 2014-09-12 | Semiconductor package and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109003946A (en) * | 2017-06-06 | 2018-12-14 | 力成科技股份有限公司 | Encapsulating structure and its manufacturing method |
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| US10872879B2 (en) | 2015-11-12 | 2020-12-22 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor package and manufacturing method thereof |
| TWI624020B (en) * | 2016-09-29 | 2018-05-11 | 矽品精密工業股份有限公司 | Electronic package and method for fabricating the same |
| TWI839179B (en) * | 2018-01-15 | 2024-04-11 | 美商艾馬克科技公司 | Semiconductor package and manufacturing method thereof |
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| TWI389220B (en) * | 2007-10-22 | 2013-03-11 | 矽品精密工業股份有限公司 | Semiconductor package and method for fabricating the same |
| TWI405361B (en) * | 2008-12-31 | 2013-08-11 | Ind Tech Res Inst | Thermoelectric device and process thereof and stacked structure of chips and chip package structure |
| TWI495051B (en) * | 2011-07-08 | 2015-08-01 | Unimicron Technology Corp | Coreless package substrate and fabrication method thereof |
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| US20080211083A1 (en) * | 2007-03-02 | 2008-09-04 | Samsung Electro-Mechanics Co., Ltd. | Electronic package and manufacturing method thereof |
| US8097490B1 (en) * | 2010-08-27 | 2012-01-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die |
| CN103066064A (en) * | 2011-10-24 | 2013-04-24 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
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| CN109003946B (en) * | 2017-06-06 | 2020-12-15 | 力成科技股份有限公司 | Package structure and method for manufacturing the same |
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| Publication number | Publication date |
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| TWI596715B (en) | 2017-08-21 |
| TW201611203A (en) | 2016-03-16 |
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