CN211529945U - System-in-package integrating multiple chips and elements - Google Patents

System-in-package integrating multiple chips and elements Download PDF

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Publication number
CN211529945U
CN211529945U CN202020411949.1U CN202020411949U CN211529945U CN 211529945 U CN211529945 U CN 211529945U CN 202020411949 U CN202020411949 U CN 202020411949U CN 211529945 U CN211529945 U CN 211529945U
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layer
chip
molding compound
package
wiring layer
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CN202020411949.1U
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Chinese (zh)
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沈志文
李宗铭
徐伟峰
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Shenzhen Jiemicrochip Technology Co ltd
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Shenzhen Jiemicrochip Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model discloses a system level package of integrated a plurality of chips and component belongs to the semiconductor technology field, including first chip package body, molding compound layer and wiring layer, molding compound layer top surface is equipped with first chip package body, molding compound layer bottom surface is equipped with the wiring layer, molding compound layer is equipped with a plurality of wire through-hole, molding compound layer passes through wire through-hole and first chip package body, wiring layer electric signal connection, still includes the electromagnetic shield layer, electromagnetic shield layer parcel first chip package body, molding compound layer and wiring layer. The utility model discloses an inlay the first chip and the passive component of a plurality of permutation and combination at first chip package body, improve the diversification and the density of chip package, set up the first chip package body of electromagnetic shield layer parcel, mould compound layer and wiring layer and play shielding electromagnetic interference, ensure chip signal of telecommunication's reliability.

Description

System-in-package integrating multiple chips and elements
Technical Field
The utility model belongs to the technical field of the semiconductor, especially, relate to a system in package of integrated a plurality of chips and component.
Background
With the continuous improvement of technical research and development, more and more intelligent electronic products have built-in semiconductor chips, for example, built-in semiconductor chips such as computers, mobile phones, digital cameras and intelligent wearing, and the current semiconductor chips still have the following defects:
1. the product is miniaturized, the packaging area of the chip is reduced, more chips are difficult to arrange, and the function is not strong due to low packaging density;
2. the chip packaging structure is single, and the functional requirements of different products cannot be met;
3. the electronic components in the product have electromagnetic interference, which easily affects the electrical signal transmission performance of the packaged chip.
SUMMERY OF THE UTILITY MODEL
The utility model provides a system in package of integrated a plurality of chips and component aims at solving current chip packaging density and hangs down, single structure, and has electromagnetic interference, is difficult to satisfy the functional demand of different products.
In order to achieve the above object, the utility model provides a following technical scheme:
the utility model provides a system level package of integrated a plurality of chips and component, includes first chip package body, molding compound layer and wiring layer, molding compound layer top surface is equipped with first chip package body, molding compound layer bottom surface is equipped with wiring layer, molding compound layer is equipped with a plurality of wire through-hole, molding compound layer passes through wire through-hole and first chip package body, wiring layer electric signal connection, still includes the electromagnetic shield layer, electromagnetic shield layer parcel first chip package body, molding compound layer and wiring layer.
Preferably, first chip package body includes plastic envelope layer, first dielectric layer, first chip group, passive component, metal lead and joint pad, be equipped with first chip group on the first dielectric layer, first chip group one side is equipped with 1 at least passive component, first dielectric layer be equipped with a plurality of with the wire through-hole corresponds the electrically conductive post of connecting, the terminal surface is equipped with the joint pad respectively about electrically conductive post, first chip group passes through metal lead and joint pad bonded connection, be equipped with the plastic envelope layer on the first dielectric layer, first chip group, passive component, metal lead and joint pad of plastic envelope layer cladding.
Preferably, the first chip group includes at least 2 first chips, an active surface of the first chip located at the bottom layer is exposed on a bottom surface of the plastic encapsulation layer, and the arrangement of the first chip groups includes side-by-side arrangement and/or stacking arrangement.
Preferably, the stacking arrangement of the first chip groups includes an oblique stepped stacking arrangement, a horizontal staggered stacking arrangement, and a pyramid stacking arrangement.
Preferably, at least 1 second chip is plastically encapsulated in the molding compound layer, the upper end face and the lower end face of each second chip are provided with second dielectric layers, conductive interconnections are arranged in the second dielectric layers positioned on the lower end faces, and the second chips are electrically connected with the wiring layers through the conductive interconnections.
Preferably, a redistribution line is arranged in the wiring layer, a welding zone is arranged on the bottom surface of the wiring layer, and a welding ball connected with the redistribution line is arranged on the welding zone.
Preferably, the wiring layer is at least 1 layer.
Preferably, the material of the molding compound layer is epoxy molding compound.
Compared with the prior art, the utility model following beneficial effect has:
the utility model provides a system level package of integrated a plurality of chips and component, through embedding a plurality of permutation and combination's first chip and passive component at first chip package body, improve chip package's diversification and density, set up first chip package body of electromagnetic shield layer parcel, molding compound layer and wiring layer, play shielding electromagnetic interference, ensure chip electrical signal transmission's reliability.
To illustrate the structural features and functions of the present invention more clearly, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
Drawings
Fig. 1 is a schematic view of a system-in-package structure integrating a plurality of chips and components according to the present invention;
fig. 2 is a schematic structural diagram of a system-in-package integrating a plurality of chips and elements according to the present invention;
fig. 3 is a schematic diagram of a chip arrangement structure of a system-in-package integrating a plurality of chips and components according to the present invention;
reference numerals: 1. a first chip package; 101. a plastic packaging layer; 102. a first dielectric layer; 103. a first chipset; 1031. a first chip; 104. a passive element; 105. a metal lead; 106. a bonding pad; 107. a conductive post; 2. a molding compound layer; 201. a second chip; 202. a second dielectric layer; 203. A conductive interconnect; 3. a wiring layer; 301. a redistribution line; 302. welding the ball; 4. a wire through hole; 5. And an electromagnetic shielding layer.
Detailed Description
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "including" and "having," and any variations thereof, in the description and claims of this application and the description of the above figures are intended to cover non-exclusive inclusions. The terms "first," "second," and the like in the description and claims of this application or in the above-described drawings are used for distinguishing between different objects and not for describing a particular order.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The embodiment of the utility model provides a system in package of integrated a plurality of chips and component, it is shown with reference to fig. 1-2, including first chip package body 1, molding compound layer 2 and wiring layer 3, 2 top surfaces of molding compound layer are equipped with first chip package body 1, 2 bottom surfaces of molding compound layer are equipped with wiring layer 3, molding compound layer 2 is equipped with a plurality of wire through-hole 4, molding compound layer 2 passes through wire through-hole 4 and first chip package body 1, wiring layer 3 electric signal connection, still includes electromagnetic shield layer 5, electromagnetic shield layer 5 parcel first chip package body 1, molding compound layer 2 and wiring layer 3.
The System-In-Package is abbreviated as SIP, and the english is System In a Package, which is to assemble a plurality of chips with different functions and passive components together, In this embodiment, a plurality of first chips 1031 and passive components 104 are integrated In a first chip Package 1, and a second chip 201 is further disposed In a molding compound layer 2, so as to form a multifunctional Package to improve the number and density of chip packages, and meet the functional requirements of more products, thereby enhancing the practicability of the chips.
The first chip package body 1 includes a plastic package layer 101, a first dielectric layer 102, a first chip set 103, a passive element 104, a metal lead 105 and a bonding pad 106, the first chip set 103 is disposed on the first dielectric layer 102, at least 1 passive element 104 is disposed on one side of the first chip set 103, the first dielectric layer 102 is disposed with a plurality of conductive posts 107 correspondingly connected to the wire through holes 4, the upper and lower end surfaces of the conductive posts 107 are respectively disposed with the bonding pad 106, the first chip set 103 is bonded and connected to the bonding pad 106 through the metal lead 105, the plastic package layer 101 is disposed on the first dielectric layer 102, and the plastic package layer 101 covers the first chip set 103, the passive element 104, the metal lead 105 and the bonding pad 106.
In the first chip package body 1 in this embodiment, a first chip group 103 and at least 1 passive element 104 are mounted on a first dielectric layer 102, the first dielectric layer 102 is provided with a plurality of conductive pillars 107, the upper and lower end surfaces of the conductive pillars 107 are respectively provided with bonding pads 106, the first chip group 103 and the bonding pads 106 are bonded and connected through metal leads 105, then plastic packaging is cured to obtain a plastic package layer 101 disposed on the upper end surface of the first dielectric layer 102, and the plastic package layer 101 wraps the first chip group 103, the passive element 104, the metal leads 105 and the bonding pads 106.
It should be noted that the first chip 1031 (or the second chip 201) in the present invention includes, but is not limited to, a functional chip of a processor and a memory, and a high frequency chip (e.g., an RF radio frequency chip, a GPS positioning chip, a DRAM memory chip, a WiFi chip, or a bluetooth chip). The first chip set 103 may be a plurality of same or different chips arranged according to a predetermined arrangement, so as to meet the functional requirements of more products, for example, the chips are used in personal computers, mobile phones, digital cameras and other electronic devices, based on uniform distribution and improvement of the functional density of the chips per unit area.
The passive element 104, i.e., a passive electronic element, is an electronic element that can exhibit its characteristics without an external power source. Such as resistors, capacitors, inductors, optics, baluns, filters, etc.
Further, the first chip group 103 includes at least 2 first chips 1031, the active surface of the first chip 1031 located at the bottom layer is exposed on the bottom surface of the molding layer 101, and the arrangement of the first chip group 103 includes a side-by-side arrangement and/or a stacking arrangement.
In this embodiment, the first chip group 103 may adopt a side-by-side arrangement or a stacked arrangement, or a combination of side-by-side arrangement and stacked arrangement, and the connection manner of the first chip 1031 in the package adopts a wire bonding connection, that is, the first chip 1031 and the bonding pad 106 are connected by the metal lead 105.
The parallel arrangement refers to the arrangement and installation of single bare chip, and the connection mode of the bare chip adopts wire bonding connection.
The stacking arrangement means that a plurality of bare chip chips are stacked together according to a preset arrangement rule to form a chip function requirement with more complete performance, more chip functions are integrated on a tiny fixed area, the function density of the chip is improved, or the area is reduced under the function density of the same chip, so that the packaged chip is more miniaturized, and the requirement of more tiny products is met.
Further, referring to fig. 3, the stacking arrangement of the first chip set 103 includes an oblique stepped stacking arrangement, a horizontal staggered stacking arrangement, and a pyramid stacking arrangement.
In one embodiment, the three-dimensional stacking arrangement of the first chip set 103 includes an oblique stepped stacking arrangement, a horizontal staggered stacking arrangement, and a pyramidal stacking arrangement.
The oblique step stacking arrangement, as shown in fig. 3(a), arranges the first chips 1031 of the same size at an angle (e.g., 45 degrees) to form a step stacking arrangement for better integration of the chip packaging space.
The first chips 1031 of the same size are arranged in a horizontally staggered and stacked arrangement, as shown in fig. 3(B), and are staggered in the opposite direction by a certain distance (for example, 1mm) to form a stacked arrangement having a staggered arrangement, so as to better integrate a chip packaging space.
In the pyramid-shaped stacked arrangement, referring to fig. 3(C), the first chips 1031 with different sizes or functions are stacked layer by layer from larger to smaller to form a pyramid-shaped arrangement, so as to better integrate the packaging space of the first chips 1031, for example, the processor chip is disposed at the bottom layer, the memory card chip is stacked at the middle layer, and the WiFi chip is disposed at the top layer.
It should be noted that the oblique step stacking arrangement, the horizontal staggered stacking arrangement, and the pyramid stacking arrangement include, but are not limited to, the size and the functional arrangement of the first chip 1031, and may also be according to the shape, the structure, and other elements of the first chip 1031.
Furthermore, at least 1 second chip 201 is encapsulated in the molding compound layer 2, a second dielectric layer 202 is disposed on the upper and lower end surfaces of the second chip 201, a conductive interconnection 203 is disposed in the second dielectric layer 202 on the lower end surface, and the second chip 201 is electrically connected to the wiring layer 3 through the conductive interconnection 203.
In this embodiment, a molding compound layer 2 is disposed under a first chip package 1, at least 1 second chip 201 is embedded in the molding compound layer 2, wherein a second dielectric layer 202 is coated on the upper and lower end surfaces of the second chip 201, and a conductive interconnection 203 for electrically connecting the second chip 201 is disposed in the second dielectric layer 202. The first chip package 1 and the molding compound layer 2 are connected by soldering, and a gap is formed between the first chip package and the molding compound layer, which is beneficial to improving the packaging density and dissipating heat.
Furthermore, redistribution lines 301 are arranged in the wiring layer 3, a welding zone is arranged on the bottom surface of the wiring layer 3, welding balls 302 connected with the redistribution lines 301 are arranged on the welding zone, and the wiring layer 3 is at least 1 layer.
In this embodiment, a wiring layer 3 is disposed on the lower end surface of the molding compound layer 2, the wiring layer 3 includes a plurality of redistribution lines 301, a bonding area and a non-bonding area are disposed on the bottom surface of the wiring layer 3, the non-bonding area is insulated and isolated, a bonding ball 302 is soldered to the bonding area and electrically connected to the redistribution lines 301, and the bonding ball 302 is used for mounting a connection inserted into a certain circuit board. The wiring layer 3 is at least 1 layer, preferably 3 layers in the embodiment, and the redistribution lines 301 between each layer are connected up and down.
Further, the chip packaging structure further comprises an electromagnetic shielding layer 5, and the electromagnetic shielding layer 5 covers the first chip package body 1, the molding compound layer 2 and the wiring layer 3.
In order to ensure the reliability of the operation of the chip monomer in the product and avoid the electromagnetic interference of signals of other elements of the product to the chip package, an electromagnetic shielding layer 5 is provided, the electromagnetic shielding layer 5 covers the first chip package body 1, the molding compound layer 2 and the wiring layer 3, and the electromagnetic shielding layer 5 is a conductive silicone material with electromagnetic shielding performance, such as Uninwell BQ-6111 conductive adhesive.
The technical principle of the present invention has been described above with reference to specific embodiments, which are merely preferred embodiments of the present invention. The utility model discloses a scope of protection not only limits in above-mentioned embodiment, and the all belongings the utility model discloses a technical scheme under the thinking all belongs to the utility model discloses a scope of protection. Those skilled in the art will appreciate that other embodiments of the invention can be devised which do not require inventive effort and which fall within the scope of the present invention.

Claims (8)

1. The utility model provides a system level package of integrated a plurality of chips and component which characterized in that, includes first chip package body, molding compound layer and wiring layer, molding compound layer top surface is equipped with first chip package body, molding compound layer bottom surface is equipped with wiring layer, molding compound layer is equipped with a plurality of wire through-hole, molding compound layer passes through wire through-hole and first chip package body, wiring layer electric signal connection, still includes the electromagnetic shield layer, the electromagnetic shield layer parcel first chip package body, molding compound layer and wiring layer.
2. The system-in-package integrating a plurality of chips and elements according to claim 1, wherein the first chip package body comprises a plastic package layer, a first dielectric layer, a first chip group, passive elements, metal leads and bonding pads, the first chip group is disposed on the first dielectric layer, at least 1 passive element is disposed on one side of the first chip group, the first dielectric layer is provided with a plurality of conductive pillars correspondingly connected to the conductive wire through holes, the bonding pads are disposed on the upper and lower end surfaces of the conductive pillars, the first chip group is bonded to the bonding pads through the metal leads, the plastic package layer is disposed on the first dielectric layer, and the plastic package layer covers the first chip group, the passive elements, the metal leads and the bonding pads.
3. The system-in-package according to claim 2, wherein the first chip group comprises at least 2 first chips, an active surface of the first chip at the bottom layer is exposed on a bottom surface of the molding layer, and an arrangement of the first chip groups comprises a side-by-side arrangement and/or a stacked arrangement.
4. The system-in-package for integrating multiple chips and components according to claim 3, wherein the stacking arrangement of the first chip groups comprises a slant step stacking arrangement, a horizontal staggered stacking arrangement and a pyramid stacking arrangement.
5. The system-in-package for integrating multiple chips and devices as claimed in claim 1, wherein at least 1 second chip is encapsulated in the molding compound layer, the second chip has a second dielectric layer on the top and bottom surfaces, and the second dielectric layer on the bottom surface has conductive interconnects, and the second chip is electrically connected to the wiring layer through the conductive interconnects.
6. The system-in-package for integrating multiple chips and components as claimed in claim 1, wherein a redistribution line is formed in the wiring layer, a bonding pad is formed on a bottom surface of the wiring layer, and a bonding ball connected to the redistribution line is formed on the bonding pad.
7. The system-in-package integrating multiple chips and components according to claim 6, wherein the wiring layer is at least 1 layer.
8. The system-in-package integrating multiple chips and components according to claim 1, wherein the molding compound layer is an epoxy molding compound.
CN202020411949.1U 2020-03-27 2020-03-27 System-in-package integrating multiple chips and elements Active CN211529945U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202020411949.1U CN211529945U (en) 2020-03-27 2020-03-27 System-in-package integrating multiple chips and elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202020411949.1U CN211529945U (en) 2020-03-27 2020-03-27 System-in-package integrating multiple chips and elements

Publications (1)

Publication Number Publication Date
CN211529945U true CN211529945U (en) 2020-09-18

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Country Status (1)

Country Link
CN (1) CN211529945U (en)

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