CN211529933U - SIP packaging assembly and chip thereof - Google Patents

SIP packaging assembly and chip thereof Download PDF

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Publication number
CN211529933U
CN211529933U CN202020412131.1U CN202020412131U CN211529933U CN 211529933 U CN211529933 U CN 211529933U CN 202020412131 U CN202020412131 U CN 202020412131U CN 211529933 U CN211529933 U CN 211529933U
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CN
China
Prior art keywords
chip
layer
chips
sip
wiring layer
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Active
Application number
CN202020412131.1U
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Chinese (zh)
Inventor
沈志文
李宗铭
徐伟峰
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Shenzhen Jiemicrochip Technology Co ltd
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Shenzhen Jiemicrochip Technology Co ltd
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Priority to CN202020412131.1U priority Critical patent/CN211529933U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Semiconductor Integrated Circuits (AREA)

Abstract

The utility model discloses a SIP encapsulation subassembly and chip thereof belongs to semiconductor package technical field, including chipset, passive component, plastic envelope layer, wiring layer, dielectric layer, metal convex block and welding ball, the plastic envelope layer cladding has chipset and passive component, an active surface of chipset exposes in a plastic envelope layer side, the chipset includes 2 at least chips, the chip is through arranging the built-up connection in order to optimize chip package density; a wiring layer coated with a dielectric layer is arranged on one side face of the plastic packaging layer, a conductive through hole is formed in the dielectric layer, a metal bump is arranged on the conductive through hole and electrically connected with the chip, a welding area is arranged on one side of the wiring layer, and the wiring layer is electrically connected with the conductive through hole and the welding area. The utility model discloses a with the permutation and combination of a plurality of chips with different demand modes encapsulation formation SIP chip, further improve the functional density that the chip was arranged to satisfy the demand of small product to the chip volume.

Description

SIP packaging assembly and chip thereof
Technical Field
The utility model belongs to the technical field of the semiconductor package, especially, relate to a SIP encapsulation subassembly and chip thereof.
Background
With the continuous progress of social informatization, semiconductors are widely used in various electronic products such as personal computers, mobile phones, digital cameras, and other electronic devices. The current electronic industry has higher and higher requirements on the integration level of products, the chip package with a single structure function cannot meet the requirements of tiny electronic products, and the combination package of multiple functional chips is integrated on a smaller area, which means that the requirements on the function density of the chips are improved, and thus, more challenges are brought to the electronic packaging technology.
SUMMERY OF THE UTILITY MODEL
The utility model provides a SIP encapsulation subassembly and chip thereof aims at solving the chip package of simplex structure, forms diversified chip packaging structure to satisfy the structure demand of different electronic product.
In order to achieve the above object, the utility model provides a following technical scheme:
an SIP packaging assembly comprises a chip set, a passive element, a plastic packaging layer, a wiring layer, a dielectric layer, a metal bump and a welding ball, wherein the plastic packaging layer is coated with the chip set and the passive element, one active surface of the chip set is exposed out of one side surface of the plastic packaging layer, the chip set comprises at least 2 chips, and the chips are connected in a permutation and combination mode to optimize the packaging density of the chips; the chip packaging structure comprises a plastic packaging layer, a chip, a wiring layer, a dielectric layer, a metal bump, a chip, a bonding pad and a bonding ball, wherein the plastic packaging layer is arranged on one side face of the plastic packaging layer, the dielectric layer is arranged between the wiring layer and the plastic packaging layer, the dielectric layer is provided with the conductive through hole, the metal bump is arranged on the conductive through hole and is electrically connected with the chip, the wiring layer is electrically connected with the conductive through hole, the bonding pad.
Preferably, the arrangement of the chips includes planar side-by-side arrangement and/or stereoscopic superposition arrangement, the planar side-by-side arrangement and the stereoscopic superposition arrangement of the chips are connected by wire bonding, and the wire bonding connects the metal bump and the chip through a metal lead.
Preferably, the three-dimensional stacking arrangement of the chips includes an oblique stepped stacking arrangement, a horizontal staggered stacking arrangement and a pyramid stacking arrangement.
Preferably, the planar side-by-side arrangement of the chips may further adopt flip-chip bonding connection, where the flip-chip bonding connection is electrically connecting the active surface of the chip and the wiring layer.
Preferably, the wiring layer is at least 1 layer.
A SIP chip comprising a package of the SIP package as described in any of the above.
Preferably, the SIP chip is a packaged computing chip, and a plurality of computing chips having the same structure are disposed on the same computing board.
Compared with the prior art, the utility model following beneficial effect has:
the utility model provides a SIP encapsulation subassembly and chip thereof encapsulates through the permutation and combination with a plurality of chips with different demand modes, forms multi-functional SIP chip, further improves the functional density that the chip was arranged in less area to satisfy the demand of small product to the chip volume.
To illustrate the structural features and functions of the present invention more clearly, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
Drawings
Fig. 1 is a schematic diagram of the overall structure of the SIP package assembly of the present invention;
fig. 2 is a schematic diagram of a single structure of the SIP package assembly of the present invention;
fig. 3 is a schematic diagram of a chip arrangement structure of the SIP package assembly of the present invention;
fig. 4 is a schematic diagram of a flip chip bonding structure of the SIP package assembly of the present invention;
fig. 5 is a schematic diagram of an SIP chip of the present invention;
reference numerals: 1. a chipset; 101. a chip; 2. a passive element; 3. a plastic packaging layer; 4. a wiring layer; 5. a dielectric layer; 6. a metal bump; 7. welding the ball; 8. a conductive via; 9. a metal lead; 10. an arithmetic chip; 11. and (4) calculating strength.
Detailed Description
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "including" and "having," and any variations thereof, in the description and claims of this application and the description of the above figures are intended to cover non-exclusive inclusions. The terms "first," "second," and the like in the description and claims of this application or in the above-described drawings are used for distinguishing between different objects and not for describing a particular order.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The embodiment of the utility model provides a SIP encapsulation subassembly, it is shown with reference to fig. 1-2, a SIP encapsulation subassembly, including chipset 1, passive component 2, plastic envelope layer 3, wiring layer 4, dielectric layer 5, metal lug 6 and welding ball 7, plastic envelope layer 3 cladding has chipset 1 and passive component 2, an active surface of chipset 1 exposes in 3 sides of plastic envelope layer, chipset 1 includes 2 at least chips 101, chip 101 is through arranging the built-up connection in order to optimize chip 101 packing density; a wiring layer 4 is arranged on one side face of the plastic package layer 3, a dielectric layer 5 is arranged between the wiring layer 4 and the plastic package layer 3, the dielectric layer 5 is provided with a conductive through hole 8, a metal bump 6 is arranged on the conductive through hole 8, the metal bump 6 is electrically connected with the chip 101, the wiring layer 4 is electrically connected with the conductive through hole 8, a welding area is arranged on one side of the wiring layer 4, and a welding ball 7 connected with the wiring layer 4 is arranged on the welding area.
In this embodiment, the SIP chinese is a System In Package (System In a Package), and a plurality of chips 101 having different functions and the passive element 2 are assembled together to implement a single standard Package having a certain function.
The chip 101 in the present embodiment includes, but is not limited to, a processor, a functional chip of a memory, and a high frequency chip (e.g., an RF radio frequency chip, a GPS positioning chip, a DRAM memory chip, a WiFi chip, a bluetooth chip, or the like). The chip set 1 may be a plurality of identical or different chips 101 arranged according to a predetermined arrangement, so as to meet the requirements of different tiny products, such as personal computers, mobile phones, digital cameras and other electronic devices, based on uniform distribution and improvement of chip function density per unit area.
The passive element 2, i.e., the passive electronic element, is an electronic element that can exhibit its characteristics without an external power source. Such as resistors, capacitors, inductors, optics, baluns, filters, etc.
Specifically, a carrier plate coated with bonding glue is obtained, a chip 101 and a passive element 2 which are preset are installed on the carrier plate for glue pouring and plastic packaging, the carrier plate and the bonding glue are removed after cooling and solidification, the chip 101 and the passive element 2 are wrapped in a plastic packaging layer 3, wherein an active surface of the chip 101 located at the bottom is exposed on one side of the plastic packaging layer 3, a plurality of chips 101 are combined and packaged to form a chip group 1, functional chips 101 and passive elements 2 required by an electronic product are installed on a certain area (such as the size of the carrier plate) as far as possible, and the packaging density of the chip 101 is optimized through arrangement, combination and connection so as to improve the performance structure of the packaged chip. More specifically, a wiring layer 4 is further arranged on one side of the plastic package layer 3, the wiring layer 4 is at least 1 layer, a dielectric layer 5 is arranged between the wiring layer 4 and the plastic package layer 3, the dielectric layer 5 is provided with a conductive through hole 8 electrically connected with the wiring layer 4, and a solder ball 7 connected with the wiring layer 4 is further arranged on one side of the wiring layer 4, so that a packaged chip single body is formed.
It should be noted that, in the process of mounting the chip 101 and the passive component 2, the metal bump 6 is also mounted, the metal bump 6 is preset at the upper end of the conductive via 8 and electrically connected to the conductive via 8, and the chip 101 is connected to the metal bump 6 through the metal lead 9 to realize electrical signal connection.
Further, the arrangement of the chips 101 includes a plane side-by-side arrangement and/or a three-dimensional stacking arrangement, the plane side-by-side arrangement and the three-dimensional stacking arrangement of the chips 101 are connected by wire bonding, and the wire bonding connects the metal bump 6 with the chip 101 through a metal lead 9.
In this embodiment, based on the SIP chip 101 package design, the chips 101 may be arranged side by side in a plane or stacked in a three-dimensional manner, or both in a parallel manner, and the connection manner of the chips 101 in the package is wire bonding connection, that is, the chips 101 are connected to the metal bumps 6 through the metal leads 9.
The plane parallel arrangement refers to the installation and installation of a single bare chip 101, and the connection mode of the bare chips 101 adopts wire bonding connection or flip chip bonding connection, wherein, referring to fig. 4, the flip chip bonding connection electrically connects the active surface of the chip 101 with the wiring layer 4 through the conductive through hole 8.
The three-dimensional stacking arrangement means that a plurality of bare chip chips 101 are stacked together according to a preset arrangement rule to form a chip function requirement with more complete performance, more chip functions are integrated on a tiny fixed area, the function density of the chips is improved, or the area is reduced under the function density of the same chip 101, so that the packaged chips are more miniaturized, and the requirements of more tiny products are met.
In one embodiment, referring to fig. 3, the three-dimensional stacking arrangement of the chips 101 includes an oblique step stacking arrangement, a horizontal staggered stacking arrangement, and a pyramid stacking arrangement.
The oblique step stacking arrangement, as shown in fig. 3(a), arranges the chips 101 with the same size at a certain angle (for example, 45 degrees) to form a step stacking arrangement, so as to better integrate the chip packaging space.
The chips 101 of the same size are arranged in a horizontally staggered and overlapped manner, and as shown in fig. 3(B), the chips 101 are arranged in a horizontally staggered and overlapped manner by a certain distance (for example, 1mm) in a reverse direction, so that the chip packaging space can be better integrated.
Pyramid-shaped stacking arrangement, referring to fig. 3(C), chips 101 with different sizes or functions are stacked one on another from larger to smaller to form a pyramid-shaped arrangement, so as to better integrate the packaging space of the chips 101, for example, a processor chip is disposed at the bottom layer, a memory card chip is stacked at the middle layer, and a WiFi chip is disposed at the top layer.
The oblique step stacking arrangement, the horizontal staggered stacking arrangement, and the pyramid stacking arrangement include, but are not limited to, the chip 101 with its size and function, and may also be based on the shape and structure of the chip 101 and other chip 101 elements.
In addition, referring to fig. 5, to achieve the above object, the present invention further provides a SIP chip, wherein the SIP chip comprises a package of the SIP package assembly as described above.
The type of the chip 101 is not limited in this embodiment. For example, the packaged chip 101 may be an arithmetic chip 10, and a plurality of arithmetic chips 10 having the same structure may be provided on the same force plate 11.
It should be understood that, for a conventional computer, only one computing processor chip, such as a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU), is disposed on a Printed Circuit Board (PCB). For a product using the computing chip 10, a plurality of computing chips 10 (referred to as computing processor chips) with the same structure are often densely disposed on a computing board 11 (PCB). In addition, at least two of the operation chips 10 are connected in series to each other among the operation chips 10.
The technical principle of the present invention has been described above with reference to specific embodiments, which are merely preferred embodiments of the present invention. The utility model discloses a scope of protection not only limits in above-mentioned embodiment, and the all belongings the utility model discloses a technical scheme under the thinking all belongs to the utility model discloses a scope of protection. Those skilled in the art will appreciate that other embodiments of the invention can be devised which do not require inventive effort and which fall within the scope of the present invention.

Claims (7)

1. An SIP packaging assembly is characterized by comprising a chip set, a passive element, a plastic packaging layer, a wiring layer, a dielectric layer, a metal bump and a welding ball, wherein the plastic packaging layer is coated with the chip set and the passive element, one active surface of the chip set is exposed out of one side surface of the plastic packaging layer, the chip set comprises at least 2 chips, and the chips are connected in a permutation and combination manner to optimize the packaging density of the chips; the chip packaging structure comprises a plastic packaging layer, a chip, a wiring layer, a dielectric layer, a metal bump, a chip, a bonding pad and a bonding ball, wherein the plastic packaging layer is arranged on one side face of the plastic packaging layer, the dielectric layer is arranged between the wiring layer and the plastic packaging layer, the dielectric layer is provided with the conductive through hole, the metal bump is arranged on the conductive through hole and is electrically connected with the chip, the wiring layer is electrically connected with the conductive through hole, the bonding pad.
2. The SIP package assembly of claim 1, wherein the arrangement of the chips comprises a planar side-by-side arrangement and/or a three-dimensional stacked arrangement, the planar side-by-side arrangement and the three-dimensional stacked arrangement of the chips are connected by wire bonds, and the wire bonds connect the metal bumps with the chips through a metal lead.
3. The SIP package of claim 2, wherein the three-dimensional stacked arrangement of chips comprises a slanted step stacked arrangement, a horizontal staggered stacked arrangement, and a pyramidal stacked arrangement.
4. The SIP package assembly of claim 2, wherein the planar side-by-side arrangement of the chips further employs a flip-chip bonding connection, the flip-chip bonding connection electrically connecting the active surface of the chip with the wiring layer.
5. The SIP package assembly of claim 1, wherein the routing layer is at least 1 layer.
6. An SIP chip, characterized in that the SIP chip comprises a package of SIP packages according to any of claims 1-5.
7. The SIP chip of claim 6, wherein the SIP chip is a packaged computing chip, and a plurality of computing chips having the same structure are disposed on the same computing board.
CN202020412131.1U 2020-03-27 2020-03-27 SIP packaging assembly and chip thereof Active CN211529933U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202020412131.1U CN211529933U (en) 2020-03-27 2020-03-27 SIP packaging assembly and chip thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202020412131.1U CN211529933U (en) 2020-03-27 2020-03-27 SIP packaging assembly and chip thereof

Publications (1)

Publication Number Publication Date
CN211529933U true CN211529933U (en) 2020-09-18

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202020412131.1U Active CN211529933U (en) 2020-03-27 2020-03-27 SIP packaging assembly and chip thereof

Country Status (1)

Country Link
CN (1) CN211529933U (en)

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