CN113169153A

CN113169153A - Packaging structure of chip

Info

Publication number: CN113169153A
Application number: CN201880099876.2A
Authority: CN
Inventors: 符会利; 郭茂; 张晓东
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-12-26
Filing date: 2018-12-26
Publication date: 2021-07-23
Anticipated expiration: 2038-12-26
Also published as: WO2020132909A1; CN113169153B

Abstract

A package structure includes a wiring board (22), and two chips (10, 20) attached to upper and lower surfaces of the wiring board (22). Since the upper and lower chips (10, 20) are directly attached to the wiring board (22), the thickness of the chips is reduced.

Description

Packaging structure of chip

Technical Field

The invention relates to the technical field of semiconductors, in particular to a chip packaging structure.

Background

Chips, have been stock devices in electronic devices. By integrating functional circuits required in the operation of the electronic equipment into a small chip, on one hand, functional devices of the electronic equipment can be modularized, so that the design and manufacturing cost of the electronic equipment is reduced; on the other hand, by integrating a large number of circuits in a chip, the size of the electronic device can be reduced, and the electronic device has great significance particularly for electronic devices in the consumer field (such as mobile phones).

Smartphones are currently the most popular consumer electronics devices. As a media terminal device for consumers, whether the smart phone is convenient to carry and operate is an important index for measuring the quality of the smart phone. In order to easily put the smart phone into a trouser pocket or allow a consumer to operate with one hand, the plane area of the smart phone cannot be too large, and the reduction of the plane area of the smart phone can be realized by reducing the plane area occupied by the chip.

In order to reduce the planar area occupied by the chip, there is a packaging technology called POP (Package on Package) in the chip field. POP packages are commonly used for the packaging of smart phone chips. In a smart phone, it is generally necessary to equip various types of chips such as a processor chip, a memory chip, and the like. POP packaging proposes that packages of various types of chips are stacked up and down to form a new chip entity. For example, the package structure shown in fig. 1 includes a memory chip package and a processor chip package. The memory chip package is disposed above the processor chip package. The memory chip 2 is fixed on the substrate 6. The processor Chip 1, also called System On Chip (SOC), is fixed on a substrate 7. Metal wiring is provided in the substrate 6 and the substrate 7, and the memory chip 2 and the processor chip 1 are communicatively connected to the respective substrates through a wire Bonding (wire Bonding) or a Pad (Pad) provided at the bottom thereof. A rewiring layer 3 is also provided between the processor chip 1 and the memory chip 2. Pads (not shown) are arranged on the upper surface and the lower surface of the redistribution layer 3, and metal wiring is arranged inside the redistribution layer 3. The substrate 6 is connected to the redistribution layer 3 through solder balls 8, and the redistribution layer 3 is connected to the substrate 7 through solder balls 4. In the POP package structure shown in fig. 1, when the processor chip 1 is to read data from the memory chip 2, the read data is transferred into the processor chip 1 through the substrate 6, the solder balls 8, the redistribution layer 3, the solder balls 4, and the substrate 7 in this order.

The POP package is not only used for the combination of the processor chip and the memory chip, and various chips in the electronic device can be stacked and sealed into one chip entity in the way of the POP package. The POP package is used to reduce the occupation of the chip on the plane space of the electronic device by using the space in the thickness direction. In the field of smart phones, one of the most intuitive results of using POP packages is that the planar size of a smart phone becomes small, and even a high-performance smart phone loaded with a plurality of functional chips becomes capable of being handled with one hand.

However, the POP package has a significant disadvantage in that it may increase the thickness of the electronic device. In the field of smart phones, the increase in thickness can affect aesthetics, which is also very detrimental to sales. Therefore, how to further reduce the thickness of POP packages is also a focus of attention in the industry.

Disclosure of Invention

In order to solve the problems in the prior art, an embodiment of the present invention provides a package structure. In the packaging structure, at least two chips are stacked and packaged together. The packaging structure comprises a first chip and a second chip. The second chip is disposed on the top of a second wiring board, and the corresponding first chip is fixed on the bottom of the second wiring board. In the package structure provided by the embodiment of the invention, the first chip is directly fixed at the bottom of the wiring board of the second chip, and the solder balls are additionally arranged between the first chip and the second chip, so that the space of the package structure in the thickness direction is saved.

In an alternative embodiment, the first chip may be fixed to the bottom of the second wiring board by a die bonding film.

In an alternative embodiment, the package structure further includes a first wiring board. The first chip is provided on the first wiring board. The first wiring board and the second wiring board are respectively provided with metal wiring, and the surfaces of the first wiring board and the second wiring board are provided with interfaces communicated with the metal wiring inside the first wiring board and the second wiring board respectively, so that the metal wiring is electrically connected with the first chip or the second chip or other circuit devices.

The interface between the surfaces of the first wiring board and the second wiring board may take various forms, such as a pad, and a length of metal wiring exposed to the surfaces of the first wiring board and the second wiring board.

In alternative embodiments, the first chip may be electrically connected to the interface on the surface of the first wiring board in various ways. For example, the first chip may be electrically connected to the pads on the top surface of the first wiring board by wire Bonding (Wired Bonding); for another example, the first chip may be in direct contact with the metal wiring exposed on the top surface of the first wiring board through the pad on the bottom. Similarly to the manner of electrical connection of the first chip and the first wiring board, the second chip can also be electrically connected to the metal wiring in the second wiring board by various methods.

In an alternative embodiment, an interconnection structure may be provided between the first wiring board and the second wiring board for communicating metal wirings in the first wiring board and the second wiring board. The interconnection structure may be a metal pillar disposed between the first wiring board and the second wiring board; alternatively, the first wiring board and the second wiring board may be metal-plated through holes penetrating through a plastic sealing material between the first wiring board and the second wiring board. Correspondingly, the top of the first wiring board and the bottom of the second wiring board are provided with interfaces corresponding to the interconnection structures. The interface can be a pad or a metal wiring exposed on the surface and is communicated with the interconnection structure through soldering tin or a direct contact mode.

From the perspective of process cost, the processing cost of adopting the metal column as the interconnection structure is lower.

Since the first chip is attached to the bottom surface of the second wiring board, the arrangement of the interconnection structure needs to avoid the first chip. Then, if the interconnection structure is realized by metal pillars, the metal pillars are arranged in a ring around the first chip. The stability of the packaging structure can be increased by the arrangement, so that the stress distribution in the thickness direction of the packaging structure is more uniform, and cracking is avoided. The ring shape is not limited to a circular ring, and may be various shapes such as a triangular ring, a rectangular ring, etc., and may even be an irregular shape surrounding the first chip. In a preferred embodiment, the ring shape may be a regular pattern centered on the first chip.

In the package structure provided in the embodiment of the present invention, the second chip and the first chip are stacked one on another. The second chip located above the first chip needs to perform signal intercommunication with the first chip, and needs to perform signal intercommunication with the outside of the package structure. Therefore, the metal posts for communicating the first wiring board and the second wiring board can be classified into two types: a first metal pillar and a second metal pillar. Correspondingly, the metal wiring in the first wiring board is also classified into three types: a first metal wiring, a second metal wiring, and a third metal wiring. The second metal wiring is connected with the second metal column and is also communicated with the chip, and the second metal wiring and the second metal column form a part of a signal path between the first chip and the second chip; a third metal wiring is connected with the first metal column, the third metal wiring is also connected with a pad at the bottom of the first wiring board, and the third metal wiring and the first metal column form a part of a signal path of the second chip communicated with the outside of the packaging structure; the first metal wiring is not connected to the metal posts, and the first metal wiring is used for connecting the first chip and the bonding pads at the bottom of the first wiring board, so that the first metal wiring forms a part of a signal path of the first chip communicating with the outside of the package structure.

In an electronic device, the package structure provided in the embodiment of the present invention is used as a chip entity obtained after packaging, and is mounted on a carrier of the electronic device. The carrier board is typically a printed circuit board. When the packaging structure is installed in an electronic device, the connecting pads at the bottom of the first wiring board are fixedly connected with the circuit devices on the carrier board through the solder balls.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of a POP package in the prior art;

FIG. 2 is a schematic diagram of a package structure according to an embodiment of the invention;

FIG. 3 is a schematic diagram of a package structure according to another embodiment of the invention;

FIGS. 4 a-4 g are process flow diagrams of a package structure according to an embodiment of the invention;

fig. 5 is a schematic view of an electronic device loaded with a package structure of an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiment of the invention provides a packaging structure. In the package structure, two or more chips are packaged together. And, these chips adopt a top-to-bottom packaging mode, that is, at least one chip is packaged above another chip.

In the embodiments of the present invention, description about "top" and "bottom" is referred to. It should be noted that the top and bottom are determined according to the position of the chip in the package structure.

In the embodiment of the present invention, the chip refers to an entity obtained by packaging a Die (Die).

Referring to fig. 2, a package structure provided by the embodiment of the invention includes a first chip 10 and a second chip 20. The first chip 10 is provided on the first wiring board 12. The second chip 20 is provided on the second wiring board 22. The second wiring board 22 is disposed on top of the first chip 10. Thus, the first chip 10, the second chip 20, the first wiring board 12, and the second wiring board 22 constitute a structure stacked up and down.

The first wiring board 12 and the second wiring board 22 may have a multilayer structure mainly composed of an insulating medium. Conductive sheets made of a metal material are provided on the surfaces of the first wiring board 12 and the second wiring board 22, or on one or more layers. Perforations (Via) are provided between different layers of the first wiring board 12 and the second wiring board 22, and these perforations penetrate through different layers, even surfaces, of the first wiring board 12 and the second wiring board 22. The through holes are filled or coated with metal. The metal in the through-hole is in communication with the conductive sheet on the layer. In the embodiments of the present invention, the metal in the via and the conductive sheet on the layer are collectively referred to as a metal wiring. The metal wiring constitutes a signal path within the first wiring board 12 and the second wiring board 22.

The metal posts, the metal sheets, the conductive sheets, and the metal wirings according to the embodiments of the present invention may be made of various metals such as copper.

From the perspective of process implementation, the first wiring board 12 and the second wiring board 22 may be substrates (substrates) or heavy wiring boards (RDLs). The substrate and the rewiring board are both of a multilayer structure, but in comparison, the substrate contains glass fibers, and the line width and the line distance of metal wiring therein are more than 10um (including horizontal distance and vertical distance); the heavy wiring board is not provided with glass fiber, and the line width and the line distance of metal wiring in the heavy wiring board can be 5 um. Therefore, if the thickness of the entire chip is reduced, the first wiring board 12 and the second wiring board 22 can be selected as the heavy wiring boards at the same time.

However, from the viewpoint of industrial cost, the chip-stacked package structure is generally used in the field of mobile phone chips. In the mobile phone chip, the second chip 20 located above is usually a memory chip, and for a mobile phone chip manufacturer, the situation that the memory chip is purchased from a third party generally exists, and the purchased memory chip and the substrate are usually packaged into a Package entity, which is also referred to as a qualified device Package (KGP) in the industry. Since a substrate is already provided for the memory chip in the KGP and pads are reserved at the bottom of the substrate to serve as signal interfaces, if the package is removed at this time and the substrate is replaced with a heavy wiring board, a large amount of additional cost is incurred. Therefore, from the viewpoint of cost saving, the second wiring board 22 may be a substrate, and the first wiring board 12 is a heavy wiring board. Of course, in the future, facing various requirements in semiconductor processes, various combinations of processes may be used for the first wiring board 12 and the second wiring board 22, for example, even a semiconductor substrate (Interposer) may be considered, and these should not be construed as limitations on the practice of the present invention.

With continued reference to fig. 2, the first chip 10 and the second chip 20 are coupled with metal wirings in the first wiring board 12 and the second wiring board 22, respectively, through pads (pads) 14 and 24 at respective bottoms. A metal post 25 is also disposed between the first wiring board 12 and the second wiring board 22. Both ends of the metal post 25 are coupled to signal paths in the first wiring board 12 and the second wiring board 22, respectively.

The bottom of the first wiring board 12 is provided with a plurality of pads 125, and the pads 125 are used as external interfaces of the package structure provided by the embodiment of the invention. Specifically, when the package structure provided by the embodiment of the invention is installed in an electronic device, the pads 125 are fixedly connected to a PCB (Printed Circuit Board) of the electronic device through solder balls.

Alternatively, in the embodiment of the present invention, the metal wirings in the first wiring board 12 include the first metal wiring 122, the second metal wiring 124, and the third metal wiring 126. The metal pillar 25 includes a first metal pillar 252 and a second metal pillar 254. The first metal wiring 122 connects the pad 14 at the bottom of the first chip 10 and the pad 125 at the bottom of the first wiring board 125, so as to implement signal communication between the first chip 10 and a circuit outside the package structure provided by the embodiment of the invention. The second metal wire 124 is connected to the second metal pillar 254 and the pad 14 at the bottom of the first chip 10, so as to implement signal communication between the first chip 10 and the second chip 10. The third metal wiring 126 is connected to the first metal pillar 252 and the pad on the bottom of the first wiring board 12, so as to implement signal communication between the second chip 20 and the circuit outside the package structure.

In an alternative embodiment, metal studs 25 are arranged in a ring around first chip 10, with first metal stud 252 and second metal stud 254 on different rings. In alternative embodiments, the metal posts 25 may be arranged in a circular ring, a rectangular ring, or even in an irregular pattern. In the embodiment of the present invention, the first chip 10 is attached to the bottom of the second wiring board 22, so the pad or pin arrangement at the bottom of the second wiring board 22 must reserve a space for the first chip 10, and the metal posts 25 corresponding to the pads or pins at the bottom of the second wiring board 22 also need to be arranged around the first chip 10. Of course, the second metal posts 254, which need to communicate with the first chip 10 due to the need to take into account the space for arrangement of the metal wirings in the first wiring board 12, can be arranged closer to the first chip than the first metal posts 252, which need only communicate with the pads at the bottom of the first wiring board 12. For example, in an alternative embodiment, the first metal pillars 252 and the second metal pillars 254 are arranged in two rings with different sizes, and the first metal pillars 252 are arranged in a ring shape surrounding the ring shape formed by the first chip 10 and the second metal pillars 254.

In the package structure of fig. 2, the first chip 10 and the second chip 20 are both coupled to metal wirings in the wiring board through pads disposed on the bottom. In alternative embodiments the chip may be coupled to metal wiring on the wiring board by top or side jumpers (Wired Bonding). Specifically, as shown in fig. 3, the top of the second chip 20 is provided with a pad 24, and the pad 24 is connected with a jumper 23. The jumper 23 is connected to the first metal post 252 or the second metal post 254 by metal wiring on the second wiring board 22.

Generally, the second chip 20 is connected to the metal wiring in the second wiring board 22 by means of jumper wires, which increases the space requirement above the second chip 20, i.e., increases the chip thickness. However, as mentioned above, the second chip 20 may be purchased KGP. If the purchased KGP is connected by a jumper, and if the KGP is disassembled, the method for connecting the second chip to the second wiring board 22 is changed, which causes additional process and design costs, so that the method for connecting the chip in the KGP may not be changed.

In the package structure of fig. 2 and 3 provided by the embodiment of the present invention, the first chip 10 is directly attached to the bottom of the second wiring board 20, and no additional solder ball is disposed between the first chip 10 and the second chip 20, or an additional wiring board is mounted, which reduces the thickness of the whole package structure regardless of the chip connection manner in KGP.

Alternatively, the first chip 10 may be fixed to the bottom of the second wiring board 20 by adhesive. The adhesive may be a Die Attach Film (DAF) that is commonly used to secure a Die in a chip.

In the package structure provided in fig. 2 and 3, the first wiring board 12 and the second wiring board 22 are communicated with each other through the metal posts 25. In an actual product, the space between the first wiring board 12 and the second wiring board 22 may be filled with an insulating medium (such as silicon dioxide or the like). In this regard, in an alternative embodiment, instead of the metal posts 25, through holes (Via) communicating the first wiring board 12 and the second wiring board 22 may be formed in the insulating medium, and the signal path between the first wiring board 12 and the second wiring board 22 may be constituted by plating or filling metal in the through holes. However, the metal column is simpler in process and low in cost. In particular, refer to fig. 4a to 4h, which illustrate a method for forming a package structure according to an embodiment of the present invention.

The packaging method provided by the embodiment of the invention comprises the following steps:

referring to fig. 4a, the KGP is fixed on the carrier 30 by an adhesive.

The KGP is a purchased package entity including the second chip 20 and the second wiring board 22. The second chip 20 and the second wiring board 22 are filled with a plastic molding material. The KGP is turned over with the top of the KGP in contact with the surface of the carrier board and the side of the second wiring board 22 facing up.

Step b, referring to fig. 4b, the first chip 10 is fixed on the second wiring board 22.

The top of the first chip 10 is bonded to the second wiring board 22 by an adhesive such as DAF. The bottom of the first chip 10, i.e. the side with the pads 14, faces upward or away from the second chip 20.

Step c, referring to fig. 4c, manufacturing a metal column array;

the metal pillar array includes a substrate 29 and a plurality of metal pillars protruding from one side of the substrate. The metal array can be formed integrally from the same metal, such as copper. The metal pillar array can be prepared by various methods, but if cost is considered, it can be considered to use the existing equipment and process in the packaging factory, for example, the metal pillar can be etched on a whole metal plate by etching process. It will be readily appreciated that the metal pillar array may be prefabricated or purchased from a third party and need not be fabricated at the present time.

Step d: referring to fig. 4d, a metal pillar array is fastened on the KGP.

The metal array is snapped onto the KGP with the metal studs 25 encircling the first chip in the center and the base 29 bridging over the first chip 10. So that the metal posts 25 are aligned with the metal wirings exposed to the surface of the second wiring board 22. Specifically, the surface of the second wiring board 22 may also be formed with a metal structure similar to a pad, and the coupling metal posts 25 and the metal wiring may be fixed by solder balls. In the embodiment of the present invention, the metal posts 25 are formed on both sides of the first chip 10. In an actual product, however, the plurality of metal studs 25 may be arranged in a ring shape to surround the first chip 10 at the center.

Step e: referring to fig. 4e, plastic packaging is performed.

And filling the gap between the metal column array and the first chip 10 with a plastic package material 35.

Step f: referring to fig. 4f, the structure shown in fig. 4e is polished to expose the pads on the bottom of the first chip 10.

In the embodiment of the invention, the substrate 29 of the metal pillar array, the molding compound between the substrate 29 and the first chip 10, and the metal pillars 25 higher than the bottom surface of the first chip 10 are polished off until the pads 14 at the bottom of the first chip 10 are exposed.

Step g: referring to fig. 4g, the first wiring board 12 is prepared.

The second wiring board 12 generally includes metal wiring, and an insulating material (for example) that wraps the metal wiring. Therefore, the insulating material can be generated on the surface of the first chip 10 and the surface of the plastic package material wrapping the first chip 10 layer by coating or growing. The metal wiring is arranged on one or more layers of the insulating material, and a plurality of interlayer perforations of the insulating material are perforated, and the perforations are filled with or coated with metal to form metal wiring for connecting different layers.

As can be seen from the above-mentioned packaging method, each metal pillar 25 is integrally formed, and the front body thereof is a pre-formed metal pillar array, and the metal pillars can be simply fixed in the packaging structure by grinding process, and communicate and support the two chips. Compared with a signal circuit which generates metal by an electrochemical method, the process cost is lower, and the structure is more stable.

In the embodiment of the invention, the whole packaging structure is equivalently divided into two layers: the first layer includes the first chip and a first wiring board; the second layer includes the second chip and a second wiring board. In the above description, the first layer including a first chip and the second layer including a second chip are only described as examples. In an actual product, the first layer may further include a plurality of first chips, and the plurality of first chips may be disposed in parallel on the first wiring board, or may be stacked such that one or more first chips are stacked on another or more first chips. The plurality of first chips may be directly communicated with each other or communicated through the first wiring board. Similarly, the second layer may include a plurality of second chips, and the plurality of second chips may be disposed in parallel on the second wiring board or may be stacked. The second chips can be directly communicated with each other or communicated with each other through the second wiring board.

Fig. 5 is a schematic view illustrating a package structure mounted on a carrier board in an electronic device according to an embodiment of the invention. As shown, the pads 125 on the bottom of the first wiring board 12 are fixedly connected to the carrier board of the electronic device by solder balls, and communicate data with other chips or devices on the carrier board through the circuits on the carrier board. The carrier is most commonly a Printed Circuit Board (Printed Circuit Board).

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

A package structure includes a first chip, a second chip and a second wiring board, the second chip being disposed on the second wiring board, the first chip being attached to a bottom of the second wiring board.
The package structure of claim 1,

further comprising a first wiring board disposed below the second wiring board, the first chip being disposed on the first wiring board,

metal wirings are provided in both the first wiring board and the second wiring board,

the first chip communicates with metal wiring in the first wiring board, and the second chip communicates with metal wiring in the second wiring board.
The package structure according to claim 2, further comprising a metal post having both ends connected to the second wiring board and the first wiring board, respectively, the both ends of the metal post communicating with metal wirings in the first wiring board and the second wiring board, respectively.
The package structure according to claim 3, wherein a pad communicating with a metal wiring in the second wiring board is provided at a bottom of the second wiring board, and the metal post is fixedly connected to the pad of the second wiring board.
The package structure of claim 4, wherein the metal posts are fixedly connected to the pads of the second wiring board by solder.
The package structure according to any one of claims 3 to 5, wherein a part of the metal wiring in the first wiring board is exposed to a surface of the first wiring board, and the metal pillar is in contact with the metal wiring exposed to the surface of the first wiring board.
The package structure of claim 3, wherein the metal pillars are arranged in a ring around the first chip.
The package structure according to claim 3, wherein a first metal wiring, a second metal wiring, and a third metal wiring are included in the first wiring board, a pad is provided at a bottom of the first wiring board, the metal pillar includes a first metal pillar and a second metal pillar, the first metal wiring communicates with the first chip and the pad at the bottom of the first wiring board, the second metal wiring communicates with the second metal pillar and the first chip, and the third metal wiring communicates with the first metal pillar and the pad at the bottom of the first wiring board.
The package structure of claim 8, wherein the first metal pillar and the second metal pillar are arranged in two rings of different sizes around the first chip, respectively, and the ring of the first metal pillar is arranged to surround the ring of the first metal pillar.
The package structure according to claim 2, wherein an interconnection structure is provided between the second wiring board and the first wiring board, the interconnection structure communicating the second wiring board and the first wiring board.
The package structure according to claim 1, wherein the first chip is fixed to a bottom of the second wiring board by a die bonding film.
An electronic device comprising a carrier and the package structure of any one of claims 1-11 carried on the carrier.
The electronic device of claim 12, wherein the package structure is fixed on the carrier via solder balls, and the package structure communicates with a circuit or a device on the carrier via the solder balls.