CN219163385U - High heat dissipation substrate structure and packaging structure - Google Patents
High heat dissipation substrate structure and packaging structure Download PDFInfo
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- CN219163385U CN219163385U CN202223297940.0U CN202223297940U CN219163385U CN 219163385 U CN219163385 U CN 219163385U CN 202223297940 U CN202223297940 U CN 202223297940U CN 219163385 U CN219163385 U CN 219163385U
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Abstract
The utility model discloses a high-heat-dissipation substrate structure and a packaging structure, wherein the heat-dissipation core plate of the high-heat-dissipation substrate structure can play roles in supporting and dissipating heat so as to play a good role in dissipating heat for a high-power component subsequently packaged at the top of the high-power component, and the high-heat-dissipation substrate structure is beneficial to ensuring normal use of the high-power component. The conductive through holes of the heat dissipation core plate are arranged, so that a heat dissipation channel from the top to the bottom is formed conveniently, and the heat dissipation effect is improved; on the other hand, the interconnection distance between the substrate and the bottom substrate is reduced, so that the packaging thickness of a stacked device formed on the basis of a high-heat-dissipation substrate structure is reduced; the conductive through holes are arranged in the heat dissipation core plate, and have good heat dissipation effect. The packaging structure is convenient to use, has more convenient packaging and good heat dissipation effect, and is suitable for packaging the top packaging body with the high-power chip.
Description
Technical Field
The utility model relates to a high-heat-dissipation substrate structure and a packaging structure.
Background
The three-dimensional packaging method represented by the package on package (Package on Package, poP) has also become the mainstream packaging method at present, and is widely applied to various high-end portable electronic products, especially to mobile communication chips and memory chip packages, so as to meet the requirements of the high-speed digital signal processing and memory response time.
Chinese patent publication No. CN103354225B discloses a stacked package device, in which a first package element and a second package element are electrically connected together by a solder ball, and in which a third package element is disposed in a space surrounded by the first package element, the second package element and the solder ball, a gap is fully utilized to reduce the thickness of the multi-layer stacked package device. However, the first package element and the second package element are interconnected by a solder ball, and if the first package element at the top is provided with a high-power chip, the heat dissipation effect is poor due to the limited heat dissipation channels from the top to the bottom of the stacked package device, which can affect the service life of the high-power chip. In addition, because the solder balls collapse under high-temperature melting, in order to ensure that the solder balls are not in short circuit, a larger solder ball pitch, for example, more than 500 micrometers, is required, so that the size of a packaged device is not reduced; the size of the solder balls between the first package member and the second package member needs to be selected according to the height of the third package member, and the thickness of the stack can be reduced to be small although the gap is reduced by a certain thickness. In addition, the substrates of the first packaging element and the second packaging element are two substrates which are arranged separately, and two substrates need to be prepared for board preparation and packaging respectively during packaging, so that the processing steps are more.
Therefore, how to overcome the above-mentioned drawbacks has become an important issue to be solved by the person skilled in the art.
Disclosure of Invention
The utility model overcomes the defects of the technology and provides a high-heat-dissipation substrate structure and a packaging structure.
In order to achieve the above purpose, the present utility model adopts the following technical scheme:
a high heat dissipation substrate structure includes:
a plurality of conductive through holes extending up and down are arranged in the heat dissipation core plate;
the top substrate comprises at least two layers of circuits, wherein the bottommost circuit is connected with the top of the conductive through hole, and the topmost circuit is a first outer circuit layer;
the bottom substrate comprises at least two layers of circuits, wherein the topmost circuit is connected with the bottom of the conductive through hole, and the bottommost circuit is a second outer circuit layer.
Preferably, the heat dissipation core plate is made of copper, the conductive material filled in the conductive through holes is copper, a resin layer is arranged between the heat dissipation core plate and the conductive through holes, and the first outer circuit layer and the second outer circuit layer are covered with solder masks.
Preferably, a first through groove is formed in the middle of the top substrate, the heat dissipation core plate is in a convex shape, the heat dissipation core plate comprises a protruding portion and a supporting portion, and a groove for placing a chip is formed between the upper end face of the protruding portion and two side walls of the first through groove.
Preferably, one or more layers of inner circuit layers are arranged between the first outer circuit layer and the top of the conductive through hole, between the bottom of the conductive through hole and the second outer circuit layer, and medium layers are arranged between adjacent inner circuit layers, between the first outer circuit layer and the inner circuit layer, between the second outer circuit layer and the inner circuit layer, between the inner circuit layer closest to the top of the conductive through hole and the top of the conductive through hole, and between the inner circuit layer closest to the bottom of the conductive through hole and the top of the conductive through hole.
A package structure, comprising:
a high heat dissipation substrate structure;
one or more top components are stacked and connected to the upper surface of the high-heat-dissipation substrate structure, wherein one top component is a high-power chip;
the plastic layer covers the upper surface of the high-heat-dissipation substrate structure and is used for plastic packaging of one or more top components;
the external solder ball is connected to the lower surface of the high-heat-dissipation substrate structure;
and the bottom component is connected to the lower surface of the high-heat-dissipation substrate structure and is packaged between the external solder balls.
Preferably, the bottom component is a flip chip, and the external solder ball can avoid the flip chip and form a space with the lower surface of the bottom substrate for placing the bottom component therein.
Preferably, the high-power chip is mounted on the heat dissipation core plate and connected with the upper surface of the top substrate through leads.
Compared with the prior art, the utility model has the beneficial effects that:
1. the heat dissipation core plate of the high heat dissipation substrate structure can play a role in supporting and dissipating heat, so that high-power components at the top of the high-power components can play a good role in dissipating heat conveniently, and normal use of the high-power components is guaranteed. The conductive through holes of the heat dissipation core plate are arranged, so that a heat dissipation channel from top to bottom is formed conveniently, and the heat dissipation effect is improved; on the other hand, the interconnection between the top substrate and the bottom substrate is convenient to realize, and compared with the prior art, a chip is not arranged between the top substrate and the bottom substrate, the thickness of the heat dissipation core plate can be 30 microns at the minimum, the interconnection thickness is greatly reduced, and the subsequent packaging thickness of the stacked packaging body formed based on the high heat dissipation substrate structure is reduced; and the conductive through holes are less deformed under high-temperature melting, so that the conductive through holes can be designed with smaller pitch and cannot cause short circuit, thereby being convenient for reducing interconnection pitch and being beneficial to reducing the volume of the high-heat-dissipation substrate structure/the stacked package. The arrangement of the top substrate and the bottom substrate is convenient for stacking and connecting the top component and the bottom component in the subsequent packaging process, and is beneficial to realizing a stacked packaging structure.
2. The heat dissipation core plate is made of copper, so that the heat dissipation core plate has good heat conduction capacity, and the high heat dissipation substrate structure has good heat dissipation effect. The arrangement of copper is filled in the conductive through hole so as to utilize good electric conduction and heat conduction capacity of copper, and heat dissipation can be realized while electric conduction is ensured. The resin layer is provided so as to serve as insulation. The arrangement of the solder mask layer is convenient for playing an insulating protection role on the same-layer circuit and preventing the part which is not welded from being connected by soldering tin.
3. The heat dissipation core board is in the convex arrangement, on one hand, the structure with the upper part short and the lower part long is convenient to form, so that the bottom is convenient to have a larger heat dissipation volume, heat generated by the top can be dissipated to the bottom more easily, and the requirement of packaging high-power components at the top is met. The arrangement of the protruding portion is convenient for form a groove for placing a chip with the first through groove, so that the space of the first through groove can be fully utilized, and the stacking thickness is reduced. The support part is arranged so as to play a supporting role. The grooves are formed, so that chips placed in the grooves can be attached to the heat-dissipation core plates conveniently, and heat dissipation of the chips is facilitated; on the other hand, the packaging height can be reduced by being matched with the size of a chip placed in the packaging structure.
4. The high-heat-dissipation substrate structure of the packaging structure is an integer, and only one substrate is needed to be prepared during packaging, so that the top component or the bottom component can be directly packaged on the substrate structure, the processing steps are reduced, and the packaging is convenient. The high-heat-dissipation substrate structure is convenient to use the performance of the heat-dissipation core plate arranged in the high-heat-dissipation substrate structure, is convenient to stack and connect the heat dissipation of the high-power chip on the upper surface of the high-heat-dissipation core plate, has a good heat dissipation effect, ensures that the heat generated by the high-power chip can be dissipated in time, and is beneficial to ensuring the normal use of the high-power chip; on the other hand, a plurality of conductive through holes which are arranged in the conductive through holes and extend up and down are convenient to form a heat dissipation channel which extends up and down, so that the heat dissipation effect is improved; and the conductive through holes can also realize interconnection of the top component and the bottom component, replace welding ball interconnection, are favorable for reducing interconnection distance and interconnection pitch, and can reduce stacking thickness and packaging volume. The plastic layer is convenient to insulate and protect the top components. The external solder balls are arranged so as to be convenient for connection with external components/external devices.
Drawings
Fig. 1 is a schematic cross-sectional view of a high heat dissipation substrate structure.
Fig. 2 is a schematic structural view of a heat sink core.
Fig. 3 is a schematic cross-sectional view of a package structure of the present disclosure.
Detailed Description
The following examples are provided to illustrate the features of the present utility model and other related features in further detail to facilitate understanding by those skilled in the art:
as shown in fig. 1 and 2, a high heat dissipation substrate structure includes:
a heat radiation core plate 000, in which a plurality of conductive through holes 1 extending up and down are provided;
the top substrate 100 includes three layers of wires, wherein the bottom layer of wires is connected with the top of the conductive via 1, and the top layer of wires is a first outer wire layer 101;
the bottom substrate 200 includes two layers of wires, the topmost layer of wires is connected to the bottom of the conductive via 1, and the bottommost layer of wires is the second outer layer 201.
As described above, the heat-dissipating core plate 000 of the high-heat-dissipating substrate structure can play a role in supporting and dissipating heat, so that a good heat-dissipating effect can be played on the high-power components subsequently packaged at the top of the high-power components, and normal use of the high-power components is guaranteed. The conductive through holes 1 of the heat dissipation core plate 000 are arranged, so that a heat dissipation channel from top to bottom is formed, and the heat dissipation effect is improved; on the other hand, the interconnection between the top substrate 100 and the bottom substrate 200 is convenient to realize, and compared with the prior art, a chip is not arranged between the top substrate 100 and the bottom substrate 200, the minimum thickness of the heat dissipation core plate 000 can be 30 microns, the interconnection thickness is greatly reduced, and the reduction of the packaging thickness of a subsequent stacked package formed based on a high heat dissipation substrate structure is facilitated; the conductive through holes 1 are less deformed under high-temperature melting, so that the conductive through holes can be designed with smaller pitch and cannot cause short circuit, thereby being convenient for reducing interconnection pitch and being beneficial to reducing the volume of the high-heat-dissipation substrate structure/the stacked package. The top substrate 100 and the bottom substrate 200 are arranged so that the top component and the bottom component can be stacked and connected during subsequent packaging, which is beneficial to realizing a stacked packaging structure.
From the above, the heat dissipation core plate 000 is made of copper, and the conductive material filled in the conductive through hole 1 is copper; as shown in fig. 1, a resin layer 120 is provided between the heat-dissipating core plate 000 and the conductive via 1; the first outer circuit layer 101 is covered with a first solder resist layer 1010, and the second outer circuit layer 201 is covered with a second solder resist layer 2010. In particular, the heat-dissipating core plate 000 may be made of nickel or other materials with better heat-conducting capability; the formation process of the conductive through hole 1 is as follows: the conductive via 1 is formed by forming a large hole by machining on the heat-dissipating core plate 000, filling resin inside and curing, then forming a small hole by machining inside the resin, and finally filling copper in the small hole so that the inner wall of the small hole is covered with a resin layer 120 and the copper at the top and the copper at the bottom are exposed outside.
As described above, the heat-dissipating core plate 000 is made of copper, so as to have good heat-conducting capability, and thus the high heat-dissipating substrate structure has good heat-dissipating effect. The conductive through hole 1 is internally filled with copper so as to utilize good electric conduction and heat conduction capacity of copper, and heat dissipation can be realized while electric conduction is ensured. The resin layer 120 is provided so as to serve an insulating function. The arrangement of the solder mask layer is convenient for playing an insulating protection role on the same-layer circuit and preventing the part which is not welded from being connected by soldering tin.
As shown in fig. 1 and 2, in the implementation, a first through groove 21 is formed in the middle of the top substrate 100, the heat dissipation core plate 000 is in a convex shape, the heat dissipation core plate 000 includes a protruding portion 001 and a supporting portion 002, and a groove 3 for placing a chip is formed between an upper end surface of the protruding portion 001 and two side walls of the first through groove 21.
As described above, the heat-dissipating core board 000 is arranged in a convex shape, so that on one hand, a structure with a short top and a long bottom is formed, so that the bottom has a larger heat-dissipating volume, and in addition, heat generated at the top can be more easily dissipated to the bottom, which is beneficial to meeting the requirement of packaging high-power components at the top. The protruding portion 001 is arranged, so that the groove 3 for placing chips is formed with the first through groove 21, and therefore the space of the first through groove 21 can be fully utilized, and the stacking thickness is reduced. The support portion 002 is provided so as to play a supporting role. The grooves 3 are arranged, so that chips placed in the grooves can be attached to the heat dissipation core plate 000 conveniently, and heat dissipation of the chips is facilitated; on the other hand, the packaging height can be reduced by being matched with the size of a chip placed in the packaging structure. In specific implementation, the protruding portion 001 and the supporting portion 002 may be selected according to the thickness of the chip, so that the height of the first through groove 21 is greater than the height of the protruding portion 001, and a groove 3 matching the chip size is formed.
As shown in fig. 1, a first inner circuit layer 102 and a second inner circuit layer 103 are sequentially disposed between the first outer circuit layer 101 and the top of the conductive via 1 from top to bottom, a third inner circuit layer 202 is disposed between the bottom of the conductive via 1 and the second outer circuit layer 201, a first dielectric layer 104 is disposed between the first inner circuit layer 102 and the second inner circuit layer 103, a second dielectric layer 105 is disposed between the first outer circuit layer 101 and the first inner circuit layer 102, a third dielectric layer 203 is disposed between the second outer circuit layer 201 and the third inner circuit layer 202, a fourth dielectric layer 301 is disposed between the top of the conductive via 1 and the second inner circuit layer 103, and a fifth dielectric layer 204 is disposed between the bottom of the conductive via 1 and the third inner circuit layer 202. In this way, the insulation between the wires and the layers is maintained.
As shown in fig. 1 and 3, a package structure includes a high heat dissipation substrate structure, three top components stacked and connected on an upper surface of the high heat dissipation substrate structure, a plastic layer 400 covering the upper surface of the high heat dissipation substrate structure, external solder balls 600 connected on a lower surface of the high heat dissipation substrate structure, and bottom components connected on the lower surface of the high heat dissipation substrate structure and packaged between the external solder balls, wherein the plastic layer 400 is used for plastic packaging the three top components; the three top components are respectively a high-power chip 401, a first flip chip 402 and a second flip chip 403, which are stacked and connected on the upper surface of the high-heat-dissipation substrate structure.
The high-heat-dissipation substrate structure of the packaging structure is an integer, and only one substrate is needed to be prepared during packaging, so that the top component or the bottom component can be directly packaged on the substrate structure, the processing steps are reduced, and the packaging is convenient. The arrangement of the high-heat-dissipation substrate structure is convenient for utilizing the performance of the heat-dissipation core plate 000 arranged therein, is convenient for stacking the heat dissipation of the high-power chip 401 connected to the upper surface of the high-heat-dissipation core plate, has good heat dissipation effect, ensures that the heat generated by the high-power chip 401 can be timely dissipated, and is beneficial to ensuring the normal use of the high-power chip 401; on the other hand, a plurality of conductive through holes 1 which are arranged in the conductive through holes and extend up and down are convenient to form a heat dissipation channel which extends up and down, so that the heat dissipation effect is improved; and the conductive through hole 1 can also realize interconnection of the top component and the bottom component, replace welding ball interconnection, be favorable to reducing interconnection distance and interconnection pitch, can reduce stacking thickness and packaging volume. The arrangement of the plastic layer 400 is convenient for playing an insulating protection role on the top components. The external solder balls 600 are provided to facilitate connection with external components/external devices.
As shown in fig. 3, the bottom component is a third flip chip 500, and the external solder ball 600 can avoid the third flip chip 500 and form a space with the lower surface of the bottom substrate 200 in which the third flip chip 500 is placed. In this way, the external solder balls 600 are conveniently arranged according to the shape of the bottom component, so that the space of the bottom is fully utilized, and the stacking thickness is reduced. In particular, the height of the external solder ball 600 is higher than the thickness of the bottom component.
In the embodiment shown in fig. 3, the high-power chip 401 is mounted on the heat-dissipating core board and connected to the upper surface of the top substrate 100 by leads 404. In this way, on one hand, the heat dissipation core board 000 is convenient to be attached to the heat dissipation core board 000 of the high-heat dissipation substrate structure, so that the high-power chip 401 can fully dissipate heat; and on the other hand, to facilitate interconnection with the top substrate 100 via the leads 404.
As described above, the top substrate 100 described in the present embodiment has 3 layers of conductive traces, and the bottom substrate 200 has 2 layers of conductive traces. The stacked package substrate can be designed into any conductive circuit layer structure according to the actual requirements of chip package. The bottom of the first flip chip 402, the second flip chip 403, the third flip chip 500 and the other small gaps in the package structure described in the embodiment of the present application are all provided with the filling glue layer 700, which can perform a good sealing function.
As described above, the present disclosure protects a high heat dissipation substrate structure and a packaging structure, and all technical solutions identical or similar to the present disclosure should be shown as falling within the scope of the present disclosure.
Claims (7)
1. The utility model provides a high heat dissipation base plate structure which characterized in that includes:
a plurality of conductive through holes extending up and down are arranged in the heat dissipation core plate;
the top substrate comprises at least two layers of circuits, wherein the bottommost circuit is connected with the top of the conductive through hole, and the topmost circuit is a first outer circuit layer;
the bottom substrate comprises at least two layers of circuits, wherein the topmost circuit is connected with the bottom of the conductive through hole, and the bottommost circuit is a second outer circuit layer.
2. The high heat dissipation substrate structure as defined in claim 1, wherein the heat dissipation core board is made of copper, the conductive material filled in the conductive through holes is copper, a resin layer is disposed between the heat dissipation core board and the conductive through holes, and the first outer circuit layer and the second outer circuit layer are covered with solder resists.
3. The structure of claim 1 or 2, wherein a first through groove is formed in the middle of the top substrate, the heat dissipation core plate is in a convex shape, the heat dissipation core plate comprises a protruding portion and a supporting portion, and a groove for placing a chip is formed between an upper end surface of the protruding portion and two side walls of the first through groove.
4. The high heat dissipation substrate structure of claim 1, wherein one or more inner circuit layers are disposed between the first outer circuit layer and the top of the conductive via, between the bottom of the conductive via and the second outer circuit layer, between adjacent inner circuit layers, between the first outer circuit layer and the inner circuit layer, between the second outer circuit layer and the inner circuit layer, between the inner circuit layer closest to the top of the conductive via and the top of the conductive via, and between the inner circuit layer closest to the bottom of the conductive via and the top of the conductive via.
5. A package structure, characterized by comprising:
the high heat dissipation substrate structure of any one of claims 1-4;
one or more top components are stacked and connected to the upper surface of the high-heat-dissipation substrate structure, wherein one top component is a high-power chip;
the plastic layer covers the upper surface of the high-heat-dissipation substrate structure and is used for plastic packaging of one or more top components;
the external solder ball is connected to the lower surface of the high-heat-dissipation substrate structure;
and the bottom component is connected to the lower surface of the high-heat-dissipation substrate structure and is packaged between the external solder balls.
6. The package structure of claim 5, wherein the bottom component is a flip chip, and the external solder balls can avoid the flip chip and form a space with the lower surface of the bottom substrate for placing the bottom package therein.
7. The package structure of claim 5, wherein the high power chip is mounted on the heat sink core and connected to the top substrate upper surface by leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223297940.0U CN219163385U (en) | 2022-12-07 | 2022-12-07 | High heat dissipation substrate structure and packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223297940.0U CN219163385U (en) | 2022-12-07 | 2022-12-07 | High heat dissipation substrate structure and packaging structure |
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| Publication Number | Publication Date |
|---|---|
| CN219163385U true CN219163385U (en) | 2023-06-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223297940.0U Active CN219163385U (en) | 2022-12-07 | 2022-12-07 | High heat dissipation substrate structure and packaging structure |
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| Country | Link |
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| CN (1) | CN219163385U (en) |
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2022
- 2022-12-07 CN CN202223297940.0U patent/CN219163385U/en active Active
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