CN108550566A - The three-dimensional stacked interconnection structure of SiC device based on nano mattisolda and preparation method - Google Patents
The three-dimensional stacked interconnection structure of SiC device based on nano mattisolda and preparation method Download PDFInfo
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- CN108550566A CN108550566A CN201810326712.0A CN201810326712A CN108550566A CN 108550566 A CN108550566 A CN 108550566A CN 201810326712 A CN201810326712 A CN 201810326712A CN 108550566 A CN108550566 A CN 108550566A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3731—Ceramic materials or glass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
Abstract
The present invention provides a kind of three-dimensional stacked interconnection structure of SiC device based on nano mattisolda and preparation methods, the interconnection structure includes nano mattisolda and ceramic wafer, the through-hole of ceramic wafer is filled with nano mattisolda, sintering forms conductive path, it is further sintered by nano mattisolda, realizes the stacked interconnected of chip electrode；Ceramic substrate increases the distance of two chips, avoids the edge breakdown effect of chip chamber as insulation board and pad level；Longitudinal interconnection of multiple chips can be achieved in the connection of the interconnection structure, and selected materials include ceramic substrate and nano mattisolda, main component is silver after nano mattisolda sintering, and electric conductivity is close with heat resistance with fine silver, it is heat-resisting material, can be used for the interconnection of high-power chip；Simple in structure compared with other packing forms, operability is strong, and has more universal applicability, is the simple and effective method for realizing high temperature and pressure stacked package.
Description
Technical field
The present invention relates to semiconductor power device encapsulation field more particularly to a kind of SiC devices based on nano mattisolda
Three-dimensional stacked interconnection structure and preparation method realize power core by nano mattisolda for filling ceramic through-hole and stacked interconnected
Piece it is three-dimensional stacked.
Background technology
Silicon carbide is typical third generation semi-conducting material, with the continuous development of electronic industry, silicon carbide device is met the tendency of
And give birth to, operating temperature is high, high pressure, and old packing forms are difficult the complete superiority for playing silicon carbide device.Silicon carbide device
Demand of the part to encapsulation is mainly reflected in high temperature and pressure encapsulation, currently, it is also seldom for the research unit of silicon carbide device encapsulation,
The encapsulation of more silicon carbide power chips is mostly modular form, bulky, is welded by solder and realizes chip attachment, using lead
Bonding realizes that the interconnection of chip electrode and external terminal, the main problem of solder welding are welding layer material after the completion of welding
The problem of matter is constant, and heatproof is relatively low, influences the selection of secondary welding material, wire bonding is that package dimension is limited to lead
Highly, lead increases parasitic inductance and resistance, reduces package reliability.Vertical stack is to realize minimize, is integrated
One of effective way, the key factor of limitation vertical stack encapsulation technology development is the interconnection technique of chip chamber, at present core
The technical method interconnected between piece is also very immature, it is therefore desirable to study new packing forms to meet the needs of high temperature and pressure, together
When reduce encapsulation volume, increase package reliability.
The applicant have been proposed entitled a silicon carbide device encapsulating structure based on three layers of DBC substrates and
Manufacturing method, Publication No. CN107393882A, publication date are on November 24th, 2017, and encapsulating structure includes in the technical solution
The DBC substrates of three layer patterns form Up-Center-Down Structure, and two layers of nano mattisolda, longitudinal silicon carbide power chip and high temperature resistant are filled out
Material；But realize chip electrode without lead merely by graphical and nano mattisolda the connection of DBC substrates in the program
It draws, the interconnection structure of three stackings cannot be formed.
Invention content
It is an object of the invention to realize silicon carbide device it is three-dimensional stacked meet the needs of high temperature and pressure, while as possible
Reduce encapsulation volume, increases package reliability, the technical problem to be solved in the present invention is the connectivity problem of multi-chip stacking, this
Connection structure not only high temperature high voltage resistant, and stable connection is reliable.
In order to achieve the above objectives, the following technical solutions are proposed by the present invention：
A kind of three-dimensional stacked interconnection structure of SiC device based on nano mattisolda, is made of ceramic substrate and nano mattisolda, pottery
It is drilled with through-hole on porcelain substrate, metal copper seed layer is deposited in through-hole wall and two linkage interfaces, nanometer silver soldering is filled in through-hole
Cream, sintering form conductive path, and the connection for realizing each electrode of chip is further sintered by nano mattisolda.
Preferably, the packing material and interconnection material are nano mattisolda, and nano mattisolda itself has mobility,
Facilitate brushing, and filling gap is more easy to by pressurization.
Preferably, the ceramic substrate in the three-dimensional stacked interconnection structure of the SiC device based on nano mattisolda is to pass through
Laser boring forms through-hole, and through-hole wall and two linkage interfaces deposit metal copper seed layer.
Preferably, 100 μm ~ 2mm of through-hole aperture range in the ceramic substrate, aperture more bigger easier filling.
Preferably, the chip is silicon carbide power chip, and its upper and lower surface is silver-plated.
Preferably, the production method of the three-dimensional stacked interconnection structure of the SiC device based on nano mattisolda is as follows：
（1）Ceramic substrate laser boring, according to the size of the position and aperture of electrode size design punching；
（2）The surface of ceramic substrate and through-hole side wall deposit seed layer, then in the electroplate of ceramic substrate；
（3）Chip is carried out two-sided silver-plated；
（4）The through-hole of ceramic substrate is filled with nano mattisolda, is sintered, connection structure is formed；
（5）Ceramic substrate is fixed using mold, then brushes nano mattisolda on the two sides of ceramic substrate, chip is formed
Stacked structure, pressure sintering；
（6）It completes.
The three-dimensional stacked interconnection structure of SiC device and preparation method provided in said program is applied to silicon carbide power device
The three-dimension packaging of part stacks connection.By the combination of ceramic substrate and nano mattisolda, connection structure is formd, ceramic substrate is made
For intermediate insulating layer and pad level, realize that the large aperture of ceramic substrate is filled by nano mattisolda.Ceramic substrate is not only led
Hot coefficient is high, high temperature resistant, and good insulation preformance, can alleviate the edge breakdown effect of chip chamber under high voltage to a certain extent.
Its 90% or more ingredient is silver after the completion of nano mattisolda sintering, and heatproof is up to 900 DEG C, and the microstructure of nano silver is more
Pore structure can buffer the stress that different interfaces are generated by thermal mismatching.
Material therefor is heat-resisting material in the present invention, both ensure that the longitudinally connected of chip chamber electrode, has in turn ensured
Chip chamber is reliably mechanically connected, and is improved the problem that traditional wire bonding connect band is come, is shortened interconnection distance, increase
Contact area enhances the service life of chip, improves the reliability of device.
Description of the drawings
Fig. 1 is the structural diagram of the present invention.
Fig. 2 is the structure preparation flow schematic diagram of the present invention.
Fig. 3 is the pressure sintering schematic diagram of the present invention.
Wherein：1,4,7-- silicon carbide power chips, 2,5-- nano mattisoldas, 2.1,2.3,5.1,5.3-linkage interfaces
Between nano mattisolda, 2.2, the nano mattisolda in 5.5-- ceramic substrate through-holes, 3,6-- ceramic substrates.
Specific implementation method
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention is clearly completely retouched
It states, it is clear that described embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on this hair
Embodiment in bright, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a kind of SiC device three-dimensional stacking structure based on nano mattisolda is as shown in Figure 1, packet
It includes：Three silicon carbide power chips 1,4,7, are vertical structure diode；Two layers of interconnection structure 2,3,5,6.Wherein mutually connection
Structure is made of the ceramic substrate 3,6 with through-hole and nano mattisolda 2,5, the through-hole aperture in ceramic substrate>100 μm,
The upper and lower surface of the hole wall of through-hole and ceramic substrate deposits one layer of metal layer as seed layer, silver-plated on surface layer, passes through screen printing
Then the full ceramic through-hole of the relatively large nano mattisolda filling of mobility, low-temperature bake are fixed by mold and are made pottery by brush method
Porcelain plate assembles silicon carbide power chip and connection structure, slightly presses respectively in two surface printing nano mattisolda of ceramic wafer
It is overflowed to soldering paste, is placed in warm table and is sintered, both obtain the three-dimensional stacking structure of silicon carbide power chip.
The preparation implementation steps of the SiC device three-dimensional stacking structure based on nano mattisolda are as follows：
（1）Ceramic substrate 3,6 laser borings, according to electrode size and structure design punch position；
（2）Ceramic substrate 3,6 surfaces and through-hole side wall deposit coating metal layer, electroplate；
（3）Silicon carbide power chip 1,4,7 carries out two-sided silver-plated；
（4）Ceramic substrate 3,6 is positioned over smooth plate, the relatively large nano mattisolda of mobility is passed through into method for printing screen
With needle tubing method for filling, fill the through-hole of full ceramic substrate, i.e., the nano mattisolda 2.2,5.2 in ceramic substrate through-hole, together with
Smooth plate and ceramic substrate are positioned over warm table and carry out low-temperature bake drying together；
（5）It is fixed on graphic arts die as shown in Fig. 2, ceramic substrate is removed, brushes nano silver on the two sides of ceramic substrate respectively
Soldering paste, i.e., 2.1,2.3,5.1,5.3 between linkage interface, stacked interconnected structure is made；
（6）By the silicon carbide power chip 1,4,7 and stacking connecting structure of two-sided silver, stacked structure stacks as shown in Figure 3
Assembling applies certain pressure to soldering paste and overflows silicon carbide power chip 1,4,7；
（7）Assembled structure is positioned over warm table to be sintered.
The present invention selects pure ceramic wafer, is sintered by punching, plating, filling perforation and the vertical of Different electrodes is realized in interconnection sintering
To interconnection, it can be achieved that the series connection of multi-chip.
Claims (6)
1. the three-dimensional stacked interconnection structure of SiC device based on nano mattisolda, which is characterized in that the interconnection structure is by ceramic base
Plate and nano mattisolda composition, fill potsherd through-hole by nano mattisolda first, are then realized and are connected by nano mattisolda
Connect the connection of each electrode of chip.
2. the three-dimensional stacked interconnection structure of the SiC device according to claim 1 based on nano mattisolda, which is characterized in that
The packing material and interconnection material are nano mattisolda.
3. the three-dimensional stacked interconnection structure of the SiC device according to claim 1 based on nano mattisolda, which is characterized in that
Ceramic substrate in the interconnection structure is to form through-hole by laser boring, and through-hole wall and two linkage interfaces deposit gold
Belong to copper seed layer.
4. the three-dimensional stacked interconnection structure of the SiC device according to claim 1 based on nano mattisolda, which is characterized in that
100 μm ~ 2mm of through-hole aperture range in the ceramic substrate, aperture more bigger easier filling.
5. the three-dimensional stacked interconnection structure of the SiC device according to claim 1 based on nano mattisolda, which is characterized in that
The chip is silicon carbide power chip, and its upper and lower surface is silver-plated.
6. preparing the three-dimensional stacked interconnection structure of the SiC device based on nano mattisolda described in claim 1-5 any one
Method, it is characterised in that steps are as follows：
（1）Ceramic substrate laser boring, according to the size of the position and aperture of electrode size design punching；
（2）The surface of ceramic substrate and through-hole side wall deposit seed layer, then in the electroplate of ceramic substrate；
（3）Chip is carried out two-sided silver-plated；
（4）The through-hole of ceramic substrate is filled with nano mattisolda, is sintered, connection structure is formed；
（5）Ceramic substrate is fixed using mold, then brushes nano mattisolda on the two sides of ceramic substrate, chip is formed
Stacked structure, pressure sintering；
（6）It completes.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810326712.0A CN108550566B (en) | 2018-04-12 | 2018-04-12 | SiC device three-dimensional stacking interconnection structure based on nano-silver solder paste and preparation method |
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| CN201810326712.0A CN108550566B (en) | 2018-04-12 | 2018-04-12 | SiC device three-dimensional stacking interconnection structure based on nano-silver solder paste and preparation method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111696870A (en) * | 2020-05-20 | 2020-09-22 | 广东佛智芯微电子技术研究有限公司 | Double-sided fan-out packaging method and double-sided fan-out packaging structure |
| CN112786531A (en) * | 2020-12-31 | 2021-05-11 | 广东工业大学 | Method for preparing deep hole interconnection structure based on nano metal |
| CN112864125A (en) * | 2021-01-13 | 2021-05-28 | 深圳第三代半导体研究院 | High-heat-dissipation chip packaging interconnection material |
| CN112969309A (en) * | 2020-08-28 | 2021-06-15 | 重庆康佳光电技术研究院有限公司 | Welding method of circuit board and light-emitting device, display module, panel and welding flux |
| CN113534366A (en) * | 2021-08-13 | 2021-10-22 | 亨通洛克利科技有限公司 | High-density CPO silicon optical engine |
| CN116825752A (en) * | 2023-08-29 | 2023-09-29 | 江西兆驰半导体有限公司 | Wafer and printing method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1464767A (en) * | 2002-06-24 | 2003-12-31 | 威盛电子股份有限公司 | Method for making base plate conducting hole and wiring of circuit using printing mode |
| TW200816439A (en) * | 2006-07-26 | 2008-04-01 | Texas Instruments Inc | Array-processed stacked semiconductor packages |
| CN102157438A (en) * | 2011-01-31 | 2011-08-17 | 江阴长电先进封装有限公司 | Method for manufacturing wafer-level patch panel |
| CN103824853A (en) * | 2014-02-24 | 2014-05-28 | 矽力杰半导体技术(杭州)有限公司 | Integrated circuit module applied to switch type regulator |
| CN104900768A (en) * | 2015-04-14 | 2015-09-09 | 芜湖九瓷电子科技有限公司 | Preparation method for alumina ceramic substrate for LED |
| CN105097750A (en) * | 2014-05-08 | 2015-11-25 | 矽品精密工业股份有限公司 | Package structure and method for fabricating the same |
| CN205069618U (en) * | 2015-09-29 | 2016-03-02 | 比亚迪股份有限公司 | Power module and vehicle that has it |
-
2018
- 2018-04-12 CN CN201810326712.0A patent/CN108550566B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1464767A (en) * | 2002-06-24 | 2003-12-31 | 威盛电子股份有限公司 | Method for making base plate conducting hole and wiring of circuit using printing mode |
| TW200816439A (en) * | 2006-07-26 | 2008-04-01 | Texas Instruments Inc | Array-processed stacked semiconductor packages |
| CN102157438A (en) * | 2011-01-31 | 2011-08-17 | 江阴长电先进封装有限公司 | Method for manufacturing wafer-level patch panel |
| CN103824853A (en) * | 2014-02-24 | 2014-05-28 | 矽力杰半导体技术(杭州)有限公司 | Integrated circuit module applied to switch type regulator |
| CN105097750A (en) * | 2014-05-08 | 2015-11-25 | 矽品精密工业股份有限公司 | Package structure and method for fabricating the same |
| CN104900768A (en) * | 2015-04-14 | 2015-09-09 | 芜湖九瓷电子科技有限公司 | Preparation method for alumina ceramic substrate for LED |
| CN205069618U (en) * | 2015-09-29 | 2016-03-02 | 比亚迪股份有限公司 | Power module and vehicle that has it |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111696870A (en) * | 2020-05-20 | 2020-09-22 | 广东佛智芯微电子技术研究有限公司 | Double-sided fan-out packaging method and double-sided fan-out packaging structure |
| CN112969309A (en) * | 2020-08-28 | 2021-06-15 | 重庆康佳光电技术研究院有限公司 | Welding method of circuit board and light-emitting device, display module, panel and welding flux |
| CN112969309B (en) * | 2020-08-28 | 2022-04-19 | 重庆康佳光电技术研究院有限公司 | Welding method of circuit board and light-emitting device, display module, panel and welding flux |
| CN112786531A (en) * | 2020-12-31 | 2021-05-11 | 广东工业大学 | Method for preparing deep hole interconnection structure based on nano metal |
| CN112786531B (en) * | 2020-12-31 | 2022-04-19 | 广东工业大学 | Method for preparing deep hole interconnection structure based on nano metal |
| CN112864125A (en) * | 2021-01-13 | 2021-05-28 | 深圳第三代半导体研究院 | High-heat-dissipation chip packaging interconnection material |
| CN113534366A (en) * | 2021-08-13 | 2021-10-22 | 亨通洛克利科技有限公司 | High-density CPO silicon optical engine |
| CN116825752A (en) * | 2023-08-29 | 2023-09-29 | 江西兆驰半导体有限公司 | Wafer and printing method thereof |
| CN116825752B (en) * | 2023-08-29 | 2024-02-09 | 江西兆驰半导体有限公司 | Wafer and printing method thereof |
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