KR101225253B1 - Silicone through via for bonding chips, chip and mounted chips comprising the same, and method for bonding mounted chips by electroplating - Google Patents

Abstract

Provided is a silicon substrate through via for chip bonding, a chip comprising the same, a stacked chip, and a stacked chip bonding method using electroplating.
The silicon substrate through via for chip bonding according to the present invention may include a metal part filling the inside of the silicon through via hole penetrating the chip; A metal pad connected to the metal part and stacked on the silicon through via hole; And a metal bump connected to the metal part and protruding from the chip by a predetermined height under the silicon through via hole, wherein the metal pad or metal bump is in contact with the metal bump or metal pad of another chip. The present invention is advantageous in that the machining process is simple and the productivity is high because the present invention can simultaneously bond the contact portions of a plurality of stacked chips having TSVs using electroplating.

Description

Silicon through via for bonding chips, chip and mounted chips comprising the same, and method for bonding mounted chips by electroplating}

The present invention relates to a silicon chip through via for chip bonding, a chip comprising the same, a laminated chip and a method of laminated chip bonding using an electroplating method, and more particularly, an electric using a metal bump exposed to a predetermined height from a chip to be bonded. The present invention relates to a through-silicon substrate through via for chip bonding, a chip including the same, a laminated chip, and an electroplating method, which can simultaneously proceed a plurality of chip bonding at a low temperature by plating.

Recently, as the miniaturization and high performance of electronic products have increased, the integration density of semiconductor chips has increased, and in order to satisfy such a trend, stacked chips having a three-dimensional shape in which a plurality of chips are stacked in a height direction are used. Various methods for manufacturing a stacked chip have been proposed, and a method using a silicon through via (TSV) among them has an advantage of minimizing the size of the stacked chip and shortening the length of the signal line. The silicon through via (TSV) is a structure in which a metal or the like is laminated in a hole (hole) penetrating a silicon chip in a thickness direction. In the prior art, the hole is processed, and a thin insulating layer and a metal seed are formed on an inner surface of the through hole. Layer) and the metal seed layer is filled with a conductive metal such as copper or tin. In order to manufacture a stacked chip, a plurality of chips processed by TSV are aligned in a height direction, and a stack is manufactured by joining TSVs of an upper chip and a lower chip.

A number of patents and research papers have been published on the method of joining a multilayer chip, mainly using soldering or thermocompression bonding. In Korean Patent No. 10-2008-0086206, “Semiconductor package and manufacturing method thereof”, a method of forming a through electrode using a photosensitive conductive film on a wafer on which a via hole is formed, stacking chips, and applying heat to cure the through electrode is bonded. In "Stack Package and Manufacturing Method" of Korean Patent No. 10-2007-0063181, a method of forming a TSV on a chip and bonding the TSV of the stacked chip with a solder paste has been presented, and the Korean Patent No. 10-2006-0025054 Stack Package ”and Korean Patent No. 10-2005-0062752“ Three-dimensional Chip Lamination Method Using Reflow Solder ”propose a method of manufacturing a laminated chip by melting solder in a state in which solder is formed on a chip or a substrate and laminated. It was. Korean Patent No. 10-2006-0001150 "Multi-stack package and a method of manufacturing the same" presented a thermocompression method for forming a gold bump (Au) bump on the laminated chip and making a joint by applying pressure. Korean Patent No. 10-2008-0068334 "Chip stack package having a tin via or solder via and a connection thereof and a manufacturing method thereof" has proposed a method of forming a connection by soldering a TSV filled with tin or copper. In addition, a research paper (“3D packaging process and equipment technology using TSV”, Korean Society of Precision Engineering, Vol. 26, No. 12, 2009) as a method for joining TSVs has been described in the thermocompression bonding method of Cu-Cu or Cu-Sn. Describes the soldering joining method of Cu. The bonding method of the laminated chip described in the above patents and research papers is a soldering or thermocompression method, and when such a method is used, damage to the chip may occur because the bonding temperature is high or excessive force is applied.

Accordingly, the present invention has been made to solve the problems of the prior art as described above, to provide an electroplating chip bonding method and a silicon through via structure of a novel structure therefor. As a result, a plurality of laminated chips are bonded at one time by electroplating using a metal wire and a metal plate to increase productivity, and to form a joint at a low temperature, thereby improving reliability.

In order to solve the above problems, the present invention provides a cylindrical silicon through via (TSV) for chip bonding, a metal portion filling the inside of the silicon through via hole penetrating the chip; is connected to the metal portion, the silicon through A metal pad stacked over the via hole; And a metal bump connected to the metal part and protruding from the chip by a predetermined height under the silicon through via hole, wherein the metal pad or metal bump is in contact with the metal bump or metal pad of another chip. And through-silicon vias for laminated chip bonding, characterized in that they are electroplated.

In one embodiment of the present invention, the metal bump may contact the metal pad of another substrate having the silicon through via of claim 1.

In one embodiment of the present invention, the metal pad may be in contact with a metal bump of another substrate having silicon through vias.

In one embodiment of the present invention, the metal pad is larger than the silicon through via hole width, and the metal bump end is conical, hemispherical or flat.

The present invention provides a chip including one or more silicon through vias as described above in order to solve the another problem.

The present invention is also a laminated chip in which one or more of the above-described chips are bonded to each other, and the bonding of the contact chip is performed by electroplating metal pads and metal bumps which are in contact with each other through silicon through vias provided in the chips.

In order to solve the above another object, the present invention is a laminated chip bonding method, the method comprises the steps of stacking a plurality of chips including the silicon through vias described above, contacting the silicon through vias of the chip with each other; It provides a laminated chip bonding method comprising the step of electroplating the silicon through vias in contact with each other in a plating solution.

In an embodiment of the present invention, the electroplating may be performed on a cathode of a DC power source commonly connected to a plurality of metal plates parallel to the side of the chip and a plurality of metal wires across the chip and a cathode of a DC power source connected to the silicon through via. It is carried out in a manner of flowing a current.

In one embodiment of the present invention, the plurality of metal wires cross each other perpendicularly, and the plurality of metal plates and metal wires are four.

In one embodiment of the present invention, the metal wire is coated with an insulating material in the first region where the silicon through via is formed in the chip, and is not coated with the insulating material in the second region where the silicon through via is not formed.

In one embodiment of the invention, the method further comprises the step of physically removing the metal wire after electroplating, the metal plate and the metal wire is copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), and lead (Pb).

In an embodiment of the present invention, the through-silicon vias are formed in the outer region of the chip, and the metal wires are exposed to the outside in the central region of the chip where the through-silicon vias are not formed.

In order to solve the above another problem, the present invention provides a laminated chip bonded by the above-described method.

According to the present invention, since the contact portions of a plurality of stacked chips having TSVs can be simultaneously bonded using electroplating, the machining process is simple and the productivity is high. In addition, the stacked chip bonding method according to an embodiment of the present invention uses the plurality of metal wires and the metal plate extended to the center of the chip as an anode to perform electroplating, so that plating is uniform even when the TSV is disposed at the center of the chip. The advantage is that it can be done. In addition, in one embodiment of the present invention, since the metal wire is exposed only to the center portion of the chip and is covered with an insulating material in the outer region where the TSV is formed, the metal wire may be in contact with the bump or the like of the TSV. After forming the metal joint with the electroplating together, there is an advantage that the metal wire is easy to remove. Furthermore, since the joint is formed at low temperature by the plating, there is an advantage that a reliable joint can be formed because residual stress and deformation do not occur. Also, since the metal joint is formed by electroplating, the electrical conductivity and the bond strength are high. There is an advantage.

1 is a view illustrating a TSV structure for chip-to-chip bonding according to an embodiment of the present invention.
2A and 2B are respectively a perspective cross-sectional view and a plan view for explaining the chip structure including the TSV of FIG.
3A to 3D are step-by-step schematic diagrams illustrating a method of bonding a TSV of a stacked chip by an electroplating method according to an embodiment of the present invention.
4 is a plan view illustrating an anode structure including a metal plate and a metal wire connected to a DC power source in the electroplating method according to an embodiment of the present invention.
5 is a schematic view for explaining an electroplating apparatus for bonding a stacked chip.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the drawings. The following embodiments are provided as examples to ensure that the spirit of the present invention can be fully conveyed to those skilled in the art. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. And in the drawings, the width, length, thickness, etc. of the components may be exaggerated for convenience, the same reference numerals throughout the specification represent the same components,

The present invention, in order to solve the above-mentioned problems of the prior art for laminated chip bonding, the through silicon via (TSV) according to the present invention is a metal (hole) of the cylinder structure through the silicon chip The filled structure is a basic structure, and the TSV according to the present invention further includes a metal pad having a predetermined width on the upper portion of the metal filling the inside of the hole, and a metal bump below the metal pad protruding from the chip by a predetermined height. . The silicon through via of the above structure according to the present invention functions as a bonding means for bonding between stacked chips.

1 is a view illustrating a TSV structure for chip-to-chip bonding according to an embodiment of the present invention.

Referring to FIG. 1, first, the insulating layer 120 and the metal seed layer 130 are sequentially stacked in the TSV 170, which is a hollow cylinder-shaped hole penetrating in the thickness direction of the chip 100. The seed layer 130 is filled with a metal part 140 made of a metal material having high electrical conductivity, for example, copper. In addition, a metal pad 150 is formed on an upper portion of the TSV 170, and a metal bump 160, which is a metal part protruding by a predetermined height from a height of the chip 100, is formed on a lower portion of the TSV 170. In one embodiment of the present invention, the metal bumps 160 and the metal pads 150 are preferably made of the same metal material, but the scope of the present invention is not limited thereto. In addition, since the metal pad 150 is in contact with the metal bump of another chip to be chip-to-chip bonding by electroplating, it is preferable that the metal pad 150 has a width wider by a predetermined length than the hole width of the TSV. Alignment is easier

In addition, the end shape of the metal bump 160, which is a metal part protruding from the chip in the TSV according to the exemplary embodiment of the present invention, may be a convex hemispherical shape or a planar shape, but preferably a conical shape 160. Thus, after contact with the metal pad of the other chip, when the electroplating, there is an advantage that can form a metal joint without pores therein. In an embodiment of the present invention, the end shape of the metal bumps 160 of the TSV was easily processed into a conical shape or a hemispherical shape using an etching method.

2A and 2B are respectively a perspective cross-sectional view and a plan view for explaining the chip structure including the TSV of FIG.

Referring to FIG. 2A, which is a perspective cross-sectional view of a chip, a chip 100 having a plurality of TSVs described with reference to FIG. 1 is disclosed, and the TSV 170 includes a metal pad 150 and a lower portion protruding from the chip by a predetermined height. And metal bumps 160.

Referring to FIG. 2B, the TSV having the metal pad 150 formed thereon is arranged in duplicate along the outer side surface of the chip. However, the scope of the present invention is not limited to the form shown in FIG. 2B.

3A to 3D are step-by-step schematic diagrams illustrating a method of bonding a TSV of a stacked chip by an electroplating method according to an embodiment of the present invention. Although two stacked chip junctions will be described with reference to the following drawings, the scope of the present invention is not limited thereto, and the present invention may also be applied to a chip junction having a multilayer structure in which two or more chips are stacked.

Referring to FIG. 3A, the TSV metal pad 220 of the lower chip 200 on which the TSV is formed and the TSV metal bump 230 of the upper chip 210 are aligned and contacted with each other. Then, the metal plate 240 spaced apart from the side of the chip and parallel to the side is connected to the positive pole of the DC power, and the bump 230 and the pad 220 of the TSV in contact with each other is connected to the negative pole of the DC power. Then, by generating a current in the DC power supply in the plating solution, a metal layer 250 is plated between the bump 230 and the pad 220, which is a cathode, so that the metal pad of the lower chip TSV junction and the metal of the upper chip TSV junction Another junction is formed between the bumps. As a result, the lower chip 200 and the upper chip 210, to which TSVs contact each other, are physically bonded by the plated metal layer 250.

However, when the anode is used as the single metal plate 240 as shown in FIG. 3A, the inventors have a metal layer 250 that is plated on the TSV in a portion close to the single metal plate 240 as the anode, and the plating layer 260 of TSV far away from the anode. The thickness of) was found to be greatly reduced. Thus, another embodiment of the present invention, as shown in Figure 3b, instead of a single metal plate, a plurality of metal plate 240 (four metal plates along the four sides of the square chip in the horizontal side of the chip chip in FIG. 3b) By using the electroplating, the amount of plated as a whole compared to the single metal plate of Figure 3a is uniform.

However, even in the case of the multi-metal plate configuration according to FIG. 3B, a problem arises in that the thickness of the chip edge close to the metal plate and the chip center region far away from the metal plate are non-uniform due to the distance difference between the anode and the chip edge. The thickness of the plating layer 250 of the TSV is relatively thicker than the thickness of the first plating layer 260 of the TSV in the central region. Therefore, in order to increase the thickness of the TSV plating layer 260 arranged at the center of the chip, another embodiment of the present invention uses a metal wire extending to the center of the chip in addition to the plurality of metal plates on the outer side of the chip, which will be described in detail below. .

3C and 3D, a metal plate 240 serving as a plurality of electrodes is provided on the side of the chip 200 and faces each other on the side of the chip having a quadrangular shape. However, in the present exemplary embodiment, a plurality of metal wires 270 crossing the lower chip 200 and vertically intersecting with each other in addition to the metal plate 240 are proposed as an element of the anode structure. That is, the metal wire 270 is connected to the anode of the DC power supply together with the metal plate 240, and the electroplating proceeds. In an embodiment of the present invention, the four metal plates 240 and the four metal wires 270 on the lower chip 200 are connected to the anode of the DC power source to perform electroplating, but the scope of the present invention is It is not limited.

According to an embodiment of the present invention, the metal plate 240 and the metal wire 270 connected to the positive pole of the DC power source may be separated from each other, or may be connected to each other, and in any case, are commonly connected to the positive pole of the DC power source. In addition, the metal wire 270 is preferably made of the same material as the four metal plates 240, which are anodes provided on the side of the chip. Furthermore, according to an embodiment of the present invention, the metal wire 270 is entirely insulated. In the chip region where the material 280 is coated but without the TSV, the inner metal wire is exposed to the outside. Herein, the chip region in which the TSV is not formed means a predetermined region in which the upper metal wire is physically moved to contact the TSV. Accordingly, the metal wire on the lower chip may be in contact with the TSV by the coating of the insulating material 280. After the plating is completed, the metal wire on the chip may be removed by a physical method, for example, nippers or scissors. .

Referring to FIG. 3D, the upper chip 210 and the lower chip 200 are stacked on each other, and the two stacked chips are in contact with each other through the metal bumps 230 and the metal pads 220 of the respective TSVs. In addition, the stacked side of the chip is provided with a metal plate 240 that is an electrode pad flat to the edge of the chip, the lower chip 200 is provided with a plurality of metal wires 270 perpendicular to each other and cross. In addition, the insulation coating structure of the metal wire 270 is as described above. In this case, in the stacked chip bonding method according to the present invention, the upper chip 210 and the lower chip 200 are aligned as shown in FIG. 3D, and the TSVs of the respective chips are in contact with each other. Thereafter, provided on the lower chip 200, four metal wires 270 intersecting with each other and four metal plates parallel along the side of the chip are applied with a current to the anode of the DC power supply, and the electroplating is performed in the plating solution. In addition, the plating amount of the contact portion of the TSV arranged in the center of the chip, which is the cathode, increases according to the electroplating, and thus the TSV junction portion obtains a uniform bonding force throughout the chip.

4 is a plan view illustrating an anode structure including a metal plate and a metal wire connected to a DC power source in the electroplating method according to an embodiment of the present invention.

Referring to FIG. 4, a plurality of TSVs 170, which are via holes penetrating a silicon substrate, are provided along the edge of the quadrangular chip 200 on the chip 200. The TSV 170 is formed with a metal pad formed in the upper part as shown in FIG. 1 and a metal bump protruding downward. A metal wire 270 is formed on the chip 200 to be connected to the anode of the DC power source, where the metal wire 270 is a first region A (ie, a metal wire contactable region) outside the chip on which the TSV is formed. In this case, the insulating material 280 is coated. However, the metal wires 270 in the second region C of the chip center where the TSV is not formed (C, the non-metal wire contact region) are exposed as they are. According to the present invention, an anode having the same distance is formed at the center and the outside of the chip 200 through such a configuration, and makes the TSV plating amount in the chip center region and the plating amount in the outer region uniform.

5 is a schematic view for explaining an electroplating apparatus for bonding a stacked chip.

Referring to FIG. 5, the plating solution 300 is filled with an electrolyte solution 310, which is a plating solution, and the upper chip 330 and the lower chip 340 on which the TSV 320 described with reference to FIG. 1 are formed are aligned. The TSVs of the chips are in contact with each other. According to the electroplating apparatus according to the present invention, the metal plate 350 installed on the upper chip 330 of the stacked chip immersed in the internal electrolyte solution 310 and in contact with the electrode pad of the upper chip TSV is a direct current power source 360. Is connected to the cathode of). In addition, the anode of the DC power supply 360 crosses the chip 340 and the plurality of metal plates 370 (for example, four) arranged in parallel along the side of the chip, and vertically intersects the chip. It is connected with the some metal wire 380 (for example, four). After the current flows through the plating solution, metal is plated and a physical junction is formed on the contact portion between the metal bump of the upper chip 330 TSV of the TSV 320 and the metal pad of the lower chip TSV.

In the present invention, a metal material such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), and lead (Pb) as a material of the plated metal plate 370 and the wire 380. It is possible to form a junction using, but the present invention is not limited thereto.

In the above description, the technical details of the bonding method of the multilayer chip using the electroplating of the present invention have been described together with the accompanying drawings, but this is only illustrative of the best embodiment of the present invention and is not intended to limit the present invention.

In addition, it is obvious that any person skilled in the art can make various modifications and imitations within the scope of the appended claims without departing from the scope of the technical idea of the present invention.

Claims (16)

delete delete delete delete delete delete delete In the laminated chip bonding method, the method,
A cylindrical silicon through via (TSV) for chip bonding, comprising: a metal portion filling an inside of a silicon through via hole penetrating the chip; A metal pad connected to the metal part and stacked on the silicon through via hole; And a metal bump connected to the metal part and protruding from the chip by a predetermined height under the silicon through via hole, wherein the metal pad or metal bump is in contact with the metal bump or metal pad of another chip. Stacking a plurality of chips including silicon through vias for laminated chip bonding, wherein the silicon through vias of the chips are in contact with each other; And
And electroplating the silicon through vias in contact with each other in a plating solution. The method of claim 8,
The electroplating is performed by passing a current through a cathode of a DC power source commonly connected to a plurality of metal plates parallel to the side of the chip and a plurality of metal wires across the chip and a cathode of a DC power source connected to the through silicon vias. Laminated chip bonding method, characterized in that. The method of claim 9,
And the plurality of metal wires cross each other perpendicularly. The method of claim 10,
The plurality of metal plate and the metal wire is a laminated chip bonding method, characterized in that four. The method of claim 9,
And the metal wire is covered with an insulating material in a first region where silicon through vias are formed in the chip, and is not coated with an insulating material in a second region where silicon through vias are not formed. The method of claim 12, wherein the method
And after the electroplating, the metal wires are further physically removed. The method of claim 13,
The metal plate and the metal wire are made of at least one material selected from the group consisting of copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), and lead (Pb). Laminated chip bonding method. The method of claim 13,
The silicon through via is formed in the outer region of the chip, the metal wire is a laminated chip bonding method, characterized in that the inner metal material is exposed to the outside in the center region of the chip where the silicon through via is not formed. A laminated chip bonded by the method according to any one of claims 8 to 15.

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