CN213635974U

CN213635974U - Chip packaging structure

Info

Publication number: CN213635974U
Application number: CN202022283700.XU
Authority: CN
Inventors: 常健伟; 周小磊; 康文彬
Original assignee: Luxshare Electronic Technology Kunshan Ltd
Current assignee: Luxshare Electronic Technology Kunshan Ltd
Priority date: 2020-10-14
Filing date: 2020-10-14
Publication date: 2021-07-06
Anticipated expiration: 2030-10-14

Abstract

The utility model relates to a chip package technical field discloses a chip packaging structure. The chip packaging structure comprises a substrate, wherein the front surface of the substrate is provided with at least one groove, at least one chip is attached in the groove, the front surface of the substrate is also provided with a first electrical property leading-out structure, and the electrical property of the chip is led to the first electrical property leading-out structure through a first metal rewiring; the back of the substrate is provided with a second electrical property derivation structure, the substrate is also provided with a conductive through hole penetrating through the front and the back of the substrate, the electrical property of the chip is led out to the second electrical property derivation structure through the first metal rewiring and the conductive through hole, and the first electrical property derivation structure and the second electrical property derivation structure are respectively arranged at two ends of the conductive through hole. The utility model discloses dwindle the interconnection pitch, reduced the loss, reduced wiring area or realized wiring higher density under the certain circumstances of area.

Description

Chip packaging structure

Technical Field

The utility model relates to a chip package technical field especially relates to a chip package structure.

Background

In the current semiconductor industry, electronic packaging has become an important direction for industry development, and in the process of decades of packaging technology development, the packaging requirements of high density, small size, low loss and low cost have become the mainstream direction of packaging.

The embedded substrate wafer level three-dimensional packaging realizes three-dimensional fan-out packaging of chips at a wafer level, is an advanced packaging process with a large I/O number and good integration flexibility, and can realize multi-chip integration in vertical and horizontal directions in one packaging body. With the development and maturation of temporary bonding technology, thin wafers and their surface structures can be supported and protected by the carrier, and therefore fan-out wafer level packaging is being developed into the next generation packaging technology.

From the packaging structure disclosed at present, the packaging volume needs to be further reduced, the interconnection pitch needs to be further reduced, and the rewiring density needs to be further improved.

SUMMERY OF THE UTILITY MODEL

Based on above, the utility model aims to provide a chip packaging structure to further reduce the encapsulation volume, shorten interconnection pitch, promote rewiring density.

In order to achieve the purpose, the utility model adopts the following technical proposal:

a chip packaging structure comprises a substrate, wherein the front surface of the substrate is provided with at least one groove, at least one chip is attached in the groove, the front surface of the substrate is also provided with a first electrical property leading-out structure, and the electrical property of the chip is led to the first electrical property leading-out structure through first metal rewiring; the back of base plate is equipped with the second electrical property and derives the structure, the base plate still is equipped with the electrically conductive through-hole that runs through its front and back, the electrical property of chip passes through first metal rewiring and electrically conductive through-hole draws forth to the back of base plate the second electrical property is derived the structure, just first electrical property is derived the structure with the second electrical property is derived the structure branch and is located the both ends of electrically conductive through-hole.

As a preferred embodiment of the chip package structure, the conductive through hole includes a straight hole perpendicular to the substrate, and the first electrical derivation structure and the second electrical derivation structure at two ends of the conductive through hole are respectively located right above and right below the straight hole.

As a preferred scheme of the chip packaging structure, the first electrical conduction structure is one of a solder ball, a metal bump and a conductive adhesive; the second electrical conduction structure is one of a solder ball, a metal bump and conductive adhesive.

As a preferred scheme of the chip packaging structure, the first electrical lead-out structure is a solder ball, and the second electrical lead-out structure is a metal bump; or, the first electrical lead-out structure is a metal bump, and the second electrical lead-out structure is a solder ball.

As a preferred scheme of the chip packaging structure, a groove-shaped holding structure is arranged on one end face, far away from the substrate, of the metal bump.

As a preferable scheme of the chip packaging structure, when two adjacent chip packaging structures are stacked, the chips in the two chip packaging structures are electrically connected in a face-to-face, face-to-back or back-to-back manner.

As a preferred scheme of a chip packaging structure, the front surface of the substrate is provided with one groove, and two chips are attached in the groove; or the front surface of the substrate is provided with two grooves, and one chip is attached in each groove.

As a preferred scheme of a chip packaging structure, a first pad is arranged on the surface of the chip, the first metal redistribution line comprises a second pad positioned above the front surface of the chip and a second pad positioned at one end of the conductive through hole facing the front surface of the substrate, the electrical property of the first pad is led to the second pad through the first metal redistribution line, insulating layers are arranged between the first metal redistribution line and the chip and the substrate and between the chip and the side wall of the groove, a first passivation layer is coated outside the first metal redistribution line, and the first electrical property leading-out structure is arranged on the second pad in a third reserved opening on the first passivation layer; the base plate back is equipped with the insulating layer, be equipped with the second metal rewiring on the insulating layer at the base plate back, the second metal rewiring is including being located the third pad of chip back below and being located the electrically conductive through-hole orientation the third pad of the one end at the base plate back, the outer cladding of second metal rewiring has the second passivation layer, the second electrical property derive the structure set up in the fourth reservation opening on the second passivation layer on the third pad.

As a preferred scheme of a chip packaging structure, the side wall and the bottom of the conductive through hole are covered with conductive metal; or, the conductive through hole is filled with conductive metal or conductive adhesive.

As a preferable scheme of the chip packaging structure, an upper opening of the groove is not smaller than a bottom opening of the groove, and a vertical cross section of the groove is rectangular or trapezoidal.

The utility model has the advantages that:

the utility model provides a chip package structure, the structure is derived to the positive first electrical property of base plate through first metal rewiring to the electrical property of chip, the structure is derived to the second electrical property that the electrical property of chip was still drawn forth to the base plate back through first metal rewiring and electrically conductive through-hole simultaneously, and the structure is derived to first electrical property and the structure is derived to the second electrical property and is divided the both ends of locating electrically conductive through-hole, above-mentioned structure has realized the three-dimensional direct interconnection of base plate tow sides, reducing the encapsulation volume, shorten the interconnection pitch, on the basis of reduction loss, further reduce wiring area or wiring more densely under the certain circumstances of area. The chip packaging structure is easy to realize miniaturization and thinning, and is convenient for three-dimensional stacking.

Drawings

Fig. 1 is a schematic diagram of a first chip package structure according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a second chip package structure according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a third chip package structure according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a fourth chip package structure according to an embodiment of the present invention;

fig. 5 is a schematic diagram of two chip package structures stacked in a face-to-face manner according to an embodiment of the present invention;

fig. 6 is a schematic diagram illustrating a two-chip package structure stacked in a back-to-back manner according to an embodiment of the present invention;

fig. 7 is a schematic diagram of two chip package structures stacked in a back-to-back manner according to an embodiment of the present invention;

fig. 8 is a schematic cross-sectional view illustrating a second embodiment of the present invention, in which a groove is formed on the front surface of a substrate, and a first insulating layer is formed on the substrate and the groove;

FIG. 9 is a schematic cross-sectional view of a second embodiment of the present invention, showing a chip attached to the bottom of a groove;

fig. 10 is a schematic cross-sectional view of a second embodiment of the present invention, in which a second insulating layer is formed on the front surface of the substrate, and a first reserved opening and a second reserved opening are formed in the second insulating layer;

fig. 11 is a schematic cross-sectional view of a second embodiment of the present invention, in which a first metal redistribution layer is formed on a second insulating layer, a first passivation layer is formed on the first metal redistribution layer, and a third reserved opening is formed on the first passivation layer;

fig. 12 is a schematic cross-sectional view illustrating the first temporary bonding of the first carrier sheet on the front surface of the substrate through the first adhesive layer according to the second embodiment of the present invention;

fig. 13 is a schematic cross-sectional view of the embodiment of the present invention, in which two pairs of substrates are thinned, through holes are formed, third insulating layers are formed on the back surfaces of the substrates and the through holes, and the third insulating layers and the first insulating layers at the bottoms of the through holes are removed;

fig. 14 is a schematic cross-sectional view of a second embodiment of the present invention, in which metal is filled in the through hole, a second metal redistribution layer is formed on the back surface of the substrate, a second passivation layer is formed on the second metal redistribution layer, a fourth reserved opening is formed in the second passivation layer, and a second electrical property derivation structure is formed in the fourth reserved opening;

fig. 15 is a schematic cross-sectional view illustrating a second temporary bonding of a second carrier sheet on the back surface of the substrate via a second adhesive layer according to an embodiment of the present invention;

fig. 16 is a schematic cross-sectional view of the second embodiment of the present invention, in which the first carrier sheet and the first adhesive layer are removed, and the first electrical property derivation structure is formed in the third reserved opening;

fig. 17 is a schematic cross-sectional view of the second embodiment of the present invention after the second carrier sheet and the second adhesive layer are removed.

In the figure:

1. a substrate; 11. a groove; 2. a chip; 21. a first pad; 3. a first electrical lead-out structure; 4. a first metal redistribution line; 41. a second pad; 5. a second electrical lead-out structure; 6. a conductive via; 61. a through hole; 7. a second metal redistribution line; 71. a third pad; 101. a first insulating layer; 102. a second insulating layer; 1021. a first reserved opening; 1022. a second reserved opening; 103. a first passivation layer; 1031. a third reserved opening; 104. a first adhesive layer; 105. a first carrier sheet; 106. a third insulating layer; 107. a second passivation layer; 108. a second adhesive layer; 109. and a second carrier sheet.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

In the description of the present invention, unless expressly stated or limited otherwise, the terms "connected," "connected," and "fixed" are to be construed broadly, e.g., as meaning permanently connected, detachably connected, or integral to one another; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

In the description of the present embodiment, the terms "upper", "lower", "left", "right", and the like are used based on the orientations and positional relationships shown in the drawings only for convenience of description and simplification of operation, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used only for descriptive purposes and are not intended to have a special meaning.

Example one

As shown in fig. 1-7, the present embodiment provides a chip package structure, which includes a substrate 1, where the substrate 1 is used as a base body for embedding a chip 2, and the material of the substrate may be silicon, glass, ceramic, metal, or a PCB board, and preferably, a silicon substrate is used in the present embodiment. The front surface of the substrate 1 is provided with at least one groove 11, and at least one chip 2 is attached in each groove 11. In this embodiment, the vertical cross-sectional shape of the groove 11 may be a trapezoid, a rectangle, or the like, and the top view shape of the groove 11 may be a rectangle, a square, or other shapes suitable for various chips 2 and the arrangement of the chips 2. The upper opening of the groove 11 is not smaller than the bottom opening of the groove 11, the depth is smaller than or equal to the thickness of the substrate 1, and the size of the groove 11 is such that the chip 2 can be placed therein. The chip 2 is mounted in the groove 11 through adhesive glue or a dry film; the chip 2 may be an analog integrated circuit chip, a digital/analog hybrid integrated circuit chip, a MEMS chip, or the like, so as to implement corresponding functions. In addition, the material of the chip 2 of the present embodiment is the same as the material of the substrate 1, which is advantageous in that the thermal expansion coefficient between the substrate 1 and the chip 2 can be made similar, and the package structure has excellent reliability.

The front surface of the substrate 1 is further provided with a first electrical property leading-out structure 3 and a first metal redistribution line 4, and the electrical property of the chip 2 is led to the first electrical property leading-out structure 3 through the first metal redistribution line 4. The back of the substrate 1 is provided with a second metal rewiring 7 and a second electrical property leading-out structure 5, the substrate 1 is further provided with a conductive through hole 6 penetrating through the front and the back of the substrate 1, the electrical property of the chip 2 is led out to the second electrical property leading-out structure 5 on the back of the substrate 1 through the first metal rewiring 4 and the conductive through hole 6, and the first electrical property leading-out structure 3 and the second electrical property leading-out structure 5 are respectively arranged at two ends of the conductive through hole 6. In this embodiment, the conductive via 6 includes a via and a conductive structure disposed in the via, specifically, the conductive structure is a conductive metal or a conductive adhesive, and the front surface and the back surface of the substrate 1 are electrically conductive by filling the via completely or filling only a part of the via (for example, only covering the sidewall and the bottom of the via). In this embodiment, it is preferable to completely fill the through hole 61 with a conductive metal, where the conductive metal may be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, and gold, and in this embodiment, it is preferable to use titanium and copper.

The embodiment realizes three-dimensional direct interconnection of the front surface and the back surface of the substrate 1, and further reduces the wiring area or wires with higher density under the condition of a certain area on the basis of reducing the packaging volume, shortening the interconnection pitch and reducing the loss. The chip packaging structure is easy to realize miniaturization and thinning, and is convenient for three-dimensional stacking.

Preferably, the conductive via 6 of the present embodiment is perpendicular to the substrate 1, and the first electrical lead-out structure 3 and the second electrical lead-out structure 5 are respectively located right above and right below the conductive via 6. By the arrangement, three-dimensional vertical interconnection of the front surface and the back surface of the substrate 1 is realized, interconnection pitches of the front surface and the back surface of the substrate 1 are further shortened, and loss is further reduced. Of course, in other embodiments, the conductive through hole 6 may also be disposed obliquely according to the requirement, and is not limited to this embodiment.

In this embodiment, the first electrical lead-out structure 3 is one of a solder ball, a metal bump and a conductive adhesive; the second electrical lead-out structure 5 is also one of a solder ball, a metal bump and a conductive adhesive. Moreover, the positions of the first electrical lead-out structure 3 and the second electrical lead-out structure 5 on the front and back sides of the substrate 1 can be interchanged, for example, as shown in fig. 1, the first electrical lead-out structure 3 is a solder ball, and the second electrical lead-out structure 5 is a metal bump; for example, as shown in fig. 2, the first electrical lead-out structures 3 are metal bumps, and the second electrical lead-out structures 5 are solder balls, and the different electrical lead-out structures are arranged to facilitate different ways of stacking the packages. Further, the metal bump is kept away from the terminal surface of base plate 1 and is still equipped with the groove-shaped and holds the structure of embracing, holds the effect of embracing the structure and lies in: the protruding parts of the corresponding solder balls are held during three-dimensional stacking, and better electrical contact is realized.

In the embodiment of the present invention, only one groove 11 may be formed in the front surface of the substrate 1, and only one chip (as shown in fig. 1 and fig. 2) is disposed in the groove 11, which has a simple structure and is convenient to connect; or, the front surface of the substrate 1 may be provided with a groove 11, and two chips 2 (as shown in fig. 3) are attached in the groove 11, so as to save space better and provide more functions to the package; or, the front surface of the substrate 1 may be provided with two grooves 11, and each of the grooves 11 is attached with one chip 2 (as shown in fig. 4), and the structure can also effectively improve the space utilization rate of the substrate 1 and reduce the product volume. The different arrangement of the grooves 11 and the chips 2 can meet different processing requirements and stacking requirements to realize more advanced system integration.

In this embodiment, as shown in fig. 5, when two adjacent chip package structures are stacked, the chips 2 in the two chip package structures may be electrically connected in a face-to-face manner, that is, the front structures of the two substrates 1 are arranged oppositely, and the first electrical lead-out structures 3 in the two chip package structures are electrically connected to each other. Alternatively, as shown in fig. 6, when two adjacent chip package structures are stacked, the chips 2 in the two chip package structures may also be electrically connected in a back-to-back manner, that is, the front structure of one substrate 1 is opposite to the back surface of the other substrate 1, and the first electrical lead-out structure 3 in one chip package structure is electrically connected to the second electrical lead-out structure 5 in the other chip package structure. Alternatively, as shown in fig. 7, when two adjacent chip package structures are stacked, the chips 2 in the two chip package structures may also be electrically connected in a back-to-back manner, that is, the back structures of the two substrates 1 are arranged oppositely, and the second electrical lead-out structures in the two chip package structures are electrically connected to each other. In practical applications, the stacking manner of the package structure can be flexibly selected according to the requirement, and is not limited to the embodiment.

Further, with reference to fig. 1, the surface of the chip 2 of this embodiment has two first pads 21, the first metal redistribution lines 4 include two second pads 41 located above the front surface of the chip 2 and two second pads 41 located at an end of the conductive through hole 6 facing the front surface of the substrate 1, and the electrical property of the first pads 21 is led to the second pads 41 through the first metal redistribution lines 4. Insulating layers are arranged between the first metal redistribution layer 4 and the chip 2 and the substrate 1 and between the chip 2 and the side wall of the groove 11, a first passivation layer 103 is coated outside the first metal redistribution layer 4, and the first electrical property derivation structure 3 is arranged on the second welding pad 41 in the third reserved opening 1031 on the first passivation layer 103; the back surface of the substrate 1 is also provided with an insulating layer, the insulating layer on the back surface of the substrate 1 is provided with a second metal redistribution line 7, and the second metal redistribution line 7 comprises two third pads 71 positioned below the back surface of the chip 2 and two third pads 71 positioned at one end of the conductive through hole 6 facing the back surface of the substrate 1. The second metal redistribution layer 7 is wrapped by a second passivation layer 107, and the second electrical lead-out structure 5 is disposed on the third pad 71 in the fourth reserved opening on the second passivation layer 107.

The three-dimensional packaging structure after the fan-out of the embedded substrate is adopted in the embodiment, the substrate fan-out is adopted, thin lines and high-density wiring can be manufactured, and the requirement of high-density O/I can be met. The chip packaging structure can realize three-dimensional stacking of chips, wafers and wafers.

Example two

As shown in fig. 8 to 17, the present embodiment provides a chip packaging method using a substrate 1 as a buried base; manufacturing high-density wiring and an electric insulation layer on the front surface of the substrate 1; bonding a first bearing sheet 105 on the front surface of the substrate 1 by using a first temporary bonding technology so as to protect the front surface structure of the substrate 1 and the support substrate 1; then thinning and manufacturing a conductive through hole 6 on the back surface of the substrate 1 to connect circuits on the front surface and the back surface of the substrate 1, manufacturing a high-density rewiring and an insulating layer on the back surface of the substrate 1, and manufacturing a second electrical lead-out structure 5 under the conductive through hole 6 and at other positions of the substrate 1; then bonding a second carrier sheet 109 on the back surface of the substrate 1 by a second temporary bonding technique to protect and support the back surface of the substrate 1; then, the first bearing sheet 105 temporarily bonded for the first time is disassembled, and a first electrical lead-out structure 3 is manufactured on the front surface of the substrate 1 right above the conductive through hole 6 and at other positions of the substrate 1; and finally, disassembling the second bearing sheet 109 temporarily bonded for the second time, thereby realizing three-dimensional direct interconnection after the chip 2 is embedded into the substrate and fanned out.

Specifically, the chip packaging method of the embodiment includes the following steps:

s1, as shown in fig. 8, first, a substrate 1 is provided, the substrate 1 has a front surface and a back surface, at least one recess 11 is formed on the front surface of the substrate 1, and a first insulating layer 101 is formed on the front surface of the substrate 1 and the surface of the recess 11.

In step S1 of this embodiment, the material of the substrate 1 may be silicon, glass, ceramic, metal, or PCB, and preferably, a silicon substrate is used in this embodiment. The first insulating layer 101 may be formed by depositing a silicon oxide layer on the front surface of the substrate 1 and the surface of the recess 11. Of course, in other embodiments, when the substrate 1 is made of an insulating material, the first insulating layer 101 may not be additionally formed.

In this embodiment, the groove 11 may be formed by etching, the vertical cross-sectional shape of the groove 11 may be a trapezoid, a rectangle, or the like, and the overlooking shape of the groove 11 may be a rectangle, a square, or other shapes suitable for various chips 2 and arrangement of the chips 2. The upper opening of the groove 11 is not smaller than the bottom opening of the groove 11, the depth is smaller than or equal to the thickness of the substrate 1, and the size of the groove 11 is such that the chip 2 can be placed therein.

S2, as shown in fig. 9, at least one chip 2 is mounted in the recess 11, the upper surface of the chip 2 has at least one first pad 21, and a gap is formed between the chip 2 and the sidewall of the recess 11.

In this embodiment, the bonding pad surface of the chip 2 faces outward, and the bonding pad surface of the chip 2 is close to the front surface of the substrate 1, so as to facilitate subsequent processing and reduce the overall size of the package structure. In specific implementation, the chip 2 may be attached to the groove 11 of the substrate 1 by an adhesive or a dry film, and the embodiment preferably uses an adhesive for bonding. In addition, the chip 2 of the present embodiment is made of the same material as the substrate 1, which is advantageous in that the thermal expansion coefficient between the substrate 1 and the chip 2 is similar, and thus the package structure has excellent reliability.

S3, as shown in fig. 10, a second insulating layer 102 is disposed in the gap between the chip 2 and the sidewall of the recess 11, the upper surface of the chip 2 and the front surface of the substrate 1, and a first reserved opening 1021 and a second reserved opening 1022 are formed on the second insulating layer 102 by photolithography, wherein the first reserved opening 1021 exposes the first pad 21 of the chip 2, and the second reserved opening 1022 is located in the outer region of the recess 11.

In this embodiment, the second insulating layer 102 may be formed by coating a photoresist or by pressing a dry film, and the embodiment preferably adopts a dry film pressing manner, so that not only the gap between the chip 2 and the sidewall of the groove 11 can be effectively filled, but also the flat second insulating layer 102 can be formed. Exemplarily, the chip 2 of the present embodiment has two first pads 21, and the first preformed opening 1021 has two first pads 21 and two first preformed openings corresponding to the first pads 21; two second reserved openings 1022 are also provided, respectively located at two sides of the recess 11, and the positions thereof correspond to the positions of the conductive through holes 6 in the subsequent step.

S4, as shown in fig. 11, fabricating a first metal redistribution layer 4 on the second insulating layer 102, where the first metal redistribution layer 4 includes a second pad 41 formed at the second preformed opening 1022 (the second pad 41 is located at an end of the conductive via 6 facing the front surface of the substrate 1), and the first metal redistribution layer 4 electrically leads the first pad 21 to the second pad 41; a first passivation layer 103 is fabricated on the first metal redistribution line 4, and a third reserved opening 1031 is formed on the first passivation layer 103 by photolithography, and the third reserved opening 1031 exposes the first metal redistribution line 4.

Further, in this embodiment, the first metal redistribution layer 4 further includes two second pads 41 located in the region above the front surface of the chip 2. The third reserved openings 1031 are also provided with four, which correspond to the positions of the four second bonding pads 41 respectively, so as to expose the second bonding pads 41, thereby facilitating the fabrication of the first electrical conduction structures 3 on the second bonding pads 41 in the subsequent steps. The materials and processing methods of the first passivation layer 103 and the second insulating layer 102 in this embodiment may be the same or similar. Preferably, the first passivation layer 103 of this embodiment is prepared by a spin coating method, so as to ensure that the first passivation layer 103 is flat and uniform.

S5, as shown in fig. 12, the first adhesive glue layer 104 is coated on the front surface of the substrate 1, and the first carrier sheet 105 is bonded on the first adhesive glue layer 104 through a temporary bonding process.

In the embodiment, the front structure of the substrate 1 is protected by the first temporary bonding technology, and the substrate 1 is supported for back processing, because the first passivation layer 103 is relatively flat, the thinnest thickness required by the process structure can be achieved by the thickness of the coated temporary bonding glue, which has positive significance for the subsequent process of depositing inorganic insulating layers such as silicon dioxide and the like on the back of the substrate 1 and in the wire through hole 6, the thicker the thickness of the temporary bonding glue is, the larger the stress change of the inorganic insulating layer during deposition is, the larger the risk of cracks on the inorganic insulating layer is, and the function failure of the inorganic insulating layer can be caused by the cracks.

Further, the material of the first carrier sheet 105 may be glass, silicon, metal or plastic, in this embodiment, glass is preferably used as the carrier sheet, a layer of photosensitive material is coated on the inner surface of the glass by utilizing the light transmission property of the glass, and finally the glass is removed by a laser photolysis bonding process.

S6, as shown in fig. 13, the back surface of the substrate 1 is thinned, the through holes 61 are formed in the back surface of the substrate 1 at positions corresponding to the second pads 41, the third insulating layers 106 are disposed in the through holes 61 and the back surface of the substrate 1, and the third insulating layers 106 and the first insulating layers 101 at the bottoms of the through holes 61 are removed to expose the second pads 41 at the bottoms of the through holes 61.

In this embodiment, the process of thinning the back surface of the substrate 1 may be one or two of grinding, dry etching and wet etching, in this embodiment, grinding and dry etching are preferred, the grinding removes the excess silicon, and the dry etching removes the stress strain layer generated by grinding. The opening of the through hole 61 of the present embodiment faces the back surface of the substrate 1, and the through hole 61 may be a straight hole or an inclined hole, and the present embodiment preferably uses a straight hole perpendicular to the substrate 1 to further shorten the interconnection pitch of the front surface and the back surface. The through hole 61 may be formed in various ways, such as laser drilling, wet etching, dry etching, and the like, and the dry etching is preferably used in this embodiment.

In this embodiment, the third insulating layer 106 may be formed by a passivation paste spraying, dry film or chemical vapor deposition, and preferably, a chemical vapor deposition process is used to deposit a layer of silicon oxide to cover the back surface of the substrate 1 and the through hole 61. In this embodiment, the silicon oxide at the bottom of the through hole 61 is removed by photolithography and development or chemical etching, so that the second pad 41 is exposed. Of course, in other embodiments, when the substrate 1 is made of an insulating material, the third insulating layer 106 may not be additionally formed.

In this embodiment, the insulating layer is preferably a dielectric layer with excellent performance, such as polyimide, and the baking curing temperature of the dielectric layer generally exceeds 230 ℃, so when the electrically conductive structure is a solder ball, since the temperature resistant to the solder ball is generally about 210 ℃, if the dielectric layer is baked for a long time, an intermetallic compound is easily formed between the solder ball and the lower layer, the soldering temperature of the intermetallic compound far exceeds the temperature that the package can bear, and the chip will be scrapped in severe cases, so the solder ball manufacturing step cannot be in front of the insulating layer, which is also the reason why two temporary bonding steps are required in this embodiment.

S7, as shown in fig. 14, a second metal redistribution layer 7 is formed on the third insulating layer 106 in the through hole 61 or in the through hole 61 and the back surface of the substrate 1, the electrical property of the second pad 41 is led out to the back surface of the substrate 1 through the second metal redistribution layer 7, the second metal redistribution layer 7 includes a third pad 71 formed on the back surface of the substrate 1, a second passivation layer 107 is formed on the second metal redistribution layer 7, a fourth reserved opening is formed on the second passivation layer 107, the fourth reserved opening exposes the third pad 71, and a second electrical lead-out structure 5 is formed on the third pad 71 in the fourth reserved opening.

In this embodiment, the through hole 61 may be filled with a conductive material completely or only a part of the through hole 61 (for example, only the sidewall and the bottom of the through hole 61 are covered) by filling a hole by electroplating or filling a conductive adhesive, so as to form the conductive through hole 6 that connects the front surface and the back surface of the substrate 1. In this embodiment, the through hole 61 is preferably completely filled with a conductive metal, which may be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, and gold, and is preferably titanium or copper.

Further, the second metal redistribution layer 7 of the present embodiment includes four third pads 71, two of the third pads 71 correspond to the two conductive vias 6, and the other two third pads 71 are located in the lower region of the back surface of the chip 2. The fourth reserved openings are also four and correspond to the positions of the four third bonding pads 71 respectively, so as to expose each third bonding pad 71, and the second electrical lead-out structure 5 can be conveniently manufactured on the third bonding pad 71.

The second electrical conduction structure 5 may be a solder ball, a metal bump, a conductive adhesive, and the like, in this embodiment, the second electrical conduction structure 5 is preferably a metal bump, and the metal bump may be manufactured by electroplating or electroplating and reflow processes. The material of the metal bump may be one or more of copper, nickel, palladium, gold, tin and silver, or one or more of copper, nickel, tin and silver, and in this embodiment, copper, nickel and gold are preferably used.

The material of the second metal redistribution lines 7 may be one or two of copper, nickel, a target, and gold, and the method of forming the second metal redistribution lines 7 may be one or two of electroplating, electroless plating, vacuum evaporation, and physical vapor deposition.

S8, as shown in fig. 15, the second adhesive glue layer 108 is coated on the back surface of the substrate 1, and the second carrier sheet 109 is bonded on the second adhesive glue layer 108 through a temporary bonding process.

In the step, the second temporary bonding technology is used for protecting the back structure of the substrate 1 and supporting the substrate 1 for front processing, so that the first electrical derivation structure 3 can be conveniently manufactured on the front surface of the substrate 1.

S9, as shown in fig. 16, the first carrier sheet 105 is removed by a bonding-breaking technique, the first adhesive layer 104 is cleaned, and the first electrical lead-out structure 3 is fabricated on the second pad 41 in the third opening 1031 on the front surface of the substrate 1.

In this embodiment, the first electrical lead-out structure 3 may be a solder ball, a metal bump, a conductive adhesive, and the like, and the solder ball is preferably used in this embodiment. Through the arrangement of the first electrical conduction structure 3, an external chip or a printed circuit board can be electrically connected with the chip 2 embedded in the substrate 1 through the first electrical conduction structure 3 on the front surface of the substrate 1 and the second electrical conduction structure 5 on the back surface of the substrate 1, so that the specific function required to be realized in three-dimensional packaging is realized.

S10, as shown in fig. 17, the second carrier sheet 109 is removed by a bonding-breaking technique, and the second adhesive layer 108 is cleaned off to obtain a final chip package structure.

The debonding technique in step S9 and step S10 may be mechanical debonding, thermal debonding, laser debonding, ultraviolet debonding, and the like, and the laser debonding technique is preferably used in this embodiment.

The embodiment can effectively achieve the advantages of reducing the packaging area, reducing the interconnection pitch, reducing the loss and the like; the thickness of the temporary bonding adhesive layer can be controlled, the process stress is controlled, and the deposition quality of dielectric layers such as silicon dioxide is improved; the influence of high-temperature processing procedure on the electric conduction structure can be avoided, the welding quality is improved, meanwhile, all operations of the embodiment are only carried out on the substrate and the bearing sheet, the technology is mature, the high-density interconnection structure is suitable for high-density interconnection, and the miniaturization and the light and thin of the packaging structure are facilitated.

In the embodiment, the influence on the first electrical lead-out structure 3 caused by the high temperature of the dielectric layer on the back surface of the substrate 1 in the curing process is avoided through the two temporary bonding processes, which is beneficial to the subsequent welding process. The chip packaging method is feasible in technology, lower in process risk and suitable for mass production.

It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.

Claims

1. The chip packaging structure is characterized by comprising a substrate (1), wherein the front surface of the substrate (1) is provided with at least one groove (11), at least one chip (2) is attached in the groove (11), the front surface of the substrate (1) is also provided with a first electrical property leading-out structure (3), and the electrical property of the chip (2) is led to the first electrical property leading-out structure (3) through a first metal rewiring (4); the back of base plate (1) is equipped with second electrical property and derives structure (5), base plate (1) still is equipped with and runs through its front and conductive through-hole (6) at the back, the electrical property of chip (2) passes through first metal rewiring (4) and conductive through-hole (6) are drawn forth extremely the back of base plate (1) second electrical property derives structure (5), just first electrical property is derived structure (3) and second electrical property is derived structure (5) branch and is located the both ends of conductive through-hole (6), conductive through-hole (6) perpendicular to base plate (1) or conductive through-hole (6) slope sets up, first electrical property is derived structure (3) and second electrical property is derived structure (5) and is located directly over and directly under conductive through-hole (6) respectively.

2. The chip package structure according to claim 1, wherein the first electrical lead-out structure (3) is one of a solder ball, a metal bump and a conductive adhesive; the second electrical conduction structure (5) is one of a solder ball, a metal bump and conductive adhesive.

3. The chip package structure according to claim 2, wherein the first electrical lead-out structure (3) is a solder ball, and the second electrical lead-out structure (5) is a metal bump; or, the first electrical lead-out structure (3) is a metal bump, and the second electrical lead-out structure (5) is a solder ball.

4. The chip package structure according to claim 2, wherein an end surface of the metal bump away from the substrate (1) is provided with a groove-shaped holding structure.

5. The chip packaging structure according to any one of claims 1-4, wherein when two adjacent chip packaging structures are stacked, the chips (2) in the two chip packaging structures are electrically connected in a face-to-face, face-to-back or back-to-back manner.

6. The chip packaging structure according to any one of claims 1-4, wherein the front surface of the substrate (1) is provided with one of the grooves (11), and two of the chips (2) are attached in the groove (11); or the front surface of the substrate (1) is provided with two grooves (11), and one chip (2) is attached to each groove (11).

7. Chip package according to claim 1, characterized in that the surface of the chip (2) has first pads (21), the first metal redistribution line (4) comprises a second pad (41) positioned above the front surface of the chip (2) and a second pad (41) positioned at one end of the conductive through hole (6) facing the front surface of the substrate (1), the electrical properties of the first bonding pad (21) are led to the second bonding pad (41) through the first metal redistribution lines (4), insulating layers are arranged between the first metal rewiring (4) and the chip (2) and the substrate (1) and between the chip (2) and the side wall of the groove (11), the first metal rewiring (4) is coated with a first passivation layer (103), the first electrical lead-out structure (3) is arranged on the second bonding pad (41) in a third reserved opening (1031) on the first passivation layer (103); the utility model discloses a chip packaging structure, including base plate (1), base plate (1) back is equipped with the insulating layer, be equipped with second metal rewiring (7) on the insulating layer at base plate (1) back, second metal rewiring (7) are including being located third pad (71) of chip (2) back below and being located electrically conductive through-hole (6) orientation third pad (71) of the one end at base plate (1) back, the outer cladding of second metal rewiring (7) has second passivation layer (107), second electrical property derivation structure (5) set up in the fourth reservation opening on second passivation layer (107) on third pad (71).

8. The chip packaging structure according to claim 1, wherein the sidewalls and bottom of the conductive via (6) are covered with a conductive metal; or the conductive through hole (6) is filled with conductive metal or conductive adhesive.

9. The chip packaging structure according to claim 1, wherein an upper opening of the groove (11) is not smaller than a bottom opening of the groove (11), and a vertical cross-sectional shape of the groove (11) is rectangular or trapezoidal.