CN115513182A - Semiconductor packaging structure and preparation method thereof - Google Patents

Semiconductor packaging structure and preparation method thereof Download PDF

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Publication number
CN115513182A
CN115513182A CN202211168023.4A CN202211168023A CN115513182A CN 115513182 A CN115513182 A CN 115513182A CN 202211168023 A CN202211168023 A CN 202211168023A CN 115513182 A CN115513182 A CN 115513182A
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China
Prior art keywords
silicon
layer
semiconductor
semiconductor group
conductive
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CN202211168023.4A
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Inventor
颜国秋
上官昌平
查晓刚
王建彬
付海涛
杜玲玲
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Shanghai Meadville Science and Technology Co Ltd
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Shanghai Meadville Science and Technology Co Ltd
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Priority to CN202211168023.4A priority Critical patent/CN115513182A/en
Publication of CN115513182A publication Critical patent/CN115513182A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

The invention provides a semiconductor packaging structure and a preparation method thereof, wherein the semiconductor packaging structure comprises: the semiconductor device comprises a carrier plate, a first circuit layer, a second circuit layer, a first rewiring layer, a silicon intermediate layer, a first semiconductor group and a second semiconductor group. The invention connects the chips in the first semiconductor group through the silicon intermediate layer, and reduces the transmission distance between the chips in the horizontal direction, thereby improving the chip density which can be realized in the semiconductor packaging structure and improving the transmission speed between the chips in the horizontal direction; meanwhile, the traditional connecting carrier plate is replaced by a structure with an embedded chip and a rewiring layer, so that the thickness of the device is not increased due to the arrangement of the silicon intermediate layer; in addition, the chip modules with different process technology requirements are granulated and independently prepared in the first semiconductor group and the second semiconductor group, so that the preparation cost, the design cost and the design difficulty of the semiconductor packaging structure are reduced, and the reuse flexibility and the preparation efficiency of the chip modules are improved.

Description

Semiconductor packaging structure and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor integrated circuit preparation, and particularly relates to a semiconductor packaging structure and a preparation method thereof.
Background
Currently, in order to pursue high integration, the mainstream system-level chip is manufactured by a plurality of computing units or chips in charge of different types of tasks on the same wafer in a photoetching mode, and all units are comprehensively promoted by using an advanced process.
In the conventional multi-chip heterogeneous package manner, as shown in fig. 1, the chips are usually interconnected by an internal circuit of the carrier and an RDL (redistribution layer). The problems of the interconnection mode are that conducting lines among chips are complex, line spacing is long, packaging thickness is high, electric signal delay and attenuation are large, and transmission efficiency is low.
The system-level chip package continuously integrates more functional units and larger on-chip storage, so that the number of transistors of the chip is increased suddenly, the area of the chip is increased sharply, the yield of the chip is reduced, the market demand of the chip on the small-size portable chip is reduced, the design difficulty is increased, and the modularized design and the updating iteration of subsequent products are not facilitated; in addition, chips integrating different process technologies and performance requirements are integrally prepared on a wafer by using a uniform process, so that the design cost and the preparation cost of the chips are greatly increased.
It should be noted that the above description of the technical background is only for the sake of clarity and complete description of the technical solutions of the present application and for the understanding of the skilled person, and the technical solutions are not considered to be known to the skilled person merely because they are described in the background section of the present application.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a semiconductor package structure and a method for manufacturing the same, which are used to solve the problems of long inter-chip transmission distance and complex manufacturing of system on chip in the semiconductor package structure in the prior art.
In order to achieve the above object, the present invention provides a semiconductor package structure, including: the device comprises a carrier plate, a first circuit layer, a second circuit layer, a first rewiring layer, a silicon intermediate layer, a first semiconductor group and a second semiconductor group;
the carrier plate comprises a first plate surface and a second plate surface which are oppositely arranged, a through groove penetrating through the first plate surface and the second plate surface is formed in the carrier plate, and the second semiconductor group is embedded in the through groove; the first circuit layer is formed on the first surface of the carrier plate, the second circuit layer is formed on the second surface of the carrier plate, the first circuit layer and the second circuit layer are effectively and electrically connected through a conductive hole penetrating through the carrier plate, and a solder ball is formed on the second circuit layer;
the first redistribution layer comprises a first wiring surface and a second wiring surface which are opposite, the second wiring surface of the first redistribution layer is arranged on the first board surface of the carrier board through the first circuit layer, and the second wiring surface of the first redistribution layer is effectively and electrically connected with the second semiconductor group through the first circuit layer;
the silicon medium layer comprises a first medium interface and a second medium interface which are arranged oppositely, a conductive silicon through hole penetrating through the silicon medium layer is arranged in the silicon medium layer, the second medium surface of the silicon medium layer is arranged on the first wiring surface of the first rewiring layer, the conductive silicon through hole is effectively and electrically connected with the first rewiring layer, and the first semiconductor group is arranged on the first medium interface of the silicon medium layer and is effectively and electrically connected with the conductive silicon through hole.
Optionally, the silicon interposer includes multiple layers of silicon wafers, the multiple layers of silicon wafers are formed by pressing, and adjacent silicon wafers in the multiple layers of silicon wafers are connected through the conductive through silicon vias and the metal bumps.
Optionally, the semiconductor package structure further includes a first solder array, a second solder array, and a third solder array, the conductive through-silicon-vias of the silicon interposer are effectively electrically connected to the first semiconductor group through the first solder array, the first wiring surface of the first redistribution layer is effectively electrically connected to the silicon interposer through the second solder array, and the solder balls formed by the second wiring layer constitute the third solder array.
Optionally, all line widths, line pitches, apertures, and metal bump pitches in the semiconductor package structure are gradually reduced from the third solder array to the first solder array.
Optionally, the first semiconductor group includes one or more chips or/and components of a capacitor, an inductor, a resistor, a transistor switch, a millimeter wave antenna, a central processing unit, a graphics processing unit, a power management unit, a dynamic random access memory, a flash memory, and a filter, the number of the chips or/and components is greater than 1, and a transmission channel is formed between the chips or/and the components through the silicon intermediate layer.
Optionally, each chip in the first semiconductor group is a bare chip die fabricated on a single wafer, and different die dies are respectively prepared by different preset processes.
The invention also provides a preparation method of the semiconductor packaging structure, which comprises the following steps:
providing a silicon wafer, wherein the silicon wafer comprises a first silicon surface and a second silicon surface which are oppositely arranged; arranging a plurality of conductive silicon through holes on the first silicon surface, and filling a metal layer in the conductive silicon through holes until the conductive silicon through holes are completely filled;
arranging a first solder array on the first silicon surface, arranging a first semiconductor group on one surface of the first solder array, which is far away from the first silicon surface, wherein the first semiconductor group is effectively and electrically connected with the first silicon surface through the first solder array; removing the silicon chip material of the second silicon surface until the metal layer is exposed, so as to form a silicon intermediate layer, wherein the first silicon surface is a first intermediate interface of the silicon intermediate layer, and the second silicon surface is a second intermediate interface of the silicon intermediate layer;
providing a carrier plate, wherein the carrier plate comprises a first plate surface and a second plate surface, and a through groove and a conductive hole are formed in the carrier plate, so that the through groove and the conductive hole penetrate through the first plate surface and the second plate surface; a second semiconductor group is arranged in the through groove, the second semiconductor group comprises an active surface and an external junction surface, and the external junction surface is flush with the first plate surface;
arranging a first circuit layer on the first board surface, arranging a second circuit layer on the second board surface, and forming effective electric connection between the active surface of the second semiconductor group and the second circuit layer; arranging a first redistribution layer on the first circuit layer of the first board surface, wherein the first redistribution layer comprises a first wiring surface and a second wiring surface which are oppositely arranged, and the second wiring surface is effectively and electrically connected with the external connection surface of the second semiconductor group through the first circuit layer; arranging a second solder array on the first wiring surface of the first redistribution layer;
disposing the silicon interposer on a first routing surface of the first redistribution layer, the first semiconductor group and the second semiconductor group forming effective electrical connections through the silicon interposer, the first redistribution layer, and the first circuit layer;
and arranging a third solder array on the second surface of the carrier plate, so that the third solder array is effectively and electrically connected with the active surface of the second semiconductor group through the second circuit layer.
Optionally, a plurality of silicon chips are provided, the silicon chips are connected through the through silicon vias and the metal bumps, and the silicon chips form the silicon interposer by pressing.
Optionally, the first semiconductor group is composed by fabricating different die core grains or/and components on different wafers, different core grains or/and components are fabricated by different fabrication processes, and transmission channels are formed between the core grains or/and components through the silicon intermediate layer.
Optionally, all line widths, line distances, apertures, and metal bump distances in the preparation method are gradually reduced from the third solder array to the first solder array.
As described above, the semiconductor package structure and the method for manufacturing the same of the present invention have the following advantages:
the invention connects the chips in the first semiconductor group through the silicon intermediate layer, and reduces the transmission distance between the chips in the horizontal direction, thereby improving the chip density which can be realized in the semiconductor packaging structure and improving the transmission speed between the chips in the horizontal direction;
the invention replaces the traditional connecting carrier plate by the structure of the embedded chip and the rewiring layer, so that the thickness of the device is not increased by the arrangement of the silicon intermediate layer;
the chip module core with different process technology requirements is granulated and independently prepared in the first semiconductor group and the second semiconductor group, so that the preparation cost, the design cost and the design difficulty of the semiconductor packaging structure are reduced, and the reuse flexibility and the preparation efficiency of the chip module are improved.
Drawings
Fig. 1 is a schematic diagram of a semiconductor package according to the prior art.
Fig. 2 is a schematic structural diagram of step 1 in the second embodiment of the present invention.
Fig. 3 is a schematic structural diagram of step 2 in the second embodiment of the present invention.
Fig. 4 is a schematic structural diagram illustrating the second package layer in step 2, which is optional in the second embodiment of the present invention.
Fig. 5 is a schematic structural diagram of step 3 in the second embodiment of the present invention.
Fig. 6 shows a schematic structural diagram of the first resist layer disposed in step 4 in the second embodiment of the present invention. 1
Fig. 7 is a schematic structural diagram showing the removal of the first resist layer in step 4 in the second embodiment of the present invention.
Fig. 8 is a schematic structural diagram showing the arrangement of the first redistribution layer and the second routing layer in step 4 in the second embodiment of the present invention.
Fig. 9 shows a schematic structural view of the second resist layer and the third resist layer removed in step 4 in the second embodiment of the present invention.
Fig. 10 is a schematic structural diagram of step 5 in the second embodiment of the present invention.
Fig. 11 is a schematic structural diagram illustrating the arrangement of the first encapsulation layer in step 5, which is optional in the second embodiment of the present invention.
Fig. 12 is a schematic structural diagram illustrating the third encapsulating layer disposed in step 5 according to the second embodiment of the present invention.
Fig. 13 is a schematic structural diagram showing the third solder array arranged in step 6 in the second embodiment of the present invention.
Description of the element reference numerals
11. Connecting the core layers; 21. a base core layer; 30. an embedded chipset; 40. an upper chipset; 50. an existing solder ball; 60. an existing dielectric layer; 70. an existing conductive layer; 80. an existing solder mask layer;
101. an organic core layer; 102. a carrier plate through hole; 103. a second dielectric layer; 104. a solder resist layer; 105. a second conductive layer; 106. a second semiconductor group; 107. a third solder array;
2011. a first dielectric layer; 2012. a first conductive layer; 2013. a third dielectric layer; 2014. a third conductive layer; 2015. a first pre-plating layer; 2016. a third pre-plating layer; 202. a second solder array; 203. a first encapsulation layer; 204. a first resist layer; 205. a third resist layer;
301. a silicon interposer; 3011. a silicon wafer; 3012. a conductive through-silicon via; 302. a first solder array; 303. a second encapsulation layer; 304. a first semiconductor group; 305. a third encapsulation layer; 306. a second resist layer; 307. and (3) a second pre-plating layer.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As used herein, the drawings are not intended to be limiting, but are to be construed in an illustrative and exemplary manner. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures.
In the context of this application, a structure described as having a first feature "on" a second feature may encompass embodiments in which the first and second features are formed in direct contact, and may also encompass embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
The first embodiment is as follows:
in the prior art, as shown in fig. 1, the chips in the horizontal direction and the chips in the vertical direction are generally electrically connected by connecting a carrier board and RDLs (redistribution layers) prepared by growing on both sides of the carrier board. The substrate carrier plate is used for arranging the embedded chip group 30, the RDLs are required to be arranged on two sides of the middle connecting carrier plate and are used for connecting the embedded chip group 30 and the upper chip group 40 in the vertical direction, the RDLs of the middle connecting carrier plate are electrically connected with the embedded chip group 30 and the upper chip group 40 of the substrate carrier plate through solder balls, and the RDLs are required to be arranged at the bottom of the substrate carrier plate and are provided with the existing solder mask layer 80 and the existing solder balls 50 to be electrically connected with an external system; the RDLs include the existing dielectric layer 60 and the existing conductive layer 70, which are stacked together, and the chips in the upper chipset 40 in the horizontal direction are electrically connected through the RDL connected to the upper portion of the carrier board; the connection carrier includes a connection core layer 11, and the substrate carrier includes a substrate core layer 21.
In the scheme, because the RDL usually adopts an organic matter as a dielectric layer structure, the thermal expansion coefficient of the RDL is higher, the RDL is easily influenced by temperature in the processing process, so that the warping problem is generated, meanwhile, the shape characteristics of the formed holes, lines and the like are easily influenced by chemical substances involved in the processing process, so that the surface roughness of the RDL is higher, the line width and line distance density which can be reached by the RDL are limited by the problems, the distance of a transmission channel between chips in the horizontal direction is longer, and the transmission speed is slower; in addition, the chip is connected in the vertical direction by adopting a structure combining the carrier board and the RDL, the formation of the carrier board needs the core layer for support, and the existence of the connection core layer 11 connected with the carrier board can cause the package structure in the prior art to need higher thickness to realize the electrical connection in the vertical direction.
As shown in fig. 13, the present invention provides a semiconductor package structure, comprising: a carrier board, a first circuit layer, a second circuit layer, a first redistribution layer, a silicon interposer 301, a first semiconductor group 304, and a second semiconductor group 106;
the carrier plate comprises a first plate surface and a second plate surface which are oppositely arranged, a through groove penetrating through the first plate surface and the second plate surface is formed in the carrier plate, and the second semiconductor group 106 is embedded in the through groove; a first circuit layer is formed on the first surface of the carrier plate, a second circuit layer is formed on the second surface of the carrier plate, the first circuit layer and the second circuit layer are effectively and electrically connected through a conductive hole penetrating through the carrier plate, and a solder ball is formed on the second circuit layer;
the first redistribution layer comprises a first wiring surface and a second wiring surface which are opposite, the second wiring surface of the first redistribution layer is arranged on the first board surface of the carrier board through the first circuit layer, and the second wiring surface of the first redistribution layer is effectively and electrically connected with the second semiconductor group 106 through the first circuit layer;
the silicon interposer 301 includes a first intermediate interface and a second intermediate interface, which are disposed opposite to each other, a conductive through-silicon via 3012 is disposed in the silicon interposer 301 and penetrates through the silicon interposer 301, the second intermediate interface of the silicon interposer 301 is disposed on the first layout surface of the first redistribution layer, the conductive through-silicon via 3012 is electrically connected to the first redistribution layer, and the first semiconductor group 304 is disposed on the first intermediate interface of the silicon interposer 301 and electrically connected to the conductive through-silicon via 3012.
According to the invention, the silicon interposer 301 replaces an RDL structure to realize the electrical connection between chips in the horizontal direction, and as the silicon material has a lower thermal expansion coefficient and a high Young modulus, the silicon interposer 301 is less influenced by temperature in the processing process, so that in the same area, the silicon interposer 301 can realize a higher line width and line distance density than the RDL without generating an obvious warping problem, can realize a smaller packaging size under the setting of the same line density, and simultaneously improves the transmission speed between chips to realize a larger data bandwidth; compared with the organic material of RDL, the silicon has more stable chemical property, the formed shape characteristic of the silicon is not easily influenced by the chemical substances involved in the processing process, and the lower surface roughness can be achieved; in addition, because a silicon dioxide layer with strong insulation property is easily formed on the surface of silicon, the electron mobility at the position of a non-conductive layer in the silicon intermediate layer 301 is greatly reduced, long-term current conduction can be carried out in a line width and line distance with smaller size without generating the problems of short circuit, open circuit and the like caused by electron migration, and compared with RDL, the packaging structure has stronger reliability; finally, in the invention, the electrical connection between the chips in the vertical direction can be realized directly through the matching structure of the RDL grown on the carrier plate of the embedded chip and the silicon interposer 301, because the RDL can be directly connected and conducted with the embedded chip, the electric signal of the embedded chip is not required to be led out from the carrier plate to the connecting carrier plate through a solder ball in the prior art, and the characteristic that the line density of the silicon interposer 301 can be higher is utilized, the structure can be thinner, the occupied space is smaller, the packaging structure is favorable for being used in small-size portable products, and higher transmission speed can be realized in the vertical direction so as to meet the application field requirements of ultra-large data throughput such as cloud infrastructure, 5G, automatic driving, artificial intelligence and the like.
By way of example, the silicon interposer 301 is less than 150 microns thick. Specifically, the size of the silicon interposer 301 can be determined according to the number and size of chips to be connected.
By way of example, the conductive through-silicon vias 3012 have a pore size of 10-50 microns. Specifically, the size and number of the conductive through-silicon vias 3012 may be determined according to the number and size of chips to be connected.
By way of example, silicon interposer 301 includes multiple layers of silicon dice 3011, where multiple layers of silicon dice 3011 are pressed to form silicon interposer 301, and adjacent silicon dice 3011 in multiple layers of silicon dice 3011 are connected by conductive through-silicon vias 3012 and metal bumps. Specifically, in the present invention, the silicon interposer 301 only needs one layer of circuit to achieve multi-chip communication, and the number of layers of the silicon sheet 3011 can be set according to the number of connections required between chips in the package structure.
Optionally, an insulating film is disposed between the metal layer in the conductive through-silicon via 3012 and the silicon wafer 3011. Preferably, the material of the insulating film is silicon dioxide. The insulating film is used as an insulating layer, so that complete electrical isolation can be performed on the silicon wafer 3011, and meanwhile, the silicon dioxide and the silicon have good binding force, and the insulating film has the characteristics of low stress, high breakdown voltage and the like, and can improve the performance reliability of devices of the semiconductor packaging structure.
As an example, the semiconductor package structure further includes a first solder array 302, a second solder array 202, and a third solder array 107, the conductive through-silicon-vias 3012 of the silicon interposer 301 are electrically connected to the first semiconductor group 304 via the first solder array 302, the first routing surface of the first redistribution layer is electrically connected to the silicon interposer 301 via the second solder array 202, and the solder balls formed by the second routing layer form the third solder array 107.
Specifically, a first packaging layer 203 is arranged between a second middle interface of the silicon interposer 301 and a first wiring surface of the first redistribution layer, and the first packaging layer 203 fills the gap of the second solder array 202, so as to prevent the second middle interface and the first wiring surface from being affected by the outside, such as oxidation and moisture, and reduce the possibility of short circuit between solder balls in the first solder array 302, and improve the reliability of the semiconductor packaging structure; the second packaging layer 303 is filled between the gaps of the first solder array 302, and the surface between the first semiconductor group 304 and the silicon interposer 301 is protected similarly as described above; the third packaging layer 305 is disposed on all the peripheral surfaces of the first redistribution layer, the silicon interposer 301, the first semiconductor group 304 and the connection structure therebetween, and provides similar protection for the entire package structure.
Specifically, the filling layer material includes, but is not limited to, epoxy resin, high performance phenolic resin, silicon powder, and halogen.
By way of example, all line widths, line pitches, apertures, and metal bump pitches in the semiconductor package structure taper from the third solder array 107 toward the first solder array 302. Specifically, n conductive layers are arranged in the first redistribution layer, n is an integer larger than 1, the number of the conductive layers increases gradually from the third solder array 107 to the 1 st layer in the direction of the first solder array 302, and the line width, the line pitch, the through hole aperture and the through hole pitch of the conductive layer of the nth layer are all smaller than or equal to the corresponding size of the (n-1) th layer.
Optionally, the semiconductor package structure may also be configured as a fan-in package structure, and the corresponding line width and line distance may be adjusted according to requirements.
As an example, the first semiconductor group 304 includes one or more chips or/and components of a capacitor, an inductor, a resistor, a transistor switch, a millimeter wave antenna, a central processing unit, a graphics processor, a power management unit, a dynamic random access memory, a flash memory, and a filter, the number of the chips or/and components is greater than 1, and a transmission channel is formed between the chips or/and components through the silicon interposer 301. According to the invention, through the arrangement of the silicon interposer 301, the compatibility of different types of chips and components can be realized, and the system-level chip connection can be realized.
As an example, each chip in the first semiconductor group 304 is a bare chip die fabricated on a single wafer, and different die are respectively prepared by different preset processes. Specifically, modules such as logic computation units, which rely on advanced processes to achieve a greater number of I/O ports (I/O ports) and a smaller line width/pitch (e.g., 7/7nm process), may be fabricated on different wafers than other modules that do not require high processing requirements (e.g., 28/28nm process). According to the invention, the chip cores in the first semiconductor group 304 are granulated, the core particles which need different preparation process procedures are manufactured by using the discrete wafers, and then the core particles are connected and packaged through the semiconductor packaging structure, so that the core particle designs of different procedures can be standardized and used for different system-level chip designs, thereby reducing the design cost and the design difficulty, and simultaneously, the whole preparation time is shortened and the preparation efficiency is improved because the core particles can be prepared separately. Specifically, the second semiconductor group 106 may also use the same arrangement as described above.
Specifically, the first solder arrays 302 on the bottom of the chips and components in the first semiconductor package 304 for connection are located at the same level, and the bottom surfaces of the first solder arrays 302 are flush with the first intermediate surface of the silicon interposer 301.
As an example, the first circuit layer includes a first dielectric layer 2011 and a first conductive layer 2012 which are stacked on each other, and a second dielectric layer 103 and a second conductive layer 105 which are stacked on each other, a first preplating layer 2015 is arranged between the first dielectric layer 2011 and the first conductive layer 2012, and a second preplating layer 307 is arranged between the second dielectric layer 103 and the second conductive layer 105; the first rewiring layer comprises a third dielectric layer 2013 and a third conductive layer 2014 which are mutually laminated, and a third pre-plating layer 2016 is arranged between the third dielectric layer 2013 and the third conductive layer 2014.
Specifically, the carrier includes an organic core layer 101 and a carrier through hole 102, the carrier through hole 102 penetrates through the organic core layer 101, so that the first circuit layer and the second circuit layer form effective electrical connection through the organic core layer 101, and a transmission path in a circuit of the external semiconductor package structure, which does not need to be processed by the second semiconductor group 106, directly forms effective electrical connection with the first circuit layer, the first redistribution layer, the silicon interposer 301, and the first semiconductor group 304 through the carrier through hole 102, wherein the organic core layer 101 has a supporting effect on the first circuit layer and the second circuit layer.
Optionally, the solder resist layer 104 is disposed between the solder balls of the third solder array 107 to reduce the influence of oxidation, moisture, and the like on the second board surface due to external influence, and at the same time, reduce the possibility of short circuit between the solder balls in the third solder array 107, and improve the reliability of the semiconductor package structure. Specifically, the solder mask 104 material includes, but is not limited to, acrylic, epoxy, silicone, and the type of solder mask 104 prepared includes dry film or wet film.
Example two:
the invention provides a preparation method of a semiconductor packaging structure, which comprises the following steps:
step 1: providing a silicon wafer 3011, wherein the silicon wafer 3011 comprises a first silicon surface and a second silicon surface which are arranged oppositely; arranging a plurality of conductive through silicon vias 3012 on the first silicon surface, and filling a metal layer in the conductive through silicon vias 3012 until the conductive through silicon vias 3012 are completely filled;
step 2: arranging a first solder array 302 on the first silicon surface, arranging a first semiconductor group 304 on the surface of the first solder array 302 far away from the first silicon surface, wherein the first semiconductor group 304 is effectively electrically connected with the first silicon surface through the first solder array 302; removing the material of the silicon wafer 3011 on the second silicon surface to expose the metal layer, so as to form the silicon interposer 301, where the first silicon surface is a first middle interface of the silicon interposer 301, and the second silicon surface is a second middle interface of the silicon interposer 301;
and step 3: providing a carrier plate, wherein the carrier plate comprises a first plate surface and a second plate surface, and a through groove and a conductive hole are arranged in the carrier plate so that the through groove and the conductive hole penetrate through the first plate surface and the second plate surface; a second semiconductor group 106 is arranged in the through groove, the second semiconductor group 106 comprises an active surface and an external junction surface, and the external junction surface is flush with the first plate surface;
and 4, step 4: arranging a first circuit layer on the first board surface, arranging a second circuit layer on the second board surface, and forming effective electric connection between the active surface of the second semiconductor group 106 and the second circuit layer; arranging a first redistribution layer on the first circuit layer of the first board surface, wherein the first redistribution layer comprises a first wiring surface and a second wiring surface which are oppositely arranged, and the second wiring surface is effectively and electrically connected with the external connection surface of the second semiconductor group 106 through the first circuit layer; arranging a second solder array 202 on the first wiring surface of the first redistribution layer;
and 5: arranging the silicon interposer 301 on the first wiring surface of the first redistribution layer, and effectively electrically connecting the first semiconductor group 304 and the second semiconductor group 106 through the silicon interposer 301, the first redistribution layer and the first wiring layer;
step 6: a third solder array 107 is disposed on the second surface of the carrier board, so that the third solder array 107 is electrically connected to the active surface of the second semiconductor group 106 through the second circuit layer.
The method for manufacturing the semiconductor package structure of the present invention will be described in detail with reference to the accompanying drawings, wherein it should be noted that the above sequence does not strictly represent the sequence of the method for manufacturing the semiconductor package structure protected by the present invention, and can be changed by those skilled in the art according to the actual manufacturing steps.
Firstly, as shown in fig. 2, step 1 is performed to provide a silicon wafer 3011, where the silicon wafer 3011 includes a first silicon surface and a second silicon surface that are oppositely disposed; a plurality of conductive through-silicon vias 3012 are disposed on the first silicon surface, and a metal layer is filled in the conductive through-silicon vias 3012 until the conductive through-silicon vias 3012 are completely filled.
Optionally, before the metal layer is disposed, an insulating film is formed in the conductive through-silicon via 3012. Preferably, the material of the insulating film is silicon dioxide. The insulating film is used as an insulating layer, so that complete electrical isolation can be performed on the silicon wafer 3011, and meanwhile, the silicon dioxide and the silicon have good binding force, and the insulating film has the characteristics of low stress, high breakdown voltage and the like, and can improve the performance reliability of devices of the semiconductor packaging structure.
By way of example, a plurality of silicon dice 3011 are provided, the plurality of silicon dice 3011 are connected to each other through conductive through-silicon vias 3012 and metal bumps, and the plurality of silicon dice 3011 are pressed to form the silicon interposer 301.
Alternatively, the metal layer material in the conductive through silicon via 3012 may be a conductive material such as copper, tungsten, polysilicon, or the like.
Then, as shown in fig. 2, step 2 is performed to dispose a first solder array 302 on the first silicon surface, and dispose a first semiconductor group 304 on a surface of the first solder array 302 away from the first silicon surface, where the first semiconductor group 304 is electrically connected to the first silicon surface effectively through the first solder array 302; the silicon wafer 3011 material on the second silicon surface is removed to expose the metal layer, so as to form the silicon interposer 301, where the first silicon surface is the first middle interface of the silicon interposer 301, and the second silicon surface is the second middle interface of the silicon interposer 301. The invention utilizes the vertical interconnection of the conductive silicon through holes 3012, reduces the interconnection length between chips, reduces the transmission signal delay, reduces the parasitic capacitance and inductance, is beneficial to improving the bandwidth and realizes the miniaturization of high-speed communication and device integration.
Specifically, when a plurality of silicon dies 3011 are arranged to be pressed to form the silicon interposer 301, the exposed surface of the silicon die 3011 closest to the first solder array 302 is a first intermediate interface, and the exposed surface of the silicon die 3011 farthest from the first solder array 302 is a second intermediate interface.
As an example, the first semiconductor group 304 is composed by fabricating different die core grains or/and components on different wafers, the different core grains or/and components are fabricated by different fabrication processes, and transmission channels are formed between the core grains or/and components through the silicon interposer 301.
For example, after the silicon interposer 301 is formed, the second package layer 303 is filled between the gaps of the first solder array 302 to prevent the surface between the first semiconductor assembly 304 and the silicon interposer 301 from being affected by external influences, such as oxidation and moisture, and to reduce the possibility of short circuit between the solder balls in the first solder array 302, thereby improving the reliability of the semiconductor package structure. Optionally, the step of filling the second package layer 303 may also be performed in other steps after the silicon interposer 301 is formed according to requirements, and the second package layer 303 may also not only fill the gap of the first solder array 302, but also cover the surface of the first semiconductor group 304 and/or the silicon interposer 301, so as to serve as a package protection layer, thereby improving the preparation efficiency of the package layer and the simplification degree of the package structure, so as to reduce the gap that may be generated between the package structures, and reduce the package defect factor that may exist.
Next, as shown in fig. 4, step 3 is performed to provide a carrier plate, where the carrier plate includes a first plate surface and a second plate surface, and a through groove and a conductive hole are formed in the carrier plate, so that the through groove and the conductive hole penetrate through the first plate surface and the second plate surface; a second semiconductor group 106 is arranged in the through groove, and the second semiconductor group 106 comprises an active surface and an external junction surface which is flush with the first plate surface. According to the invention, the outer joint surface is flush with the first plate surface, so that transmission signals entering from the outside of the semiconductor packaging structure and transmission signals of the second semiconductor group 106 can be transmitted to the first semiconductor group 304 approximately synchronously, the accuracy of data transmission and processing is improved, and the RDL growth on the carrier plate is facilitated.
Specifically, the carrier further includes an organic core layer 101 and carrier through holes 102, the carrier through holes 102 penetrate through the organic core layer 101, the organic core layer 101 may be a glass fiber cloth resin coated copper clad laminate, and the resin includes, but is not limited to, epoxy resin, phenolic resin, and polyester resin.
Specifically, after the second semiconductor group 106 is provided, a filling layer is provided between the second semiconductor group 106 and the through-trench. Preferably, the filling layer material is an ABF material, which has good fluidity and heat dissipation, and facilitates the arrangement and heat dissipation of the second semiconductor group 106.
Then, as shown in fig. 5, step 4 is performed to dispose a first circuit layer on the first board surface, and a second circuit layer on the second board surface, so that the active surface of the second semiconductor group 106 is effectively electrically connected to the second circuit layer; arranging a first redistribution layer on the first circuit layer of the first board surface, wherein the first redistribution layer comprises a first wiring surface and a second wiring surface which are oppositely arranged, and the second wiring surface is effectively and electrically connected with the external connection surface of the second semiconductor group 106 through the first circuit layer; a second solder array 202 is disposed on the first wiring surface of the first redistribution layer.
Specifically, the carrier through hole 102 enables the first circuit layer and the second circuit layer to form effective electrical connection through the organic core layer 101, so that the circuit of the external semiconductor package structure is directly electrically connected with the first circuit layer, the first redistribution layer, the silicon interposer 301, and the first semiconductor group 304 through the carrier through hole 102 without passing through a transmission path of the second semiconductor group 106, wherein the organic core layer 101 supports the first circuit layer and the second circuit layer.
Specifically, the preparation steps of the first circuit layer are as follows: as shown in fig. 6, a first dielectric layer 2011 is disposed on a first plate surface of the carrier, a predetermined groove is disposed on the first dielectric layer 2011, a first pre-plating layer 2015 is disposed on the first dielectric layer 2011 and the surface of the groove, a first resist layer 204 is disposed on the first pre-plating layer 2015, the first resist layer 204 is patterned to expose the first pre-plating layer 2015 in the groove and the first pre-plating layers 2015 at other predetermined positions, a first conductive layer 2012 is disposed on the exposed surface of the first pre-plating layer 2015, the groove and the patterned gap of the first resist layer 204 at the predetermined positions are filled with the first conductive layer 2012, and the surface of the first conductive layer 2012 is flush with the surface of the first resist layer 204; next, as shown in fig. 7, the first resist layer 204 is removed.
Specifically, as shown in fig. 8 and 9, after the preparation of the first circuit layer is finished, the preparation steps are repeated, the third dielectric layer 2013, the groove, the third pre-plating layer 2016, the patterned third resist layer 205, and the third conductive layer 2014 are sequentially prepared on the surface of the first circuit layer, and then the third resist layer 205 is removed, so as to form the first redistribution layer. Optionally, multiple layers of preplating layers, conductive layers and dielectric layers can be manufactured according to requirements, and a first rewiring layer comprising multiple circuit layers is formed to meet the requirement of chip connection.
Specifically, as shown in fig. 8 and 9, the preparation method further includes disposing a second circuit layer on the second board surface of the carrier, the preparation steps of which are consistent with those of the first circuit layer, sequentially preparing a second dielectric layer 103, a groove, a second pre-plating layer 307, a patterned second resist layer 306, and a second conductive layer 105 on the second board surface of the carrier, and then removing the second resist layer 306, so as to form the second circuit layer.
Specifically, the materials of first conductive layer 2012, second conductive layer 105, and third conductive layer 2014 include, but are not limited to, electrolytic copper and rolled copper.
Preferably, the ductility of the materials of first conductive layer 2012, second conductive layer 105 and third conductive layer 2014 is greater than or equal to 22% and the thickness is 4-8 micrometers; the ratio of the copper plating thickness of the first conductive layer 2012, the second conductive layer 105 and the third conductive layer 2014 to the line width of the first circuit layer is 1:1.
specifically, the materials of the first dielectric layer 2011, the second dielectric layer 103 and the third dielectric layer 2013 include, but are not limited to, PI (polyimide), ABF (ajinomoto stacked film), and epoxy resin.
Specifically, the materials of the first resist layer 204, the second resist layer 306, and the third resist layer 205 include, but are not limited to, a polymer adhesive (such as acrylic).
Optionally, dry etching or wet etching is adopted when the anti-corrosion layer is removed; the dry etching used includes but is not limited to ion milling, reactive ion etching and plasma etching, and the etching gas in the dry etching includes but is not limited to one or any combination of more than one of argon, nitrogen and fluorine-based gas; etching gases in wet etching include, but are not limited to, gases containing OH - 、SO 4 2- 、CO 3 2- 、OH - 、H + Or a compound comprising H 2 O 2 A mixture of (a).
Preferably, the thickness of the first dielectric layer 2011, the thickness of the second dielectric layer 103 and the thickness of the third dielectric layer 2013 are 5-10 micrometers, the diameter of the grooves is 30-40 micrometers, and the distance between the grooves is 60-80 micrometers.
Preferably, the first pre-plating layer 2015, the second pre-plating layer 307 and the third pre-plating layer 2016 include a titanium layer and a copper layer, and in the preparation process, the titanium layer is formed on the surface of the groove and the dielectric layer, and then the copper layer is formed on the titanium layer.
Preferably, the thickness of the first pre-plating layer 2015, the second pre-plating layer 307 and the third pre-plating layer 2016 is 300-500 nm.
Next, as shown in fig. 10, step 5 is performed to dispose the silicon interposer 301 on the first wiring surface of the first redistribution layer, and the first semiconductor group 304 and the second semiconductor group 106 are effectively electrically connected through the silicon interposer 301, the first redistribution layer, and the first wiring layer.
Specifically, after step 5 is completed, a filling layer is disposed between the second middle interface of the silicon interposer 301 and the first wiring surface of the first redistribution layer, and the filling layer fills the gap of the second solder array 202, so as to prevent the second middle interface and the first wiring surface from being affected by external factors, such as oxidation and moisture, and reduce the possibility of short circuit between the solder balls in the first solder array 302, thereby improving the reliability of the semiconductor package structure.
Specifically, in the preparation process of the filling layer, the temperature of a baking link can be 120-150 ℃, the preheating temperature is below 80 ℃, and the temperature control is on the premise of not influencing the reliability of the packaging structure.
Alternatively, the filling method of the filling layer includes, but is not limited to, transfer molding, injection molding, and preforming techniques. Specifically, a "one" or "L" type operation direction is used during the filling process to avoid voids between the gaps and reduce the risk of device damage due to current concentration.
Then, as shown in fig. 13, step 6 is performed to dispose a third solder array 107 on the second surface of the carrier board, so that the third solder array 107 is electrically connected to the active surface of the second semiconductor group 106 through the second circuit layer.
Preferably, the solder material of first solder array 302, second solder array 202, and third solder array 107 is silver-tin alloy, which provides good electrical connection with good adhesion, wettability, and diffusivity of tin.
Optionally, after the third solder array 107 is disposed, the solder resist layer 104 is disposed between solder balls of the third solder array 107, so as to reduce the influence of oxidation, moisture and the like on the second board surface due to external influence, and at the same time, reduce the possibility of short circuit between solder balls in the third solder array 107, and improve the reliability of the semiconductor package structure. Specifically, the solder mask 104 material includes, but is not limited to, acrylic resin, epoxy resin, silicone resin, the preparation method includes, but is not limited to, vacuum lamination or coating, and the type of the solder mask 104 prepared includes dry film or wet film.
By way of example, all line widths, line pitches, apertures, and metal bump pitches in the fabrication process taper from the third solder array 107 toward the first solder array 302. The invention realizes the high-density I/O ports of the first semiconductor group 304 by the design that the line spacing is reduced from the third solder array 107 to the first solder array 302, thereby realizing better fan-out effect.
In summary, the semiconductor package structure and the manufacturing method thereof of the present invention can connect the chips in the first semiconductor group through the silicon interposer, and reduce the transmission distance between the chips in the horizontal direction, thereby improving the chip density achievable in the semiconductor package structure and increasing the transmission speed between the chips in the horizontal direction; meanwhile, the traditional connecting carrier plate is replaced by a structure with an embedded chip and a rewiring layer, so that the thickness of the device is not increased due to the arrangement of the silicon intermediate layer; in addition, the chip module cores with different process technological requirements are granulated and independently prepared in cooperation with the first semiconductor group and the second semiconductor group, so that the preparation cost, the design cost and the design difficulty of the semiconductor packaging structure are reduced, and the reuse flexibility and the preparation efficiency of the chip module are improved.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims (10)

1. A semiconductor package structure, comprising: the device comprises a carrier plate, a first circuit layer, a second circuit layer, a first rewiring layer, a silicon intermediate layer, a first semiconductor group and a second semiconductor group;
the carrier plate comprises a first plate surface and a second plate surface which are oppositely arranged, a through groove and a conductive hole which penetrate through the first plate surface and the second plate surface are formed in the carrier plate, and the second semiconductor group is embedded in the through groove; the first circuit layer is formed on the first board surface of the carrier board, the second circuit layer is formed on the second board surface of the carrier board, the first circuit layer and the second circuit layer are effectively and electrically connected through the conductive hole penetrating through the carrier board, and the second circuit layer is provided with a solder ball;
the first redistribution layer comprises a first wiring surface and a second wiring surface which are opposite, the second wiring surface of the first redistribution layer is arranged on the first board surface of the carrier board through the first circuit layer, and the second wiring surface of the first redistribution layer is effectively and electrically connected with the second semiconductor group through the first circuit layer;
the silicon medium layer comprises a first medium interface and a second medium interface which are arranged oppositely, a conductive silicon through hole penetrating through the silicon medium layer is arranged in the silicon medium layer, the second medium surface of the silicon medium layer is arranged on the first wiring surface of the first rewiring layer, the conductive silicon through hole is effectively and electrically connected with the first rewiring layer, and the first semiconductor group is arranged on the first medium interface of the silicon medium layer and is effectively and electrically connected with the conductive silicon through hole.
2. The semiconductor package structure of claim 1, wherein the silicon interposer comprises a plurality of silicon dies pressed to form the silicon interposer, and adjacent silicon dies in the plurality of silicon dies are connected by the conductive through silicon vias and the metal bumps.
3. The semiconductor package structure of claim 1, wherein the semiconductor package structure further comprises a first solder array, a second solder array, and a third solder array, wherein the conductive through-silicon-vias of the silicon interposer are in operative electrical connection with the first semiconductor group through the first solder array, wherein the first routing surface of the first redistribution layer is in operative electrical connection with the silicon interposer through the second solder array, and wherein the third solder array is composed of solder balls formed by the second routing layer.
4. The semiconductor package structure of claim 3, wherein all of the line width, line pitch, aperture, and metal bump pitch in the semiconductor package structure taper from the third solder array toward the first solder array.
5. The semiconductor package structure according to any one of claims 1 to 4, wherein the first semiconductor group comprises one or more chips or/and components selected from a group consisting of a capacitor, an inductor, a resistor, a transistor switch, a millimeter wave antenna, a central processing unit, a graphics processor, a power management unit, a dynamic random access memory, a flash memory, and a filter, the number of the chips or/and components is greater than 1, and a transmission channel is formed between the chips or/and the components through the silicon intermediate layer.
6. The semiconductor package structure of claim 5, wherein each chip in the first semiconductor group is a die core die fabricated on a single wafer, and different core dies are respectively prepared by different predetermined processes.
7. A preparation method of a semiconductor packaging structure is characterized by comprising the following steps:
providing a silicon wafer, wherein the silicon wafer comprises a first silicon surface and a second silicon surface which are oppositely arranged; arranging a plurality of conductive silicon through holes on the first silicon surface, and filling a metal layer in the conductive silicon through holes until the conductive silicon through holes are completely filled;
arranging a first solder array on the first silicon surface, arranging a first semiconductor group on one surface of the first solder array, which is far away from the first silicon surface, wherein the first semiconductor group is effectively and electrically connected with the first silicon surface through the first solder array; removing the silicon chip material of the second silicon surface until the metal layer is exposed, so as to form a silicon intermediate layer, wherein the first silicon surface is a first intermediate interface of the silicon intermediate layer, and the second silicon surface is a second intermediate interface of the silicon intermediate layer;
providing a carrier plate, wherein the carrier plate comprises a first plate surface and a second plate surface, and a through groove and a conductive hole are formed in the carrier plate, so that the through groove and the conductive hole penetrate through the first plate surface and the second plate surface; a second semiconductor group is arranged in the through groove, the second semiconductor group comprises an active surface and an external junction surface, and the external junction surface is flush with the first plate surface;
arranging a first circuit layer on the first board surface, arranging a second circuit layer on the second board surface, and forming effective electric connection between the active surface of the second semiconductor group and the second circuit layer; arranging a first redistribution layer on the first circuit layer of the first board surface, wherein the first redistribution layer comprises a first wiring surface and a second wiring surface which are oppositely arranged, and the second wiring surface is effectively and electrically connected with the external connection surface of the second semiconductor group through the first circuit layer; arranging a second solder array on the first wiring surface of the first redistribution layer;
disposing the silicon interposer on a first routing surface of the first redistribution layer, the first semiconductor group and the second semiconductor group forming effective electrical connections through the silicon interposer, the first redistribution layer, and the first circuit layer;
and arranging a third solder array on the second board surface of the carrier board, so that the third solder array is effectively and electrically connected with the active surface of the second semiconductor group through the second circuit layer.
8. The method for manufacturing a semiconductor package structure according to claim 7, wherein a plurality of silicon chips are provided, the silicon chips are connected through the through-silicon vias and the metal bumps, and the silicon chips are pressed to form the silicon interposer.
9. The method of claim 7, wherein the first semiconductor group is formed by fabricating different die core particles and/or components on different wafers, wherein different die core particles and/or components are fabricated by different fabrication processes, and wherein the core particles and/or components have transmission channels formed therebetween through the silicon interposer.
10. The method for manufacturing a semiconductor package structure according to any one of claims 7-9, wherein all line widths, line distances, aperture diameters, and metal bump pitches in the manufacturing method are gradually reduced from the third solder array to the first solder array.
CN202211168023.4A 2022-09-23 2022-09-23 Semiconductor packaging structure and preparation method thereof Pending CN115513182A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117574816A (en) * 2024-01-15 2024-02-20 江苏中科智芯集成科技有限公司 Stress simulation method, system, equipment and storage medium for chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117574816A (en) * 2024-01-15 2024-02-20 江苏中科智芯集成科技有限公司 Stress simulation method, system, equipment and storage medium for chip
CN117574816B (en) * 2024-01-15 2024-03-29 江苏中科智芯集成科技有限公司 Stress simulation method, system, equipment and storage medium for chip

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