CN117574816A - Stress simulation method, system, equipment and storage medium for chip - Google Patents
Stress simulation method, system, equipment and storage medium for chip Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Abstract
The invention relates to the technical field of chip simulation, and discloses a stress simulation method, a system, equipment and a storage medium for a chip, wherein the method comprises the steps of obtaining a silicon intermediate layer and a rewiring layer according to the packaging structure of the chip; modeling the silicon interposer to obtain a silicon interposer model; establishing a rewiring layer model according to the wiring structure of the rewiring layer; combining the silicon interposer model and the rewiring layer model to obtain a stress simulation model; and performing stress simulation according to the stress simulation model to obtain a stress simulation result of the chip. According to the invention, modeling is carried out on the rewiring layer in a mapping or simplifying mode, so that the distribution condition of metal wiring in the rewiring layer can be accurately reflected, the complexity of a stress simulation model is effectively reduced, the influence of the simplifying degree of wiring simplification on simulation precision is reduced in a verification and iterative rollback mode, and the simulation time and hardware requirements of chip stress simulation are reduced while the simulation effect of chip stress simulation is ensured.
Description
Technical Field
The present invention relates to the field of chip simulation technologies, and in particular, to a stress simulation method, system, device, and storage medium for a chip.
Background
Along with the development of the packaging technology of chips, the packaging with Flip Chip (FC) structure, wafer Level Packaging (WLP), system In package (SiP), 2.5D/3D packaging and the like are considered to belong to advanced packaging categories, wherein the wafer level packaging is to package chips when the chips are still on a wafer, a protection layer can be adhered to the top or bottom of the wafer, then a circuit is connected, the wafer is cut into individual chips, and the wafer level packaging can be further divided into Fan-In WLP/FI-WLP (Fan-Out WLP/FO-WLP) and Fan-Out WLP (Fan-Out WLP/FO-WLP) according to different lead modes. Fan-out wafer level packaging (FO-WLP) is an enhancement to standard WLP, and a greater number of I/O connections may be implemented. The method includes embedding the die in an epoxy molding material, then building a high density redistribution layer (RDL) on the wafer surface and applying solder balls to form a reconstituted wafer (reconstituted wafer).
The stress simulation of the chip is an evaluation which must be performed when the chip is packaged, and for the stress simulation of a single chip of the Fanout chip, in order to reduce the operation time and reduce the requirement of the simulation on hardware, the current common simulation mode is to simplify the structure of a rewiring layer, replace all layers of the rewiring layer with single equivalent materials, omit RDL routing, thereby reducing the grid number and solving time.
Disclosure of Invention
In order to solve the technical problems, the invention provides a stress simulation method, a system, computer equipment and a storage medium for a chip, which can solve the problems of low precision or overlong simulation time of the existing simulation method and achieve the effects of reducing the stress simulation time of the chip and improving the stress simulation precision of the chip.
In a first aspect, the present invention provides a stress simulation method for a chip, the method comprising:
obtaining a silicon intermediate layer and a rewiring layer according to the packaging structure of the chip;
modeling the silicon interposer to obtain a silicon interposer model;
establishing a rewiring layer model according to the wiring structure of the rewiring layer, wherein the rewiring layer model comprises a rewiring layer mapping model or a rewiring layer simplifying model;
combining the silicon interposer model and the rewiring layer model to obtain a stress simulation model;
and performing stress simulation according to the stress simulation model to obtain a stress simulation result of the chip.
Further, the step of building a re-wiring layer model according to the wiring structure of the re-wiring layer includes:
dividing the rewiring layer into a plurality of rewiring sublayers according to the wiring structure of the rewiring layer;
acquiring layer parameters of each rewiring sublayer, wherein the layer parameters comprise material attribute parameters, layer thickness parameters and wiring duty ratio parameters;
and mapping each rewiring sub-layer according to the layer parameters to obtain a rewiring layer mapping model.
Further, the step of building a re-wiring layer model according to the wiring structure of the re-wiring layer includes:
dividing the rewiring layer into a plurality of rewiring sublayers according to the wiring structure of the rewiring layer;
obtaining a wiring image of each rewiring sub-layer, and simplifying the wiring image to obtain a simplified wiring image;
simplifying the wiring structure of the rewiring layer according to the simplified wiring image to obtain a simplified rewiring layer;
and performing simulation modeling on the simplified rewiring layer to obtain a rewiring layer simplified model.
Further, the step of simplifying the wiring image to obtain a simplified wiring image includes:
dividing the wiring image into finite element grids, and converting wiring segments in each finite element grid into wiring points to obtain a wiring point image;
dividing the wiring point image into a plurality of wiring point sub-images, and clustering wiring points in each wiring point sub-image to obtain a clustering center point;
connecting the clustering center points according to the connection conditions to obtain a first wiring image;
and judging whether the first wiring image meets the iteration stop condition, if so, taking the first wiring image as a simplified wiring image, otherwise, continuing to execute the current iteration simplification step until the simplified wiring image is obtained.
Further, the step of connecting the cluster center points according to the connection condition to obtain the first wiring image includes:
calculating the distance between each clustering center point and the adjacent clustering center points, and connecting each clustering center point according to the distance constraint condition and the edge connection condition to obtain a first wiring image; the distance constraint condition is that a first distance of each cluster center point is smaller than or equal to a second distance, wherein the first distance is a distance between the cluster center point and an adjacent cluster center point, and the second distance is a distance between the cluster center point and an adjacent and non-connected cluster center point; the edge connection condition is that at least one edge and at most two edges are arranged on the clustering center point, and the width of each edge is consistent with the density of points in the passing wiring point sub-image.
Further, the step of judging whether the first wiring image satisfies an iteration stop condition includes:
judging whether the first distance of each clustering center point is equal to the second distance, if so, taking the clustering center point as a first center point;
and acquiring the number of points of the first center point, judging whether the number of points is smaller than a threshold value, and if yes, judging that the first wiring image meets an iteration stop condition.
Further, before the step of simplifying the wiring structure of the rerouting layer according to the simplified wiring image corresponding to each rerouting sub-layer, the method further includes:
calculating the image similarity between the wiring image of the rewiring sub-layer and the simplified wiring image, and judging whether the simplified wiring image is an optimal simplified wiring image according to the image similarity;
if so, simplifying the wiring structure of the re-wiring layer according to each optimal simplified wiring image, otherwise, rolling back iterative simplification to obtain a previous simplified wiring image, and judging whether the previous simplified wiring image is the optimal simplified wiring image or not until the optimal simplified wiring image is obtained.
In a second aspect, the present invention provides a stress simulation system for a chip, the system comprising:
the data acquisition module is used for acquiring a silicon intermediate layer and a rewiring layer according to the packaging structure of the chip;
the first modeling module is used for modeling the silicon interposer to obtain a silicon interposer model;
the second modeling module is used for building a rerouting layer model according to the wiring structure of the rerouting layer, wherein the rerouting layer model comprises a rerouting layer mapping model or a rerouting layer simplifying model;
the third modeling module is used for combining the silicon interposer model and the rewiring layer model to obtain a stress simulation model;
and the stress simulation module is used for performing stress simulation according to the stress simulation model to obtain a stress simulation result of the chip.
In a third aspect, embodiments of the present invention further provide a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above method when executing the computer program.
In a fourth aspect, embodiments of the present invention also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the above method.
The invention provides a stress simulation method, a system, equipment and a storage medium for a chip. By the method, the silicon intermediate layer and the rewiring layer are respectively modeled, and the rewiring layer is modeled in a mapping and simplified mode, so that the complexity of the model can be reduced, the simulation time of chip stress simulation is shortened, and the simulation precision of the chip stress simulation is improved.
Drawings
FIG. 1 is a flow chart of a stress simulation method in an embodiment of the invention;
FIG. 2 is a schematic diagram of the package structure of a Fanout chip;
FIG. 3 is a schematic view of the original cut surface of a Fanout chip;
FIG. 4 is a schematic cross-sectional view of a Fanout chip after single equivalent replacement of a redistribution layer in a conventional stress simulation method;
FIG. 5 is a schematic side view of the rewiring layer of FIG. 1;
FIG. 6 is another side schematic view and a connection side schematic view of the rewiring layer of FIG. 1;
FIG. 7 is a schematic diagram of a stress simulation system in accordance with an embodiment of the present invention;
fig. 8 is an internal structural view of a computer device in an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, a stress simulation method for a chip according to a first embodiment of the present invention includes steps S10 to S50:
step S10, obtaining a silicon interposer and a rewiring layer according to the packaging structure of the chip;
step S20, modeling the silicon interposer to obtain a silicon interposer model;
step S30, a rerouting layer model is established according to the wiring structure of the rerouting layer, wherein the rerouting layer model comprises a rerouting layer mapping model or a rerouting layer simplifying model;
step S40, combining the silicon interposer model and the rewiring layer model to obtain a stress simulation model;
and S50, performing stress simulation according to the stress simulation model to obtain a stress simulation result of the chip.
Fan Out (Fan Out) packages in advanced packages refer to packages that differ in area from die in wafer level/panel level packages and do not require substrate packaging to achieve lighter, thinner, more I/O interfaces and better electrical performance. The core of the fan-out type package is that RDL (re-wiring layer) replaces the function of substrate transmission signals in the traditional package, and the substrate is removed, so that the height of a chip finished product can be reduced, and meanwhile, the cost is reduced. In addition, since the package area of the fan-out package is not so limited, the overall package design becomes more flexible. That is, RDL plays an important role in Fan Out (Fan Out) packages.
In chip design and fabrication, IO pads are typically distributed at or around the edges of the chip. The IO pad refers to a chip pin processing point, namely, signals of the chip pin are processed and sent to the inside of the chip, and signals output by the inside of the chip are processed and sent to the chip pin. The RDL process is to deposit a metal layer and a corresponding dielectric layer on the surface of the wafer, form metal wires, re-layout the IO ports, and lay out the IO ports to a new and more loosely-occupied area, thereby forming a planar array arrangement. Another great benefit of RDL provides convenience for multi-pellet lateral stacking.
The schematic structural diagram of the chip after fan-out package is shown in fig. 2, wherein after the chips are subjected to EMC molding, the signals are mutually transmitted through the redistribution layer and the Solder Ball bump thereon, for convenience of description, please refer to fig. 3, the fanout chip can be divided into two parts, the lower part is a Silicon interposer (Silicon) molded with the chip, the upper part is a redistribution layer (RDL) with metal wiring, the Solder Ball bump (Solder Ball) is set to also belong to the RDL layer, and when the stress simulation is performed on the chip, the simulation model can be actually divided into two parts, namely the Silicon interposer model and the redistribution layer model, because complex metal wiring is distributed on the RLD layer, if the RDL layer is completely simulated, the requirement on simulation hardware is higher, and the simulation operation time is longer. In order to reduce the operation time and hardware requirements, the current common mode is to simplify the structure of the re-wiring layer and replace all layers of the re-wiring layer with single equivalent materials, as shown in fig. 4, the mode is to directly replace the RDL layer on the basis of a silicon interposer model, and the distribution of RDL cannot be embodied only by inputting the metal content of the whole RDL layer so as to omit RDL routing.
According to the theory, the accuracy and the operation time of the chip stress simulation are mainly related to the rewiring layer, and in order to solve the problem, the invention provides a stress simulation method which is mainly designed for modeling of the rewiring layer, so that the simulation accuracy can be improved on the premise of reducing the operation time. Specifically, after modeling the silicon interposer to obtain a silicon interposer model, modeling the RDL layer is constructed by adopting a mapping manner, and the steps include:
step S301a, dividing the rewiring layer into a plurality of rewiring sublayers according to the wiring structure of the rewiring layer;
step S302a, layer parameters of each re-wiring sub-layer are obtained, wherein the layer parameters comprise material attribute parameters, layer thickness parameters and wiring duty ratio parameters;
and step S303a, mapping each rerouting sublayer according to the layer parameters to obtain a rerouting layer mapping model.
Because the stress of the chip is affected by the distribution structure of the metal wiring, and the situation that the mapping of the single material property of the RLD layer cannot reflect the metal distribution results in the warp simulation and the actual warp result have larger deviation, in this embodiment, the RDL layer is divided into a plurality of redistribution sub-layers according to the wiring structure of the RDL layer, as shown in fig. 5, because the RLD layer may include multiple layers of wiring according to the complexity of the wiring, the RDL layer is divided into a plurality of RDL sub-layers according to the wiring of each layer, then each sub-layer is mapped and modeled, specifically, the material property, thickness and the ratio of the metal wiring in the layer of each redistribution sub-layer are obtained, and then each redistribution sub-layer is mapped according to these parameters, thereby obtaining the mapping model of the redistribution layer. Compared with the prior art, the mapping mode provided by the invention has the advantages that the distribution of metal wiring of each layer is reflected through material properties, thickness and metal duty ratio by layering mapping, and the mode is different from the conventional simulation modeling, but the obtained mapping model is close to an actual model, and the distribution condition of the RDL layer can be reflected, so that the stress simulation precision of a chip can be effectively improved, the simulation operation time is not increased, and the practicability is higher. It should be noted that, a conventional chip simulation modeling method may be used for modeling the silicon interposer, and the mapping of the redistribution layer provided in this embodiment may be implemented by using related functions in conventional modeling software, which will not be repeated in the following.
In another preferred embodiment, the present invention also provides a method for simplified modeling of a rewiring layer, the specific steps comprising:
step S301b, dividing the rewiring layer into a plurality of rewiring sublayers according to the wiring structure of the rewiring layer;
step S302b, obtaining a wiring image of each rewiring sub-layer, and simplifying the wiring image to obtain a simplified wiring image;
step S303b, simplifying the wiring structure of the rewiring layer according to the simplified wiring image, to obtain a simplified rewiring layer;
and step S304b, performing simulation modeling on the simplified rewiring layer to obtain a rewiring layer simplified model.
As can be seen from the above description, the redistribution layer has a great influence on the stress simulation of the chip because of the distribution of the metal wires in the redistribution layer, as shown in fig. 6, in which UBM represents the under bump metallization layer, and if the complex wiring structure is completely simulated, the modeling time and the subsequent stress simulation time are greatly affected. The step of simplifying the wiring image of the rewiring sublayer comprises the following steps:
dividing the wiring image into finite element grids, and converting wiring segments in each finite element grid into wiring points to obtain a wiring point image;
dividing the wiring point image into a plurality of wiring point sub-images, and clustering wiring points in each wiring point sub-image to obtain a clustering center point;
connecting the clustering center points according to the connection conditions to obtain a first wiring image;
and judging whether the first wiring image meets the iteration stop condition, if so, taking the first wiring image as a simplified wiring image, otherwise, continuing to execute the current iteration simplification step until the simplified wiring image is obtained.
In this embodiment, first, line segments in a wiring are converted into points, specifically, a wiring image may be processed into a vector diagram, and then the vector diagram is subjected to finite element mesh division, and for wiring segments existing in a mesh in which a wiring exists, they are converted into wiring points, thereby converting the wiring image into a wiring point image. Then dividing the point image into a plurality of sub-images according to the distribution of the points, and for a plurality of wiring points in the sub-images, obtaining the clustering center points of the wiring points through clustering, it should be noted that, in the embodiment, the simplifying step is an iterative step, the sub-image dividing area of the point image is designed in advance according to the point density of the image, after the sub-images are clustered, a plurality of clustering center points can be obtained, and then each clustering center point is connected, thereby realizing the simplification of the wiring, and the specific connection steps are as follows:
calculating the distance between each clustering center point and the adjacent clustering center points, and connecting each clustering center point according to the distance constraint condition and the edge connection condition to obtain a first wiring image; the distance constraint condition is that a first distance of each cluster center point is smaller than or equal to a second distance, wherein the first distance is a distance between the cluster center point and an adjacent cluster center point, and the second distance is a distance between the cluster center point and an adjacent and non-connected cluster center point; the edge connection condition is that at least one edge and at most two edges are arranged on the clustering center point, and the width of each edge is consistent with the density of points in the passing wiring point sub-image.
In this embodiment, the connection of the cluster center points is performed according to the distance, and because of the characteristics of the wiring structure, at most two sides of each center point are set, and at least one side is set, because the point images represent the wiring trend in this embodiment, no isolated point is ensured during connection, and the connected multiple wirings are gradually combined and simplified in a simplified manner in this embodiment, and furthermore, because there may be differences in the point densities in different sub-images, the point densities represent the metal distribution in the area, and therefore, in this embodiment, the width of the connected side in each sub-image is set to be consistent with the point density, that is, the distribution situation of the metal wirings is further reflected by the width of the side, so that the simulation precision of the subsequent stress simulation on the chip is ensured.
For the distance constraint condition of connection, in this embodiment, first, a first distance between each cluster center point and adjacent cluster center points around the cluster center point is calculated, connection is performed with the adjacent cluster center points according to the requirement of the minimum value of the first distance, and assuming that the distance between the cluster center point and the adjacent and non-connected cluster center points is a second distance, then the constraint condition of connection ensures that the first distance of each cluster center point is not greater than the second distance, and when the first distance is greater than the distance threshold, the cluster center points are used as end points to stop connection, that is, the connection condition in this embodiment ensures that each connected point is the nearest point, so that simplified wiring can accurately reflect the actual wiring structure.
After the cluster center points are connected according to the constraint condition of connection, a first wiring image after one iteration is obtained, then whether the first wiring image is a final simplified wiring image is judged, if so, the wiring structure of the re-wiring layer is simplified according to the wiring image, and if not, the next iteration simplifying operation is needed, and the specific judging steps comprise:
judging whether the first distance of each clustering center point is equal to the second distance, if so, taking the clustering center point as a first center point;
and acquiring the number of points of the first center point, judging whether the number of points is smaller than a threshold value, and if yes, judging that the first wiring image meets an iteration stop condition.
In this embodiment, the judgment of the iteration stop is based on whether the adjacent wires are simplified, and because the simplification mode of this embodiment simplifies the wires by clustering the center points and judges whether the center points are on the same wire by clustering the distance between the center points, if there is a case that the first distance and the second distance of the center points are equal, this indicates that the distance between the wire and the surrounding wires is relatively close, and there is still a wire that can be combined and simplified, at this time, it is considered that the first wire image obtained by the iteration simplification operation is not a wire image that can be finally used for simplifying the wire structure, therefore, the first wire image is converted into a point image, the iteration simplification operation is continuously performed until all adjacent wires are obtained, then the wire structure of the rewiring layer is simplified according to the final simplified wire image, and the simplified rewiring layer is modeled, and because the simplified wire structure is simplified, the modeling time of the rewiring layer simulation modeling can be improved, and the simulated operation time of the simulation model of the simulation of the rewiring layer can be improved, and the simulation accuracy of the stress simulation model of the chip is ensured when the simulation model is implemented for combining the silicon intermediate layer and the simulation model of the rewiring layer.
In addition, in another preferred embodiment, in order to further improve the simulation precision of the chip stress simulation, the invention further provides a method for verifying the simplified wiring image, which comprises the following specific steps:
calculating the image similarity between the wiring image of the rewiring sub-layer and the simplified wiring image, and judging whether the simplified wiring image is an optimal simplified wiring image according to the image similarity;
if so, simplifying the wiring structure of the re-wiring layer according to each optimal simplified wiring image, otherwise, rolling back iterative simplification to obtain a previous simplified wiring image, and judging whether the previous simplified wiring image is the optimal simplified wiring image or not until the optimal simplified wiring image is obtained.
In this embodiment, for the simplified wiring image and the original wiring image, the simplified effect is determined by calculating the similarity of the images, where the structural similarity calculation method SSIM or the depth neural network model is used to identify the similarity between the simplified wiring image and the original wiring image, the specific calculation steps do not have excessive restrictions, if the image similarity of the two meets the preset similarity threshold, the simplified wiring image is considered to be the optimal simplified wiring image, at this time, the optimal simplified wiring image may be used to simplify the wiring structure of the heavy wiring layer, if the similarity threshold is not met, it is explained that the simplified wiring image of this time is excessively used to possibly affect the simulation accuracy in the stress simulation modeling, so that rollback needs to be performed on the iterative simplified operation to obtain the simplified wiring image generated by the previous iterative operation, and then, whether the image similarity between the previous simplified wiring image and the original wiring image meets the image is calculated until the simplified image meeting the image similarity requirement is obtained, and then the wiring layer is routed according to the simplified wiring image as the optimal simplified wiring structure of the simplified wiring image.
The reason why the inspection method provided in this embodiment does not calculate the image similarity with the original wiring image after obtaining the simplified wiring image each time is that the original simplified image must meet the similarity requirement, although the simplified wiring image can ensure the simulation precision in the stress simulation, the modeling time and the operation time are long due to incomplete simplification.
Compared with the traditional method, the stress simulation method for the chip cannot meet the problem of operation efficiency and simulation precision at the same time, the silicon intermediate layer and the rewiring layer of the Fanout chip are separately modeled, and the rewiring layer is modeled in a mapping or simplifying mode, so that the distribution condition of metal wires in the rewiring layer can be accurately reflected, the complexity of a stress simulation model is effectively reduced, the influence of the simplifying degree of wire simplification on the simulation precision is reduced in a verification and iterative rollback mode, the simulation time and hardware requirements of the chip stress simulation are reduced, and the simulation effect of the chip stress simulation is guaranteed.
Referring to fig. 7, a stress simulation system for a chip according to a second embodiment of the present invention includes:
the data acquisition module 10 is used for obtaining a silicon interposer and a rewiring layer according to the packaging structure of the chip;
a first modeling module 20, configured to model the silicon interposer to obtain a silicon interposer model;
a second modeling module 30, configured to build a rewiring layer model according to the wiring structure of the rewiring layer, where the rewiring layer model includes a rewiring layer mapping model or a rewiring layer simplification model;
a third modeling module 40, configured to combine the silicon interposer model and the redistribution layer model to obtain a stress simulation model;
the stress simulation module 50 is configured to perform stress simulation according to the stress simulation model, so as to obtain a stress simulation result of the chip.
The technical features and technical effects of the stress simulation system for chips according to the embodiment of the present invention are the same as those of the method according to the embodiment of the present invention, and are not described herein. The various modules in the stress simulation system for a chip described above may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
In addition, the embodiment of the invention also provides computer equipment, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the steps of the method when executing the computer program.
Referring to FIG. 8, in one embodiment, an internal architecture diagram of a computer device, which may be a terminal or a server in particular. The computer device includes a processor, a memory, a network interface, a display, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a stress simulation method for a chip. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be keys, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.
It will be appreciated by those of ordinary skill in the art that the architecture shown in fig. 8 is merely a block diagram of some of the architecture relevant to the present application and is not intended to limit the computer device on which the present application may be implemented, and that a particular computing device may include more or fewer components than those shown in the middle, or may combine certain components, or have the same arrangement of components.
Furthermore, the embodiment of the invention also provides a computer readable storage medium, on which a computer program is stored, which when being executed by a processor, implements the steps of the method.
In summary, the method, the system, the equipment and the storage medium for stress simulation of the chip provided by the embodiment of the invention obtain the silicon interposer and the rewiring layer according to the packaging structure of the chip; modeling the silicon interposer to obtain a silicon interposer model; establishing a rewiring layer model according to the wiring structure of the rewiring layer, wherein the rewiring layer model comprises a rewiring layer mapping model or a rewiring layer simplifying model; combining the silicon interposer model and the rewiring layer model to obtain a stress simulation model; and performing stress simulation according to the stress simulation model to obtain a stress simulation result of the chip. According to the invention, the silicon intermediate layer and the rewiring layer of the Fanout chip are separately modeled, and the rewiring layer is modeled in a mapping or simplified mode, so that the distribution condition of metal wires in the rewiring layer can be accurately reflected, the complexity of a stress simulation model is effectively reduced, the influence of the simplified degree of wire simplification on the simulation precision is reduced in a verification and iterative rollback mode, the simulation time and the hardware requirement of the chip stress simulation are reduced, and the simulation effect of the chip stress simulation is ensured.
In this specification, each embodiment is described in a progressive manner, and all the embodiments are directly the same or similar parts referring to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments. It should be noted that, any combination of the technical features of the foregoing embodiments may be used, and for brevity, all of the possible combinations of the technical features of the foregoing embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples represent only a few preferred embodiments of the present application, which are described in more detail and are not thereby to be construed as limiting the scope of the invention. It should be noted that modifications and substitutions can be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and substitutions should also be considered to be within the scope of the present application. Therefore, the protection scope of the patent application is subject to the protection scope of the claims.
Claims (10)
1. A stress simulation method for a chip, the method comprising:
obtaining a silicon intermediate layer and a rewiring layer according to the packaging structure of the chip;
modeling the silicon interposer to obtain a silicon interposer model;
establishing a rewiring layer model according to the wiring structure of the rewiring layer, wherein the rewiring layer model comprises a rewiring layer mapping model or a rewiring layer simplifying model;
combining the silicon interposer model and the rewiring layer model to obtain a stress simulation model;
and performing stress simulation according to the stress simulation model to obtain a stress simulation result of the chip.
2. The stress simulation method for a chip according to claim 1, wherein the step of building a re-wiring layer model according to a wiring structure of the re-wiring layer comprises:
dividing the rewiring layer into a plurality of rewiring sublayers according to the wiring structure of the rewiring layer;
acquiring layer parameters of each rewiring sublayer, wherein the layer parameters comprise material attribute parameters, layer thickness parameters and wiring duty ratio parameters;
and mapping each rewiring sub-layer according to the layer parameters to obtain a rewiring layer mapping model.
3. The stress simulation method for a chip according to claim 1, wherein the step of building a re-wiring layer model according to a wiring structure of the re-wiring layer comprises:
dividing the rewiring layer into a plurality of rewiring sublayers according to the wiring structure of the rewiring layer;
obtaining a wiring image of each rewiring sub-layer, and simplifying the wiring image to obtain a simplified wiring image;
simplifying the wiring structure of the rewiring layer according to the simplified wiring image to obtain a simplified rewiring layer;
and performing simulation modeling on the simplified rewiring layer to obtain a rewiring layer simplified model.
4. The stress simulation method for a chip according to claim 3, wherein the step of simplifying the wiring image to obtain a simplified wiring image includes:
dividing the wiring image into finite element grids, and converting wiring segments in each finite element grid into wiring points to obtain a wiring point image;
dividing the wiring point image into a plurality of wiring point sub-images, and clustering wiring points in each wiring point sub-image to obtain a clustering center point;
connecting the clustering center points according to the connection conditions to obtain a first wiring image;
and judging whether the first wiring image meets the iteration stop condition, if so, taking the first wiring image as a simplified wiring image, otherwise, continuing to execute the current iteration simplification step until the simplified wiring image is obtained.
5. The method for stress simulation of a chip according to claim 4, wherein the step of connecting the cluster center points according to the connection condition to obtain the first wiring image comprises:
calculating the distance between each clustering center point and the adjacent clustering center points, and connecting each clustering center point according to the distance constraint condition and the edge connection condition to obtain a first wiring image; the distance constraint condition is that a first distance of each cluster center point is smaller than or equal to a second distance, wherein the first distance is a distance between the cluster center point and an adjacent cluster center point, and the second distance is a distance between the cluster center point and an adjacent and non-connected cluster center point; the edge connection condition is that at least one edge and at most two edges are arranged on the clustering center point, and the width of each edge is consistent with the density of points in the passing wiring point sub-image.
6. The stress simulation method for a chip according to claim 4, wherein the step of judging whether the first wiring image satisfies an iteration stop condition comprises:
judging whether the first distance of each clustering center point is equal to the second distance, if so, taking the clustering center point as a first center point;
and acquiring the number of points of the first center point, judging whether the number of points is smaller than a threshold value, and if yes, judging that the first wiring image meets an iteration stop condition.
7. The stress simulation method for a chip according to claim 4, wherein before the step of simplifying the wiring structure of the rewiring layer based on the simplified wiring images corresponding to the respective rewiring sublayers, the method further comprises:
calculating the image similarity between the wiring image of the rewiring sub-layer and the simplified wiring image, and judging whether the simplified wiring image is an optimal simplified wiring image according to the image similarity;
if so, simplifying the wiring structure of the re-wiring layer according to each optimal simplified wiring image, otherwise, rolling back iterative simplification to obtain a previous simplified wiring image, and judging whether the previous simplified wiring image is the optimal simplified wiring image or not until the optimal simplified wiring image is obtained.
8. A stress simulation system for a chip, the system comprising:
the data acquisition module is used for acquiring a silicon intermediate layer and a rewiring layer according to the packaging structure of the chip;
the first modeling module is used for modeling the silicon interposer to obtain a silicon interposer model;
the second modeling module is used for building a rerouting layer model according to the wiring structure of the rerouting layer, wherein the rerouting layer model comprises a rerouting layer mapping model or a rerouting layer simplifying model;
the third modeling module is used for combining the silicon interposer model and the rewiring layer model to obtain a stress simulation model;
and the stress simulation module is used for performing stress simulation according to the stress simulation model to obtain a stress simulation result of the chip.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any one of claims 1 to 7 when the computer program is executed by the processor.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 7.
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