WO2022041494A1

WO2022041494A1 - Method and structure for pre-guiding logic outputs of macro cells in narrow channel layout

Info

Publication number: WO2022041494A1
Application number: PCT/CN2020/128250
Authority: WO
Inventors: 赵少峰
Original assignee: 东科半导体(安徽)股份有限公司
Priority date: 2020-08-28
Filing date: 2020-11-12
Publication date: 2022-03-03
Also published as: CN111859841A

Abstract

A method and structure for pre-guiding logic outputs of macro cells in a narrow channel layout. The method comprises: after the layout of macro cells, performing pre-winding processing on all the macro cells according to output logics of all the macro cells, and determining whether the channel dimensions of a channel between any two adjacent macro cells after layout meets the requirements for wiring track resources (110); if the channel dimensions of a first channel (3) between a first macro cell (1) and a second macro cell (2) that are adjacent do not meet the requirements for wiring track resources, performing pre-guiding processing on the first channel (3) (120); and by means of outputs of buffers in a first buffer array (6) and a second buffer array that are added by means of executing pre-guiding processing, leading the output logics of pins of the first macro cell (1) and the second macro cell (2) out of the first channel (3), so as to perform the layout of corresponding logic function units, and perform routing connection between the logic function units and the pins by means of the buffers. Thus, the problem of wiring track resources in a narrow channel layout being insufficient and not meeting logic output requirements is solved.

Description

Logic output pre-steering method and structure of macrocell under narrow channel layout

This application claims the priority of the Chinese patent application filed on August 28, 2020 with the application number 202010887106.3 and the title of the invention is "Logical Output Pre-guidance Method and Structure of Macrocells in Narrow Channel Layout".

technical field

The present invention relates to the technical field of integrated circuit layout design and optimization, in particular to a logic output pre-guidance method and structure of macro cells under narrow channel layout.

Background technique

In digital back-end integrated circuit (IC) design, the macro cell (Macro) is the most common unit in the design. A macrocell is a predefined logic function realization unit composed of flip-flops, arithmetic logic units, hardware registers, etc. with a higher abstraction level than logic gates. These logic cells are placed on the silicon chip as a whole as a macrocell. In the manufacturing process, engineers need to build metal interconnect lines between each predefined unit, and different connection methods can achieve different functions at a higher logic level.

In the design, the macro cells are arranged in an array, and there is a routing track aisle between every two macro cells, called a channel (Channel), and the routing track in the channel is called a track. Wiring between macrocells is made in vertical and horizontal routing track channels. The connection of macrocells needs to insert logical function units in order to realize different functions at a higher logic level. However, in many designs, due to the constraints and limitations of the chip area, the channel width is limited, and the channels between adjacent macrocells, or between the macrocell and the chip boundary are not enough to meet the trace resource requirements after the logic functional unit is inserted. , resulting in having to sacrifice area or redo the macrocell layout to meet the trace resource requirements.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a logic output pre-guidance method and structure for macro cells under narrow channel layout, which can solve the problem of insufficient routing track resources to meet logic output requirements under narrow channel layout.

To this end, in a first aspect, an embodiment of the present invention provides a logic output pre-guidance method for a macrocell under a narrow channel layout, including:

After the macrocell is laid out, all macrocells are pre-wired according to the output logic of all macrocells, and it is determined whether the channel size of the channel between any two adjacent macrocells after the layout meets the routing track resource requirements. ;

When the channel size of the first channel between the adjacent first macro-unit and the second macro-unit does not meet the routing track resource requirement, perform pre-steering processing on the first channel;

Wherein, the pre-guidance processing specifically includes:

Determine the total number of first routing tracks in the first channel parallel to the direction of the first channel, and assign the total number to a first number and a second number; the sum of the first number and the second number is less than equal to said total quantity;

According to the pin sequence of the first macro unit on the first channel side, corresponding to each pin, a buffer is inserted into one of the first wiring tracks in the first number of first wiring tracks in turn, and each The buffers are sequentially arranged on the adjacent second wiring tracks perpendicular to the channel direction, so as to form a first buffer array in the shape of a broken line;

According to the pin sequence of the second macro unit on the first channel side, corresponding to each pin, a buffer is inserted into one of the first wiring tracks of the second number of first wiring tracks in turn, and each The buffers are sequentially arranged on the adjacent second routing tracks perpendicular to the channel direction, so as to form a second buffer array in the shape of a broken line;

Routing along the second routing track connects each pin of the first macrocell with a buffer corresponding to one of the first buffer arrays, and routing each pin of the second macrocell with a corresponding buffer in the second buffer array;

Routing along the first routing track is used to lead the outputs of the respective buffers out of the first channel, thereby leading the logic outputs of the respective pins of the first macrocell and the second macrocell to the first channel outside;

After the pre-boot processing is performed on the first channel, corresponding logic is performed outside the first channel through the outputs of the respective buffers of the first buffer array and/or the second buffer array Placement and routing of functional units.

Preferably, the pre-winding process is specifically as follows: for any two or more pins of any two or more macro units with related output logic, inserting corresponding logic function units into the channel to connect the two or more pins.

Further preferably, the determination of whether the channel size of the channel between any two adjacent macro-units after the layout satisfies the requirements of the routing track resources is specifically:

It is determined whether the logical functional units to be inserted in each channel can all be inserted into the channel.

Preferably, the method for allocating the total number to the first number and the second number specifically includes: according to the number of pins of the first macro unit on one side of the first channel and the number of pins of the second macro unit on the first channel The number of pins on one side determines the first number and the second number.

In a second aspect, an embodiment of the present invention provides a logic output pre-steering structure of a macrocell in a narrow channel layout, including: a first macrocell, a second macrocell, a first channel, a first buffer array, and a second buffer array;

The first macro unit and the second macro unit are two adjacent macro units, and the first channel is between the first macro unit and the second macro unit; the first channel has a wiring track resources, including a plurality of first routing tracks parallel to the direction of the first channel and a plurality of second routing tracks perpendicular to the direction of the first channel;

The first buffer array and the second buffer array are arranged in the first channel, and are arranged in the shape of a broken line;

Wherein, each buffer in the first buffer array is sequentially arranged on one of the first wiring tracks of the first number, and is connected to the first wiring track along the first wiring track and the first macro unit. A corresponding pin is connected by wiring;

Each buffer in the second buffer array is sequentially disposed on one of the second number of first routing tracks, and corresponds to one of the second macrocells along the first routing track The pins are connected by wiring; the sum of the first quantity and the second quantity is less than or equal to the total quantity;

In each buffer array, adjacent buffers have displacements of at least one wiring track along the direction of the first wiring track and the direction of the second wiring track.

Preferably, the first wiring tracks of the first number and the first wiring tracks of the second number do not overlap each other.

Preferably, the structure further includes: a logical functional unit;

The logic function unit is arranged outside the first channel; one or more pins of the first macro unit and/or the second macro unit pass through the first buffer array and/or the second buffer array Corresponding buffers in are connected to the logic functional units.

Preferably, the logic function unit is also connected to one or more pins of other macro units.

Preferably, the structure further includes: other buffers outside the first channel;

One or more pins of the first macro unit and/or the second macro unit are connected to other buffers after passing through the corresponding buffers in the first buffer array and/or the second buffer array , and then connected to the logic function unit.

In the method for pre-piloting the logic output of macro cells in a narrow channel layout provided by the embodiment of the present invention, the first buffer array and the second buffer array arranged in a zigzag line are added by performing pre-pilot processing on the first channel, so that the buffer Each buffer in the array guides the pin logic output of the corresponding first macro unit and the second macro unit, and leads them out of the first channel, so as to facilitate the layout of the corresponding logic function units outside the channel, and realize The logic function unit is connected with the wiring of the pin through the buffer, thereby maximizing the rational use of the channel track resources under the narrow channel layout, so that the limited track track resources can meet the logic output requirements to the greatest extent.

Description of drawings

1 is a flowchart of a logic output pre-guidance method for a macrocell under a narrow channel layout provided by an embodiment of the present invention;

FIG. 2 is a flowchart of method steps for pre-boot processing provided by an embodiment of the present invention;

3 is a schematic structural diagram of two adjacent macro cells under a narrow channel layout provided by an embodiment of the present invention;

FIG. 4 is a schematic structural diagram-schematic diagram showing two adjacent macro-units of non-functional physical units (Physical only cells);

FIG. 5 is a schematic diagram of a logic output pre-guidance structure of a macrocell under a narrow channel layout.

detailed description

The technical solutions of the present invention will be further described in detail below through the accompanying drawings and embodiments.

An embodiment of the present invention provides a logic output pre-guidance method for a macrocell under a narrow channel layout, the main steps of which are shown in FIG. 1 , including:

Step 110: After the macro-unit is laid out, pre-wire processing is performed on all the macro-units according to the output logic of all the macro-units, and it is determined whether the channel size of the channel between any two adjacent macro-units after the layout satisfies the routing requirements. orbital resource requirements;

Specifically, after the macrocells are laid out, the positions of the respective macrocells have been determined. Each macrocell has its own output logic, and according to the output logic, the trace resources required for the output of each macrocell can be calculated.

In the channel between two adjacent macro cells, there are available wiring tracks (tracks), including a first wiring track parallel to the channel direction and a second wiring track perpendicular to the channel direction. There are multiple first wiring tracks and second wiring tracks. The multiple first wiring tracks are arranged in parallel with each other. They are on the same layer or different layers in terms of physical implementation, and the multiple second wiring tracks are also arranged in parallel with each other. , they are physically implemented at the same layer or at different layers.

Pre-wire processing is a process after the macrocell layout. It refers to inserting the corresponding logic function unit into the channel for any two or more pins of any two or more macrocells with related output logic. to connect the two or more pins. That is to say, for each adjacent first macro unit and second macro unit, confirm whether the logic function unit to be inserted in the first channel between them has enough space and routing track resources provided in the first channel. , if not, it means that the channel between these two adjacent macrocells cannot route the track resource requirements after layout.

If the resource requirements of the routing track can be met, the logic function unit can be directly inserted and then routed. If the requirements cannot be met, pre-boot processing needs to be performed.

Step 120, when the channel size of the first channel between the adjacent first macro-unit and the second macro-unit does not meet the routing track resource requirement, perform pre-guidance processing on the first channel;

Among them, the pre-guidance process is specifically shown in Figure 2, including:

Step 121, determining the total number of the first routing tracks in the first channel parallel to the first channel direction, and assigning the total number to the first number and the second number;

That is to say, first determine the number of available routing track resources in the channel, and then reasonably allocate and use the routing track resources.

A specific method for allocating the total number to the first number and the second number may be: determining the number of pins of the first macro unit on the first channel side and the number of pins of the second macro unit on the first channel side. A quantity and a second quantity. That is, the allocation is performed according to the amount of the routing track resource usage requirements of two adjacent macro cells in the same channel. Of course, the total number can also be distributed equally. In short, the sum of the first quantity and the second quantity is less than or equal to the total quantity.

Step 122, according to the order of the pins of the first macro unit on the first channel side, insert a buffer on one of the first routing tracks in the first number of first routing tracks corresponding to each pin in turn, and Each buffer is sequentially arranged on the adjacent second routing tracks in the vertical channel direction, so as to form a first buffer array in the shape of a broken line;

That is, for the first pin of the first macrocell, along the second routing track corresponding to the first pin, insert a buffer on the first routing track closest to the first macrocell; then For the second pin of the first macrocell, along the second trace corresponding to the second pin, insert a buffer on the first trace closest to the first macrocell, and so on, until Insert the first number of buffers, and then insert buffers one by one to each pin in a direction close to the first macrocell until all the buffers corresponding to the pins are inserted, forming a first buffer array.

In each buffer array, adjacent buffers have displacements of at least one wiring track along the direction of the first wiring track and the direction of the second wiring track. The buffers inserted in this way form a continuous or discontinuous polyline shape.

Step 123, according to the order of the pins of the second macro unit on the first channel side, insert a buffer on one of the first wiring tracks in the second number of first wiring tracks corresponding to each pin in turn, and Each buffer is sequentially arranged on the adjacent second routing tracks in the vertical channel direction, so as to form a second buffer array in the shape of a broken line;

Specifically, the formation process of the second buffer array is the same as that of the first buffer array, and details are not repeated here.

Step 124, routing along the second routing track to connect each pin of the first macrocell with a buffer corresponding to one of the first buffer arrays, and routing each pin of the second macrocell to the second buffer a corresponding buffer in the device array;

After the buffer array is formed, the corresponding pins and the input terminals of the buffer are wired and connected.

Step 125, routing along the first wiring track to lead the output of each buffer out of the first channel, so as to lead the logic output of each pin of the first macro unit and the second macro unit out of the first channel.

Therefore, under the condition of reasonably maximizing the utilization of the narrow channel routing resources, the logic outputs of all the pins of the macrocell are guided out of the narrow channel.

Step 130: After the pre-boot processing is performed on the first channel, through the outputs of the respective buffers of the first buffer array and/or the second buffer array, the layout and layout of the corresponding logical functional units are performed outside the first channel. Wiring connection.

In this example, only the connection of the logical outputs of two adjacent macro-units is described. Of course, for the first macro-unit and the second macro-unit, they may also be connected with one or more references of other macro-units. There is a logic function connection requirement between the pins, so the logic function unit can also be connected with one or more pins of other macro cells.

In addition, other buffers may also be provided outside the first channel; one or more pins of the first macro unit and/or the second macro unit pass through corresponding pins in the first buffer array and/or the second buffer array After the buffer is selected, it can also be connected to other buffers, and then connected to the logic functional unit.

The above describes the logic output pre-steering method of the macro cell under the narrow channel layout, and the following describes the logic output pre-steering structure of the macro cell under the narrow channel layout implemented by the above method.

As shown in FIG. 3 , the structures of two adjacent macro units under the narrow channel layout are as shown in the figure, including: a first macro unit 1 , a second macro unit 2 and a first channel 3 . The first macro unit 1 and the second macro unit 2 are two adjacent macro units, and the first channel 3 is between the first macro unit 1 and the second macro unit 2 .

The first channel 3 has routing track resources. This routing track resource is distributed throughout the entire chip in the physical design, but for the logic output of the macrocell, it is necessary to use the routing track resources in the first channel 3 for logic. output. As shown in the figure, the wire resources in the first channel 3 include a plurality of first wire tracks 41 parallel to the direction of the first channel and a plurality of second wire tracks 42 perpendicular to the direction of the first channel.

In the back-end design process of the actual chip, there will also be some non-functional physical cells (Physical only cells) occupying the area in the channel. Non-functional physical cells are those that are not in the netlist but need to exist in the actual chip. , such as power ground IO, IO that supplies power to IO, and some substrates, well contact units, etc.

As shown in FIG. 3 and FIG. 4 , the non-functional physical unit 5 occupies the first channel 3 , which makes the available routing track resources in the first channel 3 even tighter. For this reason, after the above-mentioned logic output pre-booting method is performed, a first buffer array 6 and a second buffer array (not shown in the figure) as shown in FIG. 5 will be formed in the first channel.

3, 4, and 5, the first buffer array 6 and the second buffer array are arranged in the first channel 3 and are arranged in the shape of a broken line respectively; because the second buffer array and the first buffer array The setting method of the array 6 is the same, except that the occupied trace track resources may be evenly allocated or allocated according to the output logic requirements, so the second buffer array is not shown here. In the case of evenly distributing the routing track resources occupied by the two, it can be considered that the first buffer array 6 and the second buffer array are arranged symmetrically.

Each buffer 61 in the first buffer array 6 is sequentially disposed on one of the first wiring tracks 41 of the first number of first wiring tracks, and is connected to the first macrocell 1 along the first wiring track 41 A corresponding pin 11 of 1 is connected by wiring; similarly, each buffer in the second buffer array is sequentially arranged on one of the first wiring tracks in the second number of first wiring tracks, and along the first track The wire track is connected with a corresponding pin 21 of the second macrocell 2 by wiring. The first number of first wiring tracks and the second number of first wiring tracks do not overlap each other.

The logic output pre-guidance structure also includes: a logic function unit; the logic function unit can be set at an appropriate position outside the first channel 3 according to the actual situation of the layout, so the logic function unit is not shown separately in the figure.

One or more pins of the first macrocell 1 and/or the second macrocell 2 are connected to the logic functional unit through the corresponding buffers in the first buffer array 6 and/or the second buffer array. The connection in this step is the same as the conventional wiring, which can be routed along the wiring track, which is not shown in the figure.

Of course, for the first macro unit and the second macro unit, they may also have logic function connection requirements with one or more pins of other macro units, so the logic function unit can also be connected with one or more pins of other macro units. Multiple pins are connected.

The specific embodiments described above further describe the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

A logic output pre-guidance method for macro cells under narrow channel layout, characterized in that the logic output pre-guidance method for macro cells in the narrow channel layout comprises:

After the macrocell is laid out, all macrocells are pre-wired according to the output logic of all macrocells, and it is determined whether the channel size of the channel between any two adjacent macrocells after the layout meets the routing track resource requirements. ;

When the channel size of the first channel between the adjacent first macro-unit and the second macro-unit does not meet the routing track resource requirement, perform pre-steering processing on the first channel;

Wherein, the pre-guidance processing specifically includes:

Determine the total number of first routing tracks in the first channel parallel to the direction of the first channel, and assign the total number to a first number and a second number; the sum of the first number and the second number is less than equal to said total quantity;

According to the pin sequence of the first macro unit on the first channel side, corresponding to each pin, a buffer is inserted into one of the first wiring tracks in the first number of first wiring tracks in turn, and each The buffers are sequentially arranged on the adjacent second wiring tracks perpendicular to the channel direction, so as to form a first buffer array in the shape of a broken line;

According to the pin sequence of the second macro unit on the first channel side, corresponding to each pin, a buffer is inserted into one of the first wiring tracks of the second number of first wiring tracks in turn, and each The buffers are sequentially arranged on the adjacent second routing tracks perpendicular to the channel direction, so as to form a second buffer array in the shape of a broken line;

Routing along the second routing track connects each pin of the first macrocell with a buffer corresponding to one of the first buffer arrays, and routing each pin of the second macrocell with a corresponding buffer in the second buffer array;

Routing along the first routing track is used to lead the outputs of the respective buffers out of the first channel, thereby leading the logic outputs of the respective pins of the first macrocell and the second macrocell to the first channel outside;

After the pre-boot processing is performed on the first channel, corresponding logic is performed outside the first channel through the outputs of the respective buffers of the first buffer array and/or the second buffer array Placement and routing of functional units.
The logic output pre-guidance method for macro cells in a narrow channel layout according to claim 1, wherein the pre-winding process is specifically: for any two or more macro cells with related output logic. One or more pins, and corresponding logic function units are inserted into the channel to connect the two or more pins.
The logic output pre-guidance method of macro cells under narrow channel layout according to claim 2, wherein, after the layout is determined, whether the channel size of the channel between any two adjacent macro cells satisfies the routing track The specific resource requirements are:

It is determined whether the logical functional units to be inserted in each channel can all be inserted into the channel.
The method according to claim 1, wherein the method for allocating the total number into the first number and the second number specifically comprises: according to the number of pins of the first macro unit on one side of the first channel and the number of the first The number of pins of the two macrocells on one side of the first channel determines the first number and the second number.
A logic output pre-steering structure for macro cells under narrow channel layout, characterized in that the structure includes: a first macro cell, a second macro cell, a first channel, a first buffer array, and a second buffer array ;

The first macro unit and the second macro unit are two adjacent macro units, and the first channel is between the first macro unit and the second macro unit; the first channel has a wiring track resources, including a plurality of first routing tracks parallel to the direction of the first channel and a plurality of second routing tracks perpendicular to the direction of the first channel;

The first buffer array and the second buffer array are arranged in the first channel, and the arrays are respectively arranged in the shape of a broken line;

Wherein, each buffer in the first buffer array is sequentially arranged on one of the first wiring tracks of the first number, and is connected to the first wiring track along the first wiring track and the first macro unit. A corresponding pin is connected by wiring;

Each buffer in the second buffer array is sequentially disposed on one of the second number of first routing tracks, and corresponds to one of the second macrocells along the first routing track The pins are connected by wiring; the sum of the first quantity and the second quantity is less than or equal to the total quantity;

In each buffer array, adjacent buffers have displacements of at least one wiring track along the direction of the first wiring track and the direction of the second wiring track.
The logic output pre-guiding structure of claim 5, wherein the first number of first wiring tracks and the second number of first wiring tracks do not overlap each other.
The logic output pre-boot structure according to claim 5, wherein the structure further comprises: a logic function unit;

The logic function unit is arranged outside the first channel; one or more pins of the first macro unit and/or the second macro unit pass through the first buffer array and/or the second buffer array Corresponding buffers in are connected to the logic functional units.
The logic output pre-guidance structure according to claim 7, wherein the logic function unit is further connected to one or more pins of other macro units.
The logic output pre-boot structure according to claim 7, wherein the structure further comprises: other buffers outside the first channel;

One or more pins of the first macro unit and/or the second macro unit are connected to other buffers after passing through the corresponding buffers in the first buffer array and/or the second buffer array , and then connected to the logical functional unit.