CN111859841A - Logic output pre-guiding method and structure of macro unit under narrow channel layout - Google Patents
Logic output pre-guiding method and structure of macro unit under narrow channel layout Download PDFInfo
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Abstract
The embodiment of the invention relates to a logic output pre-guiding method and a structure of a macro unit under a narrow channel layout. The method comprises the following steps: after the macro cells are distributed, performing pre-winding processing on all the macro cells according to the output logics of all the macro cells, and determining whether the channel size of a channel between any two adjacent macro cells meets the requirement of routing track resources or not after the distribution; when the channel size of a first channel between the adjacent first macro unit and the second macro unit does not meet the requirement of routing track resources, pre-guiding processing is performed on the first channel; through the output of each buffer of the first buffer array and the second buffer array added by executing pre-guiding processing on the first channel, the pin output logics of the first macro unit and the second macro unit are led out of the first channel, so that the corresponding logic function unit is arranged, and the logic function unit is connected with the wiring of the pins through the buffers, thereby solving the problem that the wiring track resources are insufficient and the logic output requirement cannot be met under the narrow channel arrangement.
Description
Technical Field
The invention relates to the technical field of integrated circuit layout design and optimization, in particular to a logic output pre-guiding method and structure of a macro cell under narrow channel layout.
Background
In digital back end Integrated Circuit (IC) design, Macro cells (Macro) are the most common cells in the design. The macro unit is a predefined logic function implementation unit composed of a trigger with higher abstraction level relative to the logic gate, an arithmetic logic unit, a hardware register, etc. The logic cells are disposed as a macro cell in its entirety on a silicon wafer. During the manufacturing process, engineers need to build metal interconnection lines between each predefined unit, and different connection modes can realize different functions at a higher logic level.
In the design, the macro cells are arranged in an array, and there is a track passageway between every two macro cells, called a Channel (Channel), and the track in the Channel is called a track. The wiring between macro cells is performed in vertical and horizontal routing track channels. The wiring of macro cells requires the insertion of logical functional units at a higher logical level in order to implement different functions. However, in many designs, because of the constraint and limitation of the chip area, the channel width is limited, and the channel between adjacent macro cells or between a macro cell and the chip boundary is not enough to satisfy the trace track resource requirement after the logic functional unit is inserted, so that the trace track resource requirement has to be satisfied at the expense of sacrificing the area or re-performing macro cell layout.
Disclosure of Invention
The invention aims to provide a logic output pre-guiding method and a structure of a macro unit under narrow-channel layout, which can solve the problem that the logic output requirement cannot be met due to insufficient routing track resources under narrow-channel layout.
To this end, in a first aspect, an embodiment of the present invention provides a method for pre-steering logic output of a macro cell in a narrow channel layout, including:
after the macro cells are distributed, performing pre-winding processing on all the macro cells according to the output logics of all the macro cells, and determining whether the channel size of a channel between any two adjacent macro cells meets the requirement of routing track resources or not after the distribution;
when the channel size of a first channel between a first macro unit and a second macro unit which are adjacent does not meet the requirement of routing track resources, pre-guiding processing is carried out on the first channel;
wherein the pre-pilot processing specifically comprises:
determining the total number of first routing tracks parallel to the first channel direction in the first channel, and allocating the total number to be a first number and a second number; the sum of the first number and the second number is less than or equal to the total number;
inserting a buffer on one first routing track of a first number of first routing tracks in sequence corresponding to each pin according to the sequence of the pins of the first macro unit on one side of the first channel, and sequentially arranging the buffers on adjacent second routing tracks vertical to the channel direction, so as to form a first buffer array in a zigzag shape;
inserting a buffer on one first routing track of a second number of first routing tracks in sequence corresponding to each pin according to the sequence of the pins of the second macro unit on one side of the first channel, and sequentially arranging the buffers on adjacent second routing tracks vertical to the channel direction, so as to form a second buffer array in a zigzag shape;
routing a buffer connecting each pin of the first macro cell with one of the first buffer arrays along the second routing track, and routing a buffer connecting each pin of the second macro cell with one of the second buffer arrays;
routing along the first trace track to direct the output of each buffer out of the first channel, thereby directing the logical output of each pin of the first and second macro-cells out of the first channel;
after the pre-steering processing is executed on the first channel, the layout and wiring connection of the corresponding logic function unit is performed outside the first channel through the output of each buffer of the first buffer array and/or the second buffer array.
Preferably, the pre-winding treatment specifically comprises: for any two or more pins of the macro-unit with relevant output logic, inserting a corresponding logic function unit in the channel for connecting the two or more pins.
Further preferably, the step of determining whether the channel size of the channel between any two adjacent macro cells after the layout meets the requirement of the routing track resource specifically includes:
it is determined whether the logical functional units to be inserted in each channel can be fully inserted in the channel.
Preferably, the method for allocating the total number to the first number and the second number specifically includes: and determining the first number and the second number according to the number of pins of the first macro unit on one side of the first channel and the number of pins of the second macro unit on one side of the first channel.
In a second aspect, an embodiment of the present invention provides a logic output pre-steering structure of a macro cell in a narrow channel layout, including: a first macro-cell, a second macro-cell, a first channel, a first buffer array, and a second buffer array;
the first macro unit and the second macro unit are two adjacent macro units, and the first channel is arranged between the first macro unit and the second macro unit; routing track resources are arranged in the first channel, and the routing track resources comprise a plurality of first routing tracks parallel to the direction of the first channel and a plurality of second routing tracks vertical to the direction of the first channel;
the first buffer array and the second buffer array are arranged in the first channel and are respectively arranged in a zigzag shape;
each buffer in the first buffer array is sequentially arranged on one first routing track in the first number of first routing tracks and is connected with one corresponding pin of the first macro cell through wiring along the first routing track;
each buffer in the second buffer array is sequentially arranged on one of the second number of first routing tracks and is connected with one corresponding pin of the second macro unit along the first routing track through wiring; the sum of the first number and the second number is less than or equal to the total number;
in each buffer array, at least one track rail displacement is arranged between adjacent buffers along the first track rail direction and the second track rail direction.
Preferably, the first number of first routing tracks and the second number of first routing tracks do not overlap with each other.
Preferably, the structure further comprises: a logic function unit;
the logic function unit is arranged outside the first channel; one or more pins of the first macro-cell and/or the second macro-cell are connected with the logic function unit through corresponding buffers in the first buffer array and/or the second buffer array.
Preferably, the logic function unit is also connected with one or more pins of other macro units.
Preferably, the structure further comprises: other buffers outside the first channel;
and one or more pins of the first macro unit and/or the second macro unit pass through corresponding buffers in the first buffer array and/or the second buffer array, are connected to other buffers, and are connected with the logic function unit.
According to the logic output pre-guiding method for the macro unit under the narrow channel layout, provided by the embodiment of the invention, the first buffer array and the second buffer array which are arranged in a broken line type are added through performing pre-guiding treatment on the first channel, and the pin logic outputs of the corresponding first macro unit and the second macro unit are guided by each buffer in the buffer arrays and are led out of the first channel, so that the layout of the corresponding logic function units outside the channel is facilitated, and the wiring connection of the logic function units and the pins through the buffers is realized, so that the wiring track resources of the channel under the narrow channel layout are reasonably utilized to the maximum extent, and the limited wiring track resources meet the logic output requirements to the maximum extent.
Drawings
Fig. 1 is a flowchart of a logic output pre-steering method for a macro cell under a narrow channel layout according to an embodiment of the present invention;
FIG. 2 is a flow chart of method steps for pre-steering processing according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of two adjacent macro cells under a narrow channel layout according to an embodiment of the present invention;
FIG. 4 is a schematic diagram showing the structures of two adjacent macro cells of a non-functional Physical cell (Physical only cells);
FIG. 5 is a schematic diagram of a logic output pre-steering structure of a macro cell in a narrow channel layout.
Detailed Description
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
The embodiment of the invention provides a logic output pre-guiding method of a macro unit under a narrow channel layout, which mainly comprises the following steps as shown in figure 1:
specifically, after the macro cells are laid out, the positions of the macro cells are determined. Each macro cell has respective output logic, and the routing track resources occupied by the output of each macro cell can be calculated according to the output logic.
In the channel between two adjacent macro-cells, there are available track tracks (tracks) including a first track in a parallel channel direction and a second track in a perpendicular channel direction. The first routing tracks and the second routing tracks are all multiple, the multiple first routing tracks are arranged in parallel, and are physically arranged on the same layer or different layers, and the multiple second routing tracks are also arranged in parallel, and are physically arranged on the same layer or different layers.
The pre-routing process is a process after the macro cell layout, and means that for any two or more macro cells with two or more pins having associated output logic, corresponding logic functional units are inserted into the channels for connecting the two or more pins. That is, for each adjacent first macro cell and second macro cell, it is determined whether the first channel to be inserted into the first channel between them has enough space and trace resource available, and if not, it means that the channel between the two adjacent macro cells cannot meet the trace resource requirement after layout.
If the requirement of routing track resources can be met, the logic function unit is directly inserted and then wiring is carried out, and if the requirement cannot be met, pre-guiding processing needs to be executed.
as shown in fig. 2, the pre-guiding process includes:
that is, the number of available track resources in the channel is determined first, and then the track resources are reasonably allocated for use.
The method for allocating the total number to the first number and the second number may specifically be: and determining the first number and the second number according to the number of pins of the first macro unit on one side of the first channel and the number of pins of the second macro unit on one side of the first channel. Namely, the distribution is performed according to the amount of the use requirement of the track resource of two adjacent macro units in the same channel. The total number may of course be equally distributed. In general, the sum of the first number and the second number is less than or equal to the total number.
that is, for a first pin of a first macro cell, a buffer is inserted into a first trace track nearest to the first macro cell along a second trace track corresponding to the first pin; and then, for a second pin of the first macro unit, inserting a buffer on a first routing track next closest to the first macro unit along a second routing track corresponding to the second pin, and so on until a first number of buffers are inserted, and then inserting buffers corresponding to the pins one by one in a direction close to the first macro unit one by one until the buffers corresponding to all the pins are completely inserted to form a first buffer array.
In each buffer array, at least one track rail displacement is arranged between adjacent buffers along the first track rail direction and the second track rail direction. The buffer inserted in this way constitutes a continuous or discontinuous broken line shape.
specifically, the forming process of the second buffer array is the same as that of the first buffer array, and is not described again.
after the buffer array is configured, the pins having the corresponding relationship are wired to the buffer ground input terminal.
In step 125, routing is performed along the first trace track to lead the output of each buffer out of the first channel, so as to lead the logic output of each pin of the first macro cell and the second macro cell out of the first channel.
Thus, logic outputs of all pins of the macro cell are directed out of the narrow channel with reasonable maximum utilization of narrow channel routing resources.
And step 130, after the pre-steering processing is performed on the first channel, performing layout and wiring connection of corresponding logic function units outside the first channel through the output of each buffer of the first buffer array and/or the second buffer array.
In this example, only the connection of the logic outputs of two adjacent macro-units is described, but it is needless to say that both the first macro-unit and the second macro-unit may have a logic function connection requirement with one or more pins of other macro-units, so that the logic function unit may also be connected with one or more pins of other macro-units.
In addition, other buffers can be arranged outside the first channel; one or more pins of the first macro unit and/or the second macro unit can be connected to other buffers after passing through the corresponding buffers in the first buffer array and/or the second buffer array, and then are connected with the logic function unit.
The logic output pre-steering method of the macro cell in the narrow channel layout is described above, and the logic output pre-steering structure of the macro cell in the narrow channel layout implemented by the method is described below.
As shown in fig. 3, the structure of two adjacent macro cells under the narrow channel layout is shown as the figure, and includes: a first macro-cell 1, a second macro-cell 2 and a first channel 3. The first macro-unit 1 and the second macro-unit 2 are two adjacent macro-units, and a first channel 3 is arranged between the first macro-unit 1 and the second macro-unit 2.
The first channel 3 has a trace track resource, which is distributed throughout the chip in physical design, but for the macro cell logical output, it is necessary to use the trace track resource in the first channel 3 for logical output. As shown, the line resource in the first channel 3 includes a plurality of first track tracks 41 parallel to the first channel direction and a plurality of second track tracks 42 perpendicular to the first channel direction.
In the back-end design process of an actual chip, some non-functional Physical cells (Physical cells) occupy the area in the channel, where the non-functional Physical cells are those that are not in the netlist and need to exist in the actual chip, such as a power ground IO, an IO for supplying power to the IO, and some substrates, well contact cells, and the like.
As shown in fig. 3 and 4, the non-functional physical unit 5 is occupied in the first channel 3, which makes the available track resources in the first channel 3 more strained. To this end, after the logic output pre-steering method is performed, a first buffer array 6 and a second buffer array (not shown) are formed in the first channel as shown in fig. 5.
As shown in fig. 3, 4, and 5, the first buffer array 6 and the second buffer array are disposed in the first channel 3 and are respectively arranged in a zigzag shape; the second buffer array is not shown because it is arranged in the same way as the first buffer array 6, except that the occupied track resources may be distributed more or less evenly or according to the output logic requirements. In case of evenly distributing the track resources occupied by both, the first buffer array 6 and the second buffer array can be considered to be symmetrically arranged.
Each buffer 61 in the first buffer array 6 is sequentially disposed on one first trace track 41 of the first trace tracks, and connected to one corresponding pin 11 of the first macro cell 1 along the first trace track 41 by wiring; similarly, each buffer in the second buffer array is sequentially disposed on one of the second number of first trace tracks, and is connected to a corresponding pin 21 of the second macro cell 2 by wiring along the first trace track. The first routing tracks of the first number are not overlapped with the first routing tracks of the second number.
In each buffer array, at least one track rail displacement is arranged between adjacent buffers along the first track rail direction and the second track rail direction.
The logic output pre-steering structure further comprises: a logic function unit; the logic function unit may be disposed at a suitable position outside the first channel 3 according to the actual situation of the layout, and thus the logic function unit is not separately shown in the drawing.
One or more pins of the first macro-unit 1 and/or the second macro-unit 2 are connected to the logic function unit via respective buffers in the first buffer array 6 and/or the second buffer array. The connection of this step is the same as the conventional wiring, and the wiring is only required to be arranged along the track rail, which is not shown in the figure.
Of course, for the first macro-unit and the second macro-unit, both of them may have a logic function connection requirement with one or more pins of other macro-units, so that the logic function unit may also be connected with one or more pins of other macro-units.
In addition, other buffers can be arranged outside the first channel; one or more pins of the first macro unit and/or the second macro unit can be connected to other buffers after passing through the corresponding buffers in the first buffer array and/or the second buffer array, and then are connected with the logic function unit.
According to the logic output pre-guiding method for the macro unit under the narrow channel layout, provided by the embodiment of the invention, the first buffer array and the second buffer array which are arranged in a broken line type are added through performing pre-guiding treatment on the first channel, and the pin logic outputs of the corresponding first macro unit and the second macro unit are guided by each buffer in the buffer arrays and are led out of the first channel, so that the layout of the corresponding logic function units outside the channel is facilitated, and the wiring connection of the logic function units and the pins through the buffers is realized, so that the wiring track resources of the channel under the narrow channel layout are reasonably utilized to the maximum extent, and the limited wiring track resources meet the logic output requirements to the maximum extent.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (9)
1. A logic output pre-guiding method of macro unit under narrow channel layout is characterized in that the logic output pre-guiding method of macro unit under narrow channel layout comprises the following steps:
after the macro cells are distributed, performing pre-winding processing on all the macro cells according to the output logics of all the macro cells, and determining whether the channel size of a channel between any two adjacent macro cells meets the requirement of routing track resources or not after the distribution;
when the channel size of a first channel between a first macro unit and a second macro unit which are adjacent does not meet the requirement of routing track resources, pre-guiding processing is carried out on the first channel;
wherein the pre-pilot processing specifically comprises:
determining the total number of first routing tracks parallel to the first channel direction in the first channel, and allocating the total number to be a first number and a second number; the sum of the first number and the second number is less than or equal to the total number;
inserting a buffer on one first routing track of a first number of first routing tracks in sequence corresponding to each pin according to the sequence of the pins of the first macro unit on one side of the first channel, and sequentially arranging the buffers on adjacent second routing tracks vertical to the channel direction, so as to form a first buffer array in a zigzag shape;
inserting a buffer on one first routing track of a second number of first routing tracks in sequence corresponding to each pin according to the sequence of the pins of the second macro unit on one side of the first channel, and sequentially arranging the buffers on adjacent second routing tracks vertical to the channel direction, so as to form a second buffer array in a zigzag shape;
routing a buffer connecting each pin of the first macro cell with one of the first buffer arrays along the second routing track, and routing a buffer connecting each pin of the second macro cell with one of the second buffer arrays;
routing along the first trace track to direct the output of each buffer out of the first channel, thereby directing the logical output of each pin of the first and second macro-cells out of the first channel;
after the pre-steering processing is executed on the first channel, the layout and wiring connection of the corresponding logic function unit is performed outside the first channel through the output of each buffer of the first buffer array and/or the second buffer array.
2. The method of claim 1, wherein the pre-routing process comprises: for any two or more pins of the macro-unit with relevant output logic, inserting a corresponding logic function unit in the channel for connecting the two or more pins.
3. The method as claimed in claim 2, wherein the step of determining whether the channel size of the channel between any two adjacent macro cells meets the requirement of routing track resources is specifically as follows:
it is determined whether the logical functional units to be inserted in each channel can be fully inserted in the channel.
4. The method according to claim 1, wherein the assigning the total number to the first number and the second number specifically comprises: and determining the first number and the second number according to the number of pins of the first macro unit on one side of the first channel and the number of pins of the second macro unit on one side of the first channel.
5. A logic output pre-steering structure for macro cells in a narrow channel layout, the structure comprising: a first macro-cell, a second macro-cell, a first channel, a first buffer array, and a second buffer array;
the first macro unit and the second macro unit are two adjacent macro units, and the first channel is arranged between the first macro unit and the second macro unit; routing track resources are arranged in the first channel, and the routing track resources comprise a plurality of first routing tracks parallel to the direction of the first channel and a plurality of second routing tracks vertical to the direction of the first channel;
the first buffer array and the second buffer array are arranged in the first channel and are respectively arranged in a zigzag shape;
each buffer in the first buffer array is sequentially arranged on one first routing track in the first number of first routing tracks and is connected with one corresponding pin of the first macro cell through wiring along the first routing track;
each buffer in the second buffer array is sequentially arranged on one of the second number of first routing tracks and is connected with one corresponding pin of the second macro unit along the first routing track through wiring; the sum of the first number and the second number is less than or equal to the total number;
in each buffer array, at least one track rail displacement is arranged between adjacent buffers along the first track rail direction and the second track rail direction.
6. The logic output pre-routing structure of claim 5, wherein the first number of first trace tracks and the second number of first trace tracks do not overlap with each other.
7. The logic output pre-steering structure of claim 5, further comprising: a logic function unit;
the logic function unit is arranged outside the first channel; one or more pins of the first macro-cell and/or the second macro-cell are connected with the logic function unit through corresponding buffers in the first buffer array and/or the second buffer array.
8. The logic output pre-steering structure according to claim 7, wherein the logic functional unit is further connected to one or more pins of other macro-units.
9. The logic output pre-steering structure of claim 7, further comprising: other buffers outside the first channel;
and one or more pins of the first macro unit and/or the second macro unit pass through corresponding buffers in the first buffer array and/or the second buffer array, are connected to other buffers, and are connected with the logic function unit.
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| CN202010887106.3A CN111859841A (en) | 2020-08-28 | 2020-08-28 | Logic output pre-guiding method and structure of macro unit under narrow channel layout |
| PCT/CN2020/128250 WO2022041494A1 (en) | 2020-08-28 | 2020-11-12 | Method and structure for pre-guiding logic outputs of macro cells in narrow channel layout |
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| CN202010887106.3A CN111859841A (en) | 2020-08-28 | 2020-08-28 | Logic output pre-guiding method and structure of macro unit under narrow channel layout |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112699631A (en) * | 2021-01-14 | 2021-04-23 | 安徽省东科半导体有限公司 | Design optimization method for solving problem of wiring congestion at corner of wiring channel |
| WO2022041494A1 (en) * | 2020-08-28 | 2022-03-03 | 东科半导体(安徽)股份有限公司 | Method and structure for pre-guiding logic outputs of macro cells in narrow channel layout |
| CN114492290A (en) * | 2022-04-06 | 2022-05-13 | 飞腾信息技术有限公司 | Power switch planning method, device, equipment and storage medium of chip |
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| JPH08213466A (en) * | 1995-02-07 | 1996-08-20 | Kawasaki Steel Corp | Semiconductor integrated circuit |
| JP2000114468A (en) * | 1998-10-06 | 2000-04-21 | Seiko Epson Corp | Semiconductor integrated circuit |
| JP2000236025A (en) * | 1999-02-15 | 2000-08-29 | Matsushita Electric Ind Co Ltd | Clock skew adjusting circuit and layout design thereof |
| US6492205B1 (en) * | 2000-12-26 | 2002-12-10 | Taiwan Semiconductor Manufacturing Company | Utilization of macro power routing area for buffer insertion |
| US8375347B2 (en) * | 2009-05-12 | 2013-02-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Driven metal critical dimension (CD) biasing |
| CN111859841A (en) * | 2020-08-28 | 2020-10-30 | 安徽省东科半导体有限公司 | Logic output pre-guiding method and structure of macro unit under narrow channel layout |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022041494A1 (en) * | 2020-08-28 | 2022-03-03 | 东科半导体(安徽)股份有限公司 | Method and structure for pre-guiding logic outputs of macro cells in narrow channel layout |
| CN112699631A (en) * | 2021-01-14 | 2021-04-23 | 安徽省东科半导体有限公司 | Design optimization method for solving problem of wiring congestion at corner of wiring channel |
| WO2022151787A1 (en) * | 2021-01-14 | 2022-07-21 | 东科半导体(安徽)股份有限公司 | Design optimization method for solving problem of wiring congestion at corner of wiring channel |
| CN114492290A (en) * | 2022-04-06 | 2022-05-13 | 飞腾信息技术有限公司 | Power switch planning method, device, equipment and storage medium of chip |
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Address after: Building 38, digital Silicon Valley International Industrial Park, 999 Yinhuang East Road, Dangtu County, Ma'anshan City, Anhui Province 243100 Applicant after: Dongke semiconductor (Anhui) Co.,Ltd. Address before: Building 38, digital Silicon Valley International Industrial Park, 999 Yinhuang East Road, Dangtu County, Ma'anshan City, Anhui Province 243100 Applicant before: ANHUI DONGKE SEMICONDUCTOR Co.,Ltd. |
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| CB02 | Change of applicant information |