CN114492290B - Power switch planning method, device, equipment and storage medium of chip - Google Patents

Power switch planning method, device, equipment and storage medium of chip Download PDF

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Publication number
CN114492290B
CN114492290B CN202210352721.3A CN202210352721A CN114492290B CN 114492290 B CN114492290 B CN 114492290B CN 202210352721 A CN202210352721 A CN 202210352721A CN 114492290 B CN114492290 B CN 114492290B
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power switch
switch unit
planned
information
sample
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CN114492290A (en
Inventor
孙永丰
栾晓琨
蒋剑锋
陈占之
金文江
李天丽
边少鲜
左博敏
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Phytium Technology Co Ltd
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Phytium Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

Abstract

The application provides a power switch planning method, a power switch planning device, power switch planning equipment and a storage medium of a chip, and belongs to the technical field of chip design. The method comprises the following steps: acquiring unit planning information of a plurality of programmable power switch units in a target chip, wherein the unit planning information comprises: position information of the power switch unit can be planned; obtaining arrangement information of a sample power switch unit according to the unit planning information, wherein the sample power switch unit is any one of a plurality of programmable power switch units; and determining the arrangement information of each power switch unit to be planned according to the arrangement information of the sample power switch units and the position information of each power switch unit to be planned, wherein the power switch unit to be planned is a power switch unit except the sample power switch unit in the plurality of power switch units which can be planned. The planning efficiency can be improved.

Description

Power switch planning method, device, equipment and storage medium of chip
Technical Field
The present disclosure relates to the field of chip design technologies, and in particular, to a power switch planning method, device, apparatus, and storage medium for a chip.
Background
In the design process of a chip, in order to reduce the power consumption of the chip, the chip is generally divided into a plurality of areas, and when a certain area in the chip does not work, the power supply to the chip in the area can be reduced or the chip in the area is directly powered off, so that the reduction of the power consumption is realized.
In the prior art, in the design of dividing the chip into areas, the adopted technical means is generally to determine each area in the chip one by one, so as to determine whether the area is used as an area that can be controlled by a Power Switch (Power Switch) unit.
However, this method consumes a lot of time during the planning process, and is very inefficient in the design requiring a lot of power switch unit planning, and the adoption of the independent planning method among the plurality of power switch units may result in uneven power supply as a whole, easily cause circuit violation, and require extra time for repairing.
Disclosure of Invention
The application aims to provide a power switch planning method, a power switch planning device, power switch planning equipment and a storage medium of a chip, and planning efficiency can be improved.
The embodiment of the application is realized as follows:
in one aspect of the embodiments of the present application, a method for planning a power switch of a chip is provided, including:
acquiring unit planning information of a plurality of programmable power switch units in a target chip, wherein the unit planning information comprises: position information of the power switch unit can be planned;
obtaining arrangement information of a sample power switch unit according to the unit planning information, wherein the sample power switch unit is any one of a plurality of programmable power switch units;
and determining the arrangement information of each power switch unit to be planned according to the arrangement information of the sample power switch units and the position information of each power switch unit to be planned, wherein the power switch unit to be planned is a power switch unit except the sample power switch unit in the plurality of power switch units which can be planned.
Optionally, determining the arrangement information of each power switch unit to be planned according to the arrangement information of the sample power switch units and the position information of each power switch unit to be planned includes:
acquiring position information of a first target element in a sample power switch unit according to the arrangement information of the sample power switch unit;
determining the position information of a second target element in the power switch unit to be planned according to the position information of the power switch unit to be planned;
determining a relative distance of the second target element from the first target element;
and determining the arrangement information of each power switch unit to be planned according to the relative distance between the second target element and the first target element and the arrangement information of the sample power switch units.
Optionally, determining the relative distance of the second target element from the first target element comprises:
determining the abscissa distance of the second target element from the first target element;
determining the vertical coordinate distance between the second target element and the first target element;
the abscissa distance and the ordinate distance are taken as relative distances.
Optionally, determining the arrangement information of each power switch unit to be planned according to the relative distance between the second target element and the first target element and the arrangement information of the sample power switch units, including:
superposing the abscissa and the abscissa distance of each element in the sample power switch unit to obtain the abscissa of the corresponding element in the power switch unit to be planned;
superposing the vertical coordinate of each element in the sample power switch unit with the vertical coordinate distance to obtain the vertical coordinate of the corresponding element in the power switch unit to be planned;
and taking the attribute information of each element in the sample power switch unit as the attribute information of the corresponding element in the power switch unit to be planned.
Optionally, determining the position information of the second target element in the power switch unit to be planned according to the position information of the power switch unit to be planned includes:
and determining the position information of the second target element according to the position information of the boundary line of the power switch unit to be planned and the position information of the routing track in the area where the power switch unit to be planned is located.
Optionally, determining the position information of the second target element according to the position information of the boundary line of the power switch unit to be planned and the position information of the routing track in the area where the power switch unit to be planned is located includes:
and if the distance between the first routing track with the minimum distance from the boundary line in the power switch unit to be planned and the boundary line is greater than or equal to the preset distance, determining that the position of the first routing track is the position of the second target element.
Optionally, determining the position information of the second target element according to the position information of the boundary line of the power switch unit to be planned and the position information of the routing track in the area where the power switch unit to be planned is located includes:
and if the distance between the first routing track with the minimum distance from the boundary line in the power switch unit to be planned and the boundary line is less than the preset distance, determining that the position of a second routing track adjacent to the first routing track is the position of a second target element.
Optionally, the boundary line of the power switch unit to be planned is a boundary line of the bottom of the power switch unit to be planned.
Optionally, obtaining the arrangement information of the sample power switch unit according to the unit planning information includes:
according to the information to be planned of the sample power switch unit, acquiring position information of a boundary line of the sample power switch unit, position information of a routing track in an area where the sample power switch unit is located and relative distances of elements in the sample power switch unit;
obtaining position information of a first target element in the arrangement information according to the position information of the boundary line of the sample power switch unit and the position information of the routing track in the area where the sample power switch unit is located;
and obtaining the position information of each element except the first target element in the arrangement information according to the relative distance of each element in the sample power switch unit and the position information of the first target element.
Optionally, determining the arrangement information of each power switch unit to be planned according to the arrangement information of the sample power switch units and the position information of each power switch unit to be planned, including:
obtaining the relative distance between each element in the sample power switch unit and the first target element from the arrangement information of the sample power switch unit;
acquiring position information of a second target element in a power switch unit to be planned;
and determining the arrangement information of the power switch unit to be planned according to the relative distance between each element in the sample power switch unit and the first target element in the sample power switch unit and the position information of the second target element.
In another aspect of the embodiments of the present application, a power switch planning apparatus for a chip is provided, which includes: the system comprises an acquisition module, a sample planning module and an overall planning module;
an obtaining module, configured to obtain unit planning information of a plurality of programmable power switch units in a target chip, where the unit planning information includes: position information of the power switch unit can be planned;
the sample planning module is used for obtaining the arrangement information of the sample power switch unit according to the unit planning information, wherein the sample power switch unit is any one of a plurality of programmable power switch units;
and the integral planning module is used for determining the arrangement information of each power switch unit to be planned according to the arrangement information of the sample power switch units and the position information of each power switch unit to be planned, wherein the power switch unit to be planned is a power switch unit except the sample power switch unit in the plurality of power switch units which can be planned.
Optionally, the overall planning module is specifically configured to obtain position information of a first target element in the sample power switch unit according to the arrangement information of the sample power switch unit; determining the position information of a second target element in the power switch unit to be planned according to the position information of the power switch unit to be planned; determining a relative distance of the second target element from the first target element; and determining the arrangement information of each power switch unit to be planned according to the relative distance between the second target element and the first target element and the arrangement information of the sample power switch units.
Optionally, the overall planning module is specifically configured to determine an abscissa distance between the second target element and the first target element; determining the vertical coordinate distance between the second target element and the first target element; the abscissa distance and the ordinate distance are taken as relative distances.
Optionally, the overall planning module is specifically configured to superimpose the abscissa and the abscissa distance of each element in the sample power switch unit to obtain the abscissa of the corresponding element in the power switch unit to be planned; superposing the vertical coordinate of each element in the sample power switch unit with the vertical coordinate distance to obtain the vertical coordinate of the corresponding element in the power switch unit to be planned; and taking the attribute information of each element in the sample power switch unit as the attribute information of the corresponding element in the power switch unit to be planned.
Optionally, the overall planning module is specifically configured to determine the position information of the second target element according to the position information of the boundary line of the power switch unit to be planned and the position information of the routing track in the area where the power switch unit to be planned is located.
Optionally, the overall planning module is specifically configured to determine that the position of the first routing track is the position of the second target element if the distance between the first routing track in the power switch unit to be planned, which has the smallest distance from the boundary line, and the boundary line is greater than or equal to a preset distance.
Optionally, the overall planning module is specifically configured to determine that a position of a second routing track adjacent to the first routing track is a position of a second target element if a distance between the first routing track and the boundary line, which is the smallest distance between the first routing track and the boundary line in the power switch unit to be planned, is smaller than a preset distance.
Optionally, the overall planning module is specifically configured to obtain, according to information to be planned of the sample power switch unit, position information of a boundary line of the sample power switch unit, position information of a routing track in an area where the sample power switch unit is located, and a relative distance between each element in the sample power switch unit; obtaining position information of a first target element in the arrangement information according to the position information of the boundary line of the sample power switch unit and the position information of the routing track in the area where the sample power switch unit is located; and obtaining the position information of each element except the first target element in the arrangement information according to the relative distance of each element in the sample power switch unit and the position information of the first target element.
Optionally, the overall planning module is specifically configured to obtain, from the arrangement information of the sample power switch unit, a relative distance between each element in the sample power switch unit and the first target element; acquiring position information of a second target element in a power switch unit to be planned; and determining the arrangement information of the power switch unit to be planned according to the relative distance between each element in the sample power switch unit and the first target element in the sample power switch unit and the position information of the second target element.
In another aspect of the embodiments of the present application, there is provided a computer device, including: the power switch planning method comprises the steps of a memory and a processor, wherein a computer program capable of running on the processor is stored in the memory, and when the processor executes the computer program, the power switch planning method of the chip is realized.
In another aspect of the embodiments of the present application, a computer-readable storage medium is provided, where a computer program is stored on the storage medium, and when the computer program is executed by a processor, the steps of the power switch planning method for the chip are implemented.
The beneficial effects of the embodiment of the application include:
in a power switch planning method, device, equipment, and storage medium of a chip provided in an embodiment of the present application, unit planning information of a plurality of programmable power switch units in a target chip may be acquired, where the unit planning information includes: position information of the power switch unit can be planned; obtaining arrangement information of a sample power switch unit according to the unit planning information, wherein the sample power switch unit is any one of a plurality of programmable power switch units; and determining the arrangement information of each power switch unit to be planned according to the arrangement information of the sample power switch units and the position information of each power switch unit to be planned, wherein the power switch unit to be planned is a power switch unit except the sample power switch unit in the plurality of power switch units which can be planned. The layout information of each power switch unit to be planned can be obtained through the layout information of the sample power switch unit and the position information of each power switch unit to be planned, and then each power switch unit to be planned of each target chip can be planned more quickly, accordingly, the planning efficiency of the target chip can be improved, the possibility of circuit violation is reduced, and the planning and design efficiency of the circuit is improved. Meanwhile, the problems of omission and the like of the power switch unit in the cutting process due to non-advanced planning can be avoided, and extra waste caused by errors is avoided.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a target chip according to an embodiment of the present disclosure;
fig. 2 is a schematic flowchart of a power switch planning method of a chip according to an embodiment of the present disclosure;
fig. 3 is a schematic flowchart of a power switch planning method of a chip according to an embodiment of the present disclosure;
fig. 4 is a schematic flowchart of a power switch planning method for a chip according to an embodiment of the present disclosure;
fig. 5 is a schematic flowchart of a power switch planning method of a chip according to an embodiment of the present disclosure;
fig. 6 is a schematic flowchart of a power switch planning method of a chip according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a target chip planning result provided in the embodiment of the present application;
fig. 8 is a schematic structural diagram of a power switch planning apparatus of a chip according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of a computer device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures.
In the description of the present application, it is noted that the terms "first", "second", "third", and the like are used merely for distinguishing between descriptions and are not intended to indicate or imply relative importance.
In the design process of a chip, in order to improve the performance of an integrated circuit to which the chip is applied, it is generally necessary to design a chip with lower power consumption. In order to reduce the power consumption of the chip, the technical scheme adopted in the prior art may specifically be to reduce the power consumption of the whole chip by turning off the power supply voltage of a certain region or a certain module that is temporarily not used in the chip. In the process of turning off the power supply voltage of the chip, the turning-off position in the chip can be determined through the planning of each power switch unit based on the planning of the power switch units, so that the power supply turning-off operation of the area where the turning-off position is located is realized.
In the prior art, there are two main ways to plan a power switch:
firstly, each power switch unit is directly planned, and the power switch units are planned one by one in a circulating mode.
However, the planning of a huge number of power switch units cannot be realized by adopting the scheme, which results in long cycle and low efficiency, and some power lines and holes may even exceed the range of the power switch units, which wastes a lot of wiring resources, may also cause partial local DRC (Design Rule Control) violation, may take time to process the problems, and the whole Design may cause congestion due to the shortage of wiring resources, thereby causing difficult timing convergence.
Secondly, power supply planning is carried out according to the size of the whole plane layout (Floorplan) in the chip, compensation and space size of each layer in the chip need to be defined in the planning process, parts except the power supply switch unit can be cut after the global definition is finished, and a preset script in a computer can be adopted in the execution process.
However, the scheme cuts the power supply part outside the area of each power switch unit, and removes redundant power lines, so that the process is complicated and is not easy to operate; in addition, the number of power lines of each layer in each power switch unit planned in the method is not consistent, so that the violation condition of the circuit can be caused, and the repair time of the violation condition is longer and the risk is higher for the power switch units with large number; in addition, by adopting the scheme, the switching power supply unit is easy to be programmed in a gap between the static random access memory or other relevant parts of the chip, so that a large amount of manpower and material resources are consumed in power supply programming design and inspection.
In order to solve the problems in the prior art, the application provides a power switch planning method for a chip, and the planning of other switch units can be rapidly completed by planning a sample power switch unit and based on the position relationship between the sample power switch unit and other switch units needing to be planned, so that the various problems in the prior art can be simultaneously solved, and the problems of circuit violation and the like are avoided while the planning efficiency is greatly improved.
The following first explains a specific structure of a target chip involved in the embodiments of the present application.
Fig. 1 is a schematic structural diagram of a target chip provided in an embodiment of the present application, please refer to fig. 1, where the target chip may be, for example, an electronic chip applied in a terminal device, and the terminal device may be, for example, an electronic device such as a notebook, a mobile phone, a computer, or a portable device, and the present application is not limited specifically herein. The target chip may have a multi-layer structure, for example, a three-layer structure (an M1 layer, an M2 layer, and an M3 layer), where the M1 layer may be configured in advance when the target chip leaves a factory, and may not be specifically programmed, and specifically, the M2 layer and the M3 layer may be specifically programmed respectively when the target chip is programmed, and one of the layers shown in fig. 1, for example, may be the M2 layer.
Optionally, in the level of the target chip, there are a plurality of different dyed routing tracks for arranging the power lines, in this embodiment, two different dyed routing tracks are taken as an example, in order to distinguish color differences, different colors are replaced by lines with different thicknesses in fig. 1, a plurality of two different routing tracks may be alternately distributed in the M2 layer, holes may be provided on the routing tracks, the power lines may be arranged by passing the power lines through the holes on the routing tracks, positions of the routing tracks are arranged in advance, for example, the routing tracks may be arranged alternately, when planning the power switch units, each power switch unit may be in a rectangular shape, and each power switch unit may include a part of the routing track. The line disposed on the track may be the power line or other types of wires, and is not limited in particular.
As an example of the range of the sample power switch unit 110 (a part is shown by a dotted line in fig. 1) in fig. 1, it can be seen that, in an area where the sample power switch unit is located, a plurality of trace tracks, specifically two types of trace tracks with different thicknesses, are included, and the longitudinal direction and the transverse direction are respectively arranged in a staggered manner, and when the sample power switch unit 110 is arranged, elements such as a power line of the sample power switch unit can be arranged on the trace tracks in the area.
It should be noted that the chip structure shown in fig. 1 is only one example, and when the chip structure is actually planned, the chip structure can be planned in a corresponding planning manner according to a specific structure of an actual chip, and the chip structure is not limited to the above structure, for example: more levels, more trace tracks, etc. may be included.
The following explains a specific implementation process of the power switch planning method of the chip provided in the embodiment of the present application based on the actual structure of the target chip.
Fig. 2 is a schematic flowchart of a method for planning a power switch of a chip according to an embodiment of the present disclosure, and please refer to fig. 2, an execution main body of the method may be a computer device. The method comprises the following steps:
s210: and acquiring unit planning information of a plurality of programmable power switch units in the target chip.
Wherein the unit planning information includes: the position information of the power switching unit can be programmed.
Optionally, a plurality of programmable power switch units may be disposed in the target chip, and the programmable power switch units have corresponding unit programming information.
The unit planning information may specifically include information such as position information of the programmable power switch units, relative positions of elements in each programmable power switch unit, the number of elements in each programmable power switch unit, and attributes in each programmable power switch unit.
The position information of the programmable power switch unit may specifically be a specific position of the programmable power switch unit in the target chip; each programmable power switch unit may include a plurality of elements, and the relative position of the elements in each programmable power switch unit may specifically be a relative position or a relative distance between different elements, or the like; the number of elements in each programmable power switch unit may specifically be the total number of elements included in the programmable power switch unit; the attribute of each programmable power switch unit may specifically be related information such as a type, a color, or a manufacturing material of an element in the unit, and information such as a size of the unit itself, and may be set correspondingly according to an actual requirement, which is not limited specifically herein.
It should be noted that the unit planning information of the plurality of programmable power switch units may be predetermined information, and may be stored in a memory of the computer, or may be input into the computer from another device, and the information may be actively acquired based on the above method.
Alternatively, the cell planning information may be stored in a memory of the computer specifically in a DEF (Design Exchange Format).
S220: and obtaining the arrangement information of the sample power switch unit according to the unit planning information.
Wherein the sample power switch unit is any one of a plurality of programmable power switch units.
Alternatively, the sample power switch unit may be any one of a plurality of programmable power switch units manually selected by an operator, or any one of a plurality of programmable power switch units automatically randomly selected, without limitation.
For example: if the target chip includes 1000 programmable power switch units, and if the programmable power switch unit a is used as the sample power switch unit, the other programmable power switch units except a are all to-be-programmed power switch units.
The arrangement information of the sample power switch unit may specifically include an arrangement situation of each element on the sample power switch unit on the target chip, for example: the power line and other elements in the sample power switch unit are specifically disposed on which trace track of the area where the sample power switch unit is located.
Optionally, after the unit planning information is obtained, the arrangement information of the sample power switch units may be determined based on the relative positions of the elements in each programmable power switch unit, the number of the elements in each programmable power switch unit, and other information in the unit planning information.
S230: and determining the arrangement information of each power switch unit to be planned according to the arrangement information of the sample power switch units and the position information of each power switch unit to be planned.
Optionally, the power switch unit to be programmed is a power switch unit other than the sample power switch unit in the plurality of programmable power switch units. That is, the programmable power switch unit corresponds to a set of each to-be-programmed power switch unit and the sample power switch unit.
After the arrangement information of the sample power switch units and the position information of each power switch unit to be planned are respectively determined, the arrangement information of the power switch unit to be planned can be obtained according to the arrangement information of the sample power switch units and the position information of any power switch unit to be planned, and correspondingly, the arrangement information of each power switch unit to be planned can be respectively determined and obtained by adopting the above mode.
The arrangement information of the power switch unit to be planned may include the arrangement of each element on the target chip, for example: the power line or other elements in the power switch unit to be programmed are specifically arranged on which routing track of the target chip.
In the power switch planning method for a chip provided by the embodiment of the application, unit planning information of a plurality of programmable power switch units in a target chip can be acquired, and the unit planning information includes: position information of the programmable power switch unit; obtaining arrangement information of a sample power switch unit according to the unit planning information, wherein the sample power switch unit is any one of a plurality of programmable power switch units; and determining the arrangement information of each power switch unit to be planned according to the arrangement information of the sample power switch units and the position information of each power switch unit to be planned, wherein the power switch unit to be planned is a power switch unit except the sample power switch unit in the plurality of power switch units which can be planned. The layout information of each power switch unit to be planned can be obtained through the layout information of the sample power switch unit and the position information of each power switch unit to be planned, and then each power switch unit to be planned of each target chip can be planned more quickly, accordingly, the planning efficiency of the target chip can be improved, the possibility of circuit violation is reduced, and the planning and design efficiency of the circuit is improved. Meanwhile, the problems of omission and the like of the power switch unit in the cutting process due to non-advanced planning can be avoided, and extra waste caused by errors is avoided.
Another specific implementation process of the power switch planning method of the chip provided in the embodiment of the present application is explained below.
Fig. 3 is a schematic flowchart of a power switch planning method for a chip according to an embodiment of the present application, please refer to fig. 3, which determines arrangement information of each to-be-planned power switch unit according to arrangement information of a sample power switch unit and position information of each to-be-planned power switch unit, and includes:
s310: and acquiring the position information of the first target element in the sample power switch unit according to the arrangement information of the sample power switch unit.
Alternatively, the first target element may be any one of the elements in the sample power switch unit, for example: any one power line or other electrical line, etc., is not particularly limited herein.
The position information of the first target element may specifically be an arrangement position of the first target element in the target chip, for example: and the like, specifically the position on the track, and the like.
After the arrangement information of the sample power switch unit is obtained, the position information of the first target element in the sample power switch unit can be obtained from the arrangement information.
That is, after the arrangement condition of the sample power switch unit on the target chip is obtained, the specific arrangement position of the first target element in the sample power switch unit can be determined.
S320: and determining the position information of the second target element in the power switch unit to be planned according to the position information of the power switch unit to be planned.
Alternatively, the second target element may be any one of the elements of the power switch unit to be programmed, which second target element must correspond to the first target element, for example: if the first target element is the first power line in the sample power switch unit, the second target element is the first power line in the power switch unit to be programmed.
The position information of the second target element may specifically be an arrangement position of the second target element in the target chip, for example: and the like, specifically the position on the track, and the like.
After the arrangement information of the power switch unit to be planned is obtained, the position information of the second target element in the power switch unit to be planned can be obtained from the arrangement information.
It should be noted that, the above two steps of S310 and S320 may be performed simultaneously or sequentially without limitation, and fig. 3 illustrates the simultaneous operation as an example.
S330: a relative distance of the second target element from the first target element is determined.
Alternatively, after obtaining the first target element and the second target element respectively, a relative distance between the second target element and the first target element may be calculated, where the relative distance may be a distance of a difference in position between the second target element and the first target element in the target chip.
S340: and determining the arrangement information of each power switch unit to be planned according to the relative distance between the second target element and the first target element and the arrangement information of the sample power switch units.
Optionally, after the relative distance between the second target element and the first target element and the arrangement information of the sample power switch unit are respectively determined, the relevant information of other elements in the power switch unit to be planned may be determined, and then the arrangement information of the power switch unit to be planned may be obtained.
The above method can be adopted to sequentially and respectively determine the arrangement information of each power switch unit to be planned.
In the power switch planning method for the chip provided by the embodiment of the application, the position information of a first target element in a sample power switch unit can be obtained according to the arrangement information of the sample power switch unit; determining the position information of a second target element in the power switch unit to be planned according to the position information of the power switch unit to be planned; determining a relative distance of the second target element from the first target element; and determining the arrangement information of each power switch unit to be planned according to the relative distance between the second target element and the first target element and the arrangement information of the sample power switch units. In the process of determining the arrangement information of each power switch unit to be planned, the arrangement information can be determined specifically based on a target element, that is, a relative distance between a first target element and a second target element is determined first, so that the arrangement information of the power switch unit to be planned is obtained according to the relative distance and the arrangement information of the sample power switch unit, and the arrangement information can be determined more accurately and quickly through the relative distance of the elements, so that the arrangement information of each power switch unit to be planned is obtained more efficiently.
Next, a further specific implementation process of the power switch planning method of the chip provided in the embodiment of the present application is explained.
Fig. 4 is a schematic flowchart of a power switch planning method of a chip according to an embodiment of the present application, please refer to fig. 4, in which determining a relative distance between a second target element and a first target element includes:
s410: the abscissa distance of the second target element from the first target element is determined.
S420: a vertical coordinate distance of the second target element from the first target element is determined.
Alternatively, after the position information of the first target element and the position information of the second target element are respectively determined, coordinates where the first target element and the second target element are located may be respectively determined based on the position information, and if the target element is a power line, the coordinates may be specifically coordinates of a starting point of the power line in the programmable power switch unit.
After coordinates of the first target element and the second target element are obtained respectively, the abscissa distance can be obtained according to the abscissa of the second target element and the abscissa of the first target element; the ordinate distance may be derived from the ordinate of the second target element and the ordinate of the first target element.
The specific calculation formula is as follows:
△X=x2-x1；
△Y=y2-y1；
wherein the first target element has coordinates of (x)1，y1) The coordinates of the second target element are (x)2，y2) DeltaX is the abscissa distance and DeltaY is the ordinate distance.
S430: the abscissa distance and the ordinate distance are taken as relative distances.
Alternatively, after determining the abscissa and ordinate distances, respectively, the relative distance may be obtained, which may be expressed as (Δ X, Δ Y).
On the basis of the above determination of the relative distances, the arrangement information of the power switch units to be planned can be determined in the following manner.
Optionally, determining the arrangement information of each power switch unit to be planned according to the relative distance between the second target element and the first target element and the arrangement information of the sample power switch units, including: superposing the abscissa and the abscissa distance of each element in the sample power switch unit to obtain the abscissa of the corresponding element in the power switch unit to be planned; superposing the vertical coordinate and the vertical coordinate distance of each element in the sample power switch unit to obtain the vertical coordinate of the corresponding element in the power switch unit to be planned; and taking the attribute information of each element in the sample power switch unit as the attribute information of the corresponding element in the power switch unit to be planned.
After determining the relative distance between the second target element and the first target element, the determination of the arrangement information of each power switch unit to be planned may be performed based on the relative distance and the arrangement information of the sample power switch units.
Specifically, the positions of all elements in each power switch unit to be planned can be determined after the horizontal and vertical coordinates of the elements are obtained, and specifically, the horizontal coordinates and the horizontal coordinate distances of each element in the sample power switch unit can be superposed to obtain the horizontal coordinates of the corresponding elements in the power switch unit to be planned; and superposing the vertical coordinate of each element in the sample power switch unit with the vertical coordinate distance to obtain the vertical coordinate of the corresponding element in the power switch unit to be planned.
The specific formula is as follows:
X0=x0+△X；
Y0=y0+△Y；
wherein the position of any element in the sample power switch unit is (x)0，y0) The position of the element corresponding to the element in each power switch to be planned is (X)0，Y0）。
Based on the calculation mode, the horizontal and vertical coordinates of each element in the power switch unit to be planned can be calculated respectively.
For the attribute information, the attribute information is not usually changed with the change of the position, and the attribute information of each element in the sample power switch unit can be used as the attribute information of the corresponding element in the power switch unit to be planned.
After the attribute information and the horizontal and vertical coordinates of each element in any power switch unit to be planned are respectively determined, the arrangement information of the power switch unit to be planned can be determined, and then the arrangement information of each power switch unit to be planned can be respectively determined.
Optionally, determining the position information of the second target element in the power switch unit to be planned according to the position information of the power switch unit to be planned includes: and determining the position information of the second target element according to the position information of the boundary line of the power switch unit to be planned and the position information of the routing track in the area where the power switch unit to be planned is located.
When the position information of the second target element is determined, the specific position of the second target element may be specifically determined according to the position information of the routing track in the area where the power switch unit to be planned is located and the position relationship of the position information of the boundary line of the power switch unit to be planned.
The position information of the routing track in the area where the power switch unit to be planned is located may be a specific position coordinate range of the routing track, and the position information of the boundary line of the power switch unit to be planned may be a specific position coordinate range of four boundaries of the power switch unit to be planned.
Specifically, if the distance between the first routing track in the power switch unit to be planned, which has the minimum distance from the boundary line, and the boundary line is greater than or equal to a preset distance, it is determined that the position of the first routing track is the position of the second target element.
Wherein, the first trace track may be a trace track with a closest distance parallel to the boundary line to which the first trace track is compared, for example: if the boundary line of the power switch unit to be planned is the boundary line at the bottom of the power switch unit to be planned, the first routing track may be the first routing track from bottom to top in the power switch unit to be planned in the horizontal direction.
That is, after it is determined that the distance between the first trace track and the boundary line is greater than or equal to the preset distance, the position of the first trace track may be taken as the position of the second target element.
In contrast, if the distance between the first routing track in the power switch unit to be planned, which has the minimum distance from the boundary line, and the boundary line is smaller than the preset distance, it is determined that the position of the second routing track adjacent to the first routing track is the position of the second target element.
The second routing track may be a routing track parallel to and adjacent to the first routing track, and continuing to take the above example as an example, if the first routing track is in the horizontal direction, the first routing track in the power switch unit to be programmed is from bottom to top; the second trace track may be a second trace track from bottom to top in the power switch unit to be programmed in the horizontal direction.
It should be noted that, the arrangement of the first routing track and the second routing track is not limited thereto, and if the selected boundary lines are different, the corresponding routing tracks are also different, for example: if the first routing track is the top boundary line, the first routing track is a first routing track from top to bottom in the power switch unit to be planned, and the second routing track is a second routing track from top to bottom in the power switch unit to be planned; if the boundary line is the left boundary line, the first routing track is a first routing track from left to right in the power switch unit to be planned in the vertical direction, and the second routing track is a second routing track from left to right in the power switch unit to be planned in the vertical direction; if the boundary line is the right boundary line, the first routing track is a first routing track from right to left in the power switch unit to be planned in the vertical direction, and the second routing track is a second routing track from right to left in the power switch unit to be planned in the vertical direction.
In an actual target chip structure, the trace tracks may include a plurality of traces, which may be set in both horizontal and vertical directions, and when the trace tracks and the boundary lines are actually determined, the trace tracks and the boundary lines may be set correspondingly according to actual requirements, which is just an example.
In the power switch planning method for the chip provided in the embodiment of the application, if the boundary line of the power switch unit to be planned is the boundary line at the bottom of the power switch unit to be planned, the first routing track may be a first routing track from bottom to top in the power switch unit to be planned in the horizontal direction; and if the distance between the first routing track with the minimum distance from the boundary line in the power switch unit to be planned and the boundary line is less than the preset distance, determining that the position of a second routing track adjacent to the first routing track is the position of a second target element. The specific position of the second target element can be obtained more accurately and with reduced errors by determining the distance between the routing track and the boundary line, so that the DRC problem in subsequent cutting and other operations can be avoided, a part of power lines or holes can be prevented from being punched outside the power switch unit, and a large amount of repair of the power switch unit can be avoided.
As another alternative, the arrangement information of the power switch units to be programmed may also be determined in the following manner.
Fig. 5 is a schematic flowchart of a power switch planning method for a chip according to an embodiment of the present application, please refer to fig. 5, which determines arrangement information of each to-be-planned power switch unit according to arrangement information of a sample power switch unit and position information of each to-be-planned power switch unit, and includes:
s510: and obtaining the relative distance between each element in the sample power switch unit and the first target element from the arrangement information of the sample power switch unit.
Optionally, the method may be implemented in two ways in parallel with the foregoing S310-S330, and in the actual implementation process, one way of the two ways may be implemented.
Optionally, the arrangement information of the sample power switch unit may include a specific position (for example, a specific area arranged on the trace track) where each element in the sample power switch unit is arranged, that is, the relative distance between each element in the sample power switch unit and the first target element may be obtained based on the position of each element.
S520: and acquiring the position information of a second target element in the power switch unit to be planned.
Optionally, the position information of the second target element may be specifically determined according to unit planning information in the power switch unit to be planned.
S530: and determining the arrangement information of the power switch unit to be planned according to the relative distance between each element in the sample power switch unit and the first target element in the sample power switch unit and the position information of the second target element.
Optionally, after determining the relative distance between each element in the sample power switch unit and the first target element in the sample power switch unit and the position information of the second target element, the relative distance between each element in the power switch unit to be programmed and the second target element may be sequentially calculated based on the relative distance between each element in the sample power switch unit and the first target element in the sample power switch unit (the relative distances between the sample power switch unit and the corresponding elements in the power switch unit to be programmed are equal).
Furthermore, on the basis of the position information of the second target element, the position information of each element in the power switch unit to be planned can be respectively calculated, that is, the arrangement information of the power switch unit to be planned is obtained.
Optionally, after the information to be planned of the plurality of programmable power switch units in the target chip is obtained, the information may be output, so that the operator performs a specific operation, or the information is output to the chip processing device to perform a specific operation based on the planned situation, which is not limited herein.
Next, a further specific implementation process of the power switch planning method of the chip provided in the embodiment of the present application is explained.
Fig. 6 is a schematic flowchart of a power switch planning method for a chip according to an embodiment of the present application, please refer to fig. 6, where obtaining layout information of a sample power switch unit according to unit planning information includes:
s610: according to the information to be planned of the sample power switch unit, position information of a boundary line of the sample power switch unit, position information of a routing track in an area where the sample power switch unit is located and relative distances of elements in the sample power switch unit are obtained.
Optionally, the position information of the boundary line of the sample power switch unit, the position information of the trace track in the area where the sample power switch unit is located, and the relative distance of each element in the sample power switch unit may be determined according to the position information of the sample power switch unit, the relative position of the element in the sample power switch unit, and the attribute of the element in each sample power switch unit in the to-be-planned information of the sample power switch unit.
For example: obtaining position information of a boundary line of the sample power switch unit based on the position of the sample power switch unit in the target chip and the attribute (specifically, the size) of the sample power switch unit; the position information of the trace track in the area where the sample power switch unit is located and the relative distance of each element in the sample power switch unit can be determined according to the relative position of the element in the power switch unit.
S620: and obtaining the position information of the first target element in the arrangement information according to the position information of the boundary line of the sample power switch unit and the position information of the track in the area where the sample power switch unit is located.
Alternatively, after the position information of the boundary line of the sample power switch unit and the position information of the trace track in the area where the sample power switch unit is located are obtained, respectively, the position information of the first target element may be obtained based on the selected first target element. The specific determination method is the same as the aforementioned method for determining the second target element, and details are not repeated herein.
S630: and obtaining the position information of each element except the first target element in the arrangement information according to the relative distance of each element in the sample power switch unit and the position information of the first target element.
Optionally, after obtaining the relative distance between each element in the sample power switch unit and the position information of the first target element, the position information of each element except the first target element in the arrangement information may be obtained, and then the position of each element may be expressed by coordinates, so as to perform subsequent calculation.
It should be noted that, in the power off design, the whole power supply implementation can be divided into two parts, one is a normally open power supply and the other is a power off power supply. The normally open power supply is that the whole normally open power supply domain is connected whenever power is supplied. The power supply capable of being turned off controls whether the normally open power supply and the power supply capable of being turned off are conducted or not according to the working mode of the power supply switch unit. The power supply of unit is on can turn-off power supply in the whole design is directly received, and the power supply implementation method that this design provided is to normally open power supply, and the switch unit just is equivalent to middle bridge, and normally open power supply down supplies power through the top layer, at first is connected to all switch unit's normally open power supply on, then whether the operating condition according to the circuit realizes supplying power or cuts off to can turn-off power supply. The realization of the turn-off power supply is consistent with the realization method of a common power supply at ordinary times, so the most key of the whole power supply design is the realization of the normally-on power supply on the power supply switch. If the power supply wiring on the power switch cells is uniform, the power supply trend of the whole design is smooth and strong.
Fig. 7 is a schematic diagram of a target chip planning result provided in an embodiment of the present application, please refer to fig. 7, where fig. 7 takes 7 programmable power switch units (a dashed line in fig. 7 is a frame) as an example, where the first one on the left side may be used as a sample power switch unit 110, and the above method steps are performed to determine the arrangement information of the power switch units to be planned, so as to obtain a planning result.
The other power switch units are power switch units to be planned, and it can be obtained that different programmable power switch units are the same in size, but because the positions distributed in the target chip are not fixed, the relative positions of the wiring tracks included in each programmable power switch unit are not the same, so that it is necessary to determine, based on the positions of the wiring tracks, on which wiring track in the unit each element in each power switch to be planned should be arranged, and further after each element is arranged, the arrangement information of the unit to be planned can be obtained.
The following describes apparatuses, devices, and storage media corresponding to the method for implementing power switch planning of a chip provided in the present application, and specific implementation processes and technical effects thereof are referred to above, and will not be described again below.
Fig. 8 is a schematic structural diagram of a power switch planning apparatus of a chip according to an embodiment of the present application, and referring to fig. 8, the power switch planning apparatus includes: an acquisition module 810, a sample planning module 820 and an overall planning module 830;
an obtaining module 810, configured to obtain unit planning information of a plurality of programmable power switch units in a target chip, where the unit planning information includes: position information of the programmable power switch unit;
a sample planning module 820, configured to obtain arrangement information of a sample power switch unit according to the unit planning information, where the sample power switch unit is any one of a plurality of programmable power switch units;
and an overall planning module 830, configured to determine the arrangement information of each to-be-planned power switch unit according to the arrangement information of the sample power switch units and the position information of each to-be-planned power switch unit, where the to-be-planned power switch unit is a power switch unit except the sample power switch unit in the plurality of programmable power switch units.
Optionally, the overall planning module 830 is specifically configured to obtain, according to the arrangement information of the sample power switch unit, position information of a first target element in the sample power switch unit; determining the position information of a second target element in the power switch unit to be planned according to the position information of the power switch unit to be planned; determining a relative distance of the second target element from the first target element; and determining the arrangement information of each power switch unit to be planned according to the relative distance between the second target element and the first target element and the arrangement information of the sample power switch units.
Optionally, the overall planning module 830 is specifically configured to determine an abscissa distance between the second target element and the first target element; determining the vertical coordinate distance between the second target element and the first target element; the abscissa distance and the ordinate distance are taken as relative distances.
Optionally, the overall planning module 830 is specifically configured to superimpose the abscissa and the abscissa distance of each element in the sample power switch unit to obtain the abscissa of the corresponding element in the power switch unit to be planned; superposing the vertical coordinate of each element in the sample power switch unit with the vertical coordinate distance to obtain the vertical coordinate of the corresponding element in the power switch unit to be planned; and taking the attribute information of each element in the sample power switch unit as the attribute information of the corresponding element in the power switch unit to be planned.
Optionally, the overall planning module 830 is specifically configured to determine the position information of the second target element according to the position information of the boundary line of the power switch unit to be planned and the position information of the routing track in the area where the power switch unit to be planned is located.
Optionally, the overall planning module 830 is specifically configured to determine that the position of the first routing track is the position of the second target element if the distance between the first routing track in the power switch unit to be planned, which has the smallest distance from the boundary line, and the boundary line is greater than or equal to a preset distance.
Optionally, the overall planning module 830 is specifically configured to determine that a position of a second routing track adjacent to the first routing track is a position of a second target element if a distance between the first routing track and the boundary line, which is the smallest distance between the first routing track and the boundary line, in the power switch unit to be planned is smaller than a preset distance.
Optionally, the overall planning module 830 is specifically configured to obtain, according to information to be planned of the sample power switch unit, position information of a boundary line of the sample power switch unit, position information of a routing track in an area where the sample power switch unit is located, and a relative distance between each element in the sample power switch unit; obtaining position information of a first target element in the arrangement information according to the position information of the boundary line of the sample power switch unit and the position information of the routing track in the area where the sample power switch unit is located; and obtaining the position information of each element except the first target element in the arrangement information according to the relative distance of each element in the sample power switch unit and the position information of the first target element.
Optionally, the overall planning module 830 is specifically configured to obtain, from the arrangement information of the sample power switch unit, the relative distance between each element in the sample power switch unit and the first target element; acquiring position information of a second target element in a power switch unit to be planned; and determining the arrangement information of the power switch unit to be planned according to the relative distance between each element in the sample power switch unit and the first target element in the sample power switch unit and the position information of the second target element. The above-mentioned apparatus is used for executing the method provided by the foregoing embodiment, and the implementation principle and technical effect are similar, which are not described herein again.
These above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors, or one or more Field Programmable Gate Arrays (FPGAs), etc. For another example, when one of the above modules is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
Fig. 9 is a schematic structural diagram of a computer device according to an embodiment of the present application, and referring to fig. 9, the computer device includes: the memory 910 and the processor 920, wherein the memory 910 stores a computer program operable on the processor 920, and when the processor 920 executes the computer program, the steps of the power switch planning method of the chip are implemented.
Optionally, the computer device may be specifically the computer device, that is, an execution subject of the method.
In another aspect of the embodiments of the present application, a computer-readable storage medium is further provided, where the storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the power switch planning method for the chip are implemented.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (13)

1. A power switch planning method for a chip is characterized by comprising the following steps:
acquiring unit planning information of a plurality of programmable power switch units in a target chip, wherein the unit planning information comprises: position information of the power switch unit can be planned;
obtaining arrangement information of a sample power switch unit according to the unit planning information, wherein the sample power switch unit is any one of the plurality of programmable power switch units;
determining the arrangement information of each power switch unit to be planned according to the arrangement information of the sample power switch units and the position information of each power switch unit to be planned, wherein the power switch unit to be planned is a power switch unit except the sample power switch unit in the plurality of programmable power switch units, and the arrangement information comprises: the specific location of each element arrangement in the power switch unit.
2. The method according to claim 1, wherein the determining the arrangement information of each power switch unit to be planned according to the arrangement information of the sample power switch units and the position information of each power switch unit to be planned comprises:
acquiring position information of a first target element in the sample power switch unit according to the arrangement information of the sample power switch unit;
determining the position information of a second target element in the power switch unit to be planned according to the position information of the power switch unit to be planned;
determining a relative distance of the second target element from the first target element;
and determining the arrangement information of each power switch unit to be planned according to the relative distance between the second target element and the first target element and the arrangement information of the sample power switch units.
3. The method of claim 2, wherein determining the relative distance of the second target element from the first target element comprises:
determining an abscissa distance of the second target element from the first target element;
determining a vertical coordinate distance of the second target element from the first target element;
taking the abscissa distance and the ordinate distance as the relative distance.
4. The method according to claim 3, wherein the determining the arrangement information of each power switch unit to be planned according to the relative distance between the second target element and the first target element and the arrangement information of the sample power switch units comprises:
superposing the abscissa of each element in the sample power switch unit and the abscissa distance to obtain the abscissa of the corresponding element in the power switch unit to be planned;
superposing the vertical coordinate of each element in the sample power switch unit with the vertical coordinate distance to obtain the vertical coordinate of the corresponding element in the power switch unit to be planned;
and taking the attribute information of each element in the sample power switch unit as the attribute information of the corresponding element in the power switch unit to be planned.
5. The method according to any one of claims 2 to 4, wherein the determining the position information of the second target element in the power switch unit to be planned according to the position information of the power switch unit to be planned comprises:
and determining the position information of the second target element according to the position information of the boundary line of the power switch unit to be planned and the position information of the routing track in the area where the power switch unit to be planned is located.
6. The method according to claim 5, wherein the determining the position information of the second target element according to the position information of the boundary line of the power switch unit to be planned and the position information of the routing track in the area where the power switch unit to be planned is located includes:
and if the distance between the first routing track with the minimum distance from the boundary line in the power switch unit to be planned and the boundary line is greater than or equal to a preset distance, determining that the position of the first routing track is the position of the second target element.
7. The method according to claim 5, wherein the determining the position information of the second target element according to the position information of the boundary line of the power switch unit to be planned and the position information of the routing track in the area where the power switch unit to be planned is located includes:
and if the distance between a first routing track with the minimum distance from the boundary line in the power switch unit to be planned and the boundary line is smaller than a preset distance, determining that the position of a second routing track adjacent to the first routing track is the position of the second target element.
8. The method according to claim 5, wherein the boundary line of the power switch unit to be planned is the boundary line of the bottom of the power switch unit to be planned.
9. The method according to any one of claims 2-4, wherein the obtaining of the arrangement information of the sample power switch unit according to the unit planning information comprises:
according to the unit planning information of the sample power switch unit, acquiring position information of a boundary line of the sample power switch unit, position information of a routing track in an area where the sample power switch unit is located and relative distances of elements in the sample power switch unit;
obtaining the position information of the first target element in the layout information according to the position information of the boundary line of the sample power switch unit and the position information of the routing track in the area where the sample power switch unit is located;
and obtaining the position information of each element except the first target element in the arrangement information according to the relative distance of each element in the sample power switch unit and the position information of the first target element.
10. The method according to claim 1, wherein the determining the arrangement information of each power switch unit to be planned according to the arrangement information of the sample power switch units and the position information of each power switch unit to be planned comprises:
obtaining the relative distance between each element in the sample power switch unit and a first target element from the arrangement information of the sample power switch unit, wherein the relative distances between the sample power switch unit and the corresponding elements in the power switch unit to be planned are equal;
acquiring position information of a second target element in the power switch unit to be planned;
and determining the arrangement information of the power switch unit to be planned according to the relative distance between each element in the sample power switch unit and the first target element in the sample power switch unit and the position information of the second target element.
11. A power switch planning apparatus for a chip, comprising: the system comprises an acquisition module, a sample planning module and an overall planning module;
the obtaining module is configured to obtain unit planning information of a plurality of programmable power switch units in a target chip, where the unit planning information includes: position information of the power switch unit can be planned;
the sample planning module is used for obtaining the arrangement information of a sample power switch unit according to the unit planning information, wherein the sample power switch unit is any one of the plurality of programmable power switch units;
the overall planning module is configured to determine arrangement information of each to-be-planned power switch unit according to the arrangement information of the sample power switch units and the position information of each to-be-planned power switch unit, where the to-be-planned power switch unit is a power switch unit other than the sample power switch unit among the plurality of programmable power switch units, and the arrangement information includes: the specific location of each element arrangement in the power switch unit.
12. A computer device, comprising: memory in which a computer program is stored which is executable on the processor, a processor which, when executing the computer program, carries out the steps of the method according to any one of claims 1 to 10.
13. A computer-readable storage medium, characterized in that the storage medium has stored thereon a computer program which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 10.
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