CN218385195U - Fan-out row chip packaging structure - Google Patents
Fan-out row chip packaging structure Download PDFInfo
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- CN218385195U CN218385195U CN202222294453.2U CN202222294453U CN218385195U CN 218385195 U CN218385195 U CN 218385195U CN 202222294453 U CN202222294453 U CN 202222294453U CN 218385195 U CN218385195 U CN 218385195U
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Abstract
The utility model discloses a fan-out line chip packaging structure, which belongs to the technical field of semiconductor packaging, and comprises a first plastic packaging layer for plastic packaging of a chip, wherein one side of the first plastic packaging layer is sequentially provided with a first dielectric layer and a second dielectric layer; the other side of the first plastic package layer is provided with a heat dissipation module. Furthermore, the heat dissipation module sequentially comprises a first insulating layer, a metal layer and a second insulating layer, and the first insulating layer is connected with the chip. The radiating efficiency of the chip after fan-out type packaging and plastic packaging is improved by introducing the radiating module, so that the stable work of the chip is ensured, and the packaging reliability is improved. Furthermore, the heat dissipation coefficient of the heat dissipation module formed by the first insulation layer/the metal layer/the second insulation layer is far greater than that of the plastic package layer, so that the heat dissipation efficiency of the fan-out type packaging structure is greatly improved.
Description
Technical Field
The utility model relates to a semiconductor package technical field especially relates to a fan-out is chip packaging structure in line.
Background
In recent years, the feature size of chips has approached the physical limit, and advanced packaging technology has become an important approach to continue moore's law. A new family of packaging technologies is emerging, and among them fan-out wafer level packaging (FOWLP) is expected to provide robust and powerful support for the next generation of compact, high performance electronic devices.
The fan-out wafer level packaging technology can realize packaging heterogeneous integration of chips with smaller overall dimensions without using an interposer or Through Silicon Vias (TSVs). When each die is embedded, an additional I/O connection point is arranged in the gap between the dies, so that the utilization rate of silicon is improved while the I/O quantity is increased. With the addition of fan-out wafer level packaging technology, semiconductor devices with thousands of I/O points can be seamlessly connected through two to five micron spaced lines, thereby maximizing interconnect density.
The process steps of fan-out wafer die packaging generally include: restructuring a wafer → performing plastic package, removing a slide glass → manufacturing a rewiring layer → thinning the wafer → planting balls, and in the packaging process of the fan-out wafer chip, because the plastic package generally adopts epoxy resin, the heat dissipation is poor after the fan-out packaging plastic package, and the overall reliability of the packaging structure is reduced.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome prior art's problem, provide a fan-out capable chip package structure.
The purpose of the utility model is realized through the following technical scheme: a fan-out line chip packaging structure comprises a first plastic packaging layer for plastic packaging of a chip, wherein a first medium layer and a second medium layer are sequentially arranged on one surface of the first plastic packaging layer; the other side of the first plastic package layer is provided with a heat dissipation module.
In one example, the heat dissipation module sequentially comprises a first insulating layer, a metal layer and a second insulating layer, wherein the first insulating layer is connected with the chip.
In an example, the package structure further includes a second molding layer for molding the heat dissipation module.
In one example, the thickness of the first plastic package layer is equal to the thickness of the chip, and the surface of the chip is flush with the surface of the first plastic package layer.
In one example, the thickness of the second molding compound layer is larger than that of the heat dissipation module.
In an example, the first molding compound layer and the second molding compound layer are both epoxy resin molding compounds.
In one example, the first dielectric layer is epoxy resin, PBO, al 2 O 3 、SiO 2 And SiNx; the second dielectric layer is made of epoxy resin, PBO and Al 2 O 3 、SiO 2 And SiNx.
In one example, the redistribution layer is one or more redistribution sub-layers.
In one example, the metal layer is any one of Cu, ti, al, ni, and Au.
In one example, the first insulating layer is AlN or Al 2 O 3 Any one or a combination thereof; the second insulating layer is AlN or Al 2 O 3 Any one or a combination thereof.
It should be further noted that the technical features corresponding to the above examples can be combined with each other or replaced to form a new technical solution.
Compared with the prior art, the utility model discloses beneficial effect is:
1. in one example, the heat dissipation efficiency of the chip after fan-out type packaging and plastic packaging is improved by introducing the heat dissipation module, so that stable work of the chip is guaranteed, and packaging reliability is improved.
2. In one example, the heat dissipation module formed by the first insulating layer/the metal layer/the second insulating layer has a heat dissipation coefficient much larger than that of the molding compound layer, so that the heat dissipation efficiency of the fan-out package structure is greatly improved.
3. In an example, the heat dissipation module is plastically packaged through the second plastic packaging layer, so that the packaging reliability of the whole plastic packaging structure is further improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention.
FIG. 1 is a schematic view of the package structure obtained in step S1 of the package structure manufacturing method of the present invention;
FIG. 2 is a schematic view of the package structure obtained in step S2 of the package structure manufacturing method of the present invention;
FIG. 3 is a schematic view of the package structure obtained in step S3 of the package structure manufacturing method of the present invention;
fig. 4 is a schematic view of the package structure obtained in step S4 of the package structure manufacturing method of the present invention;
FIG. 5 is a schematic view of the package structure obtained in step S5 of the package structure manufacturing method of the present invention;
fig. 6 is a schematic view of the package structure obtained in step S6 of the package structure manufacturing method of the present invention;
fig. 7 is a schematic view of the package structure obtained in step S7 of the package structure manufacturing method of the present invention;
fig. 8 is a schematic view of the package structure obtained in step S8 of the package structure manufacturing method of the present invention;
fig. 9 is a schematic view of the package structure obtained in step S9 of the package structure manufacturing method according to the present invention;
fig. 10 is a schematic view of the package structure obtained in step S10 of the package structure manufacturing method of the present invention;
fig. 11 is a schematic diagram of the package structure obtained in step S11 of the package structure preparation method of the present invention, which is also a schematic diagram of the package structure in the preferred example of the present invention.
In the figure: the chip comprises a chip 1, a carrier plate 2, a first plastic package layer 3, a first insulating layer 4, a metal layer 5, a second insulating layer 6, a second plastic package layer 7, a first dielectric layer 8, a rewiring layer 9, a bonding pad 10, a second dielectric layer 11 and a solder ball 12.
Detailed Description
The technical solution of the present invention will be described clearly and completely with reference to the accompanying drawings, and obviously, the described embodiments are some, but not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like are the directions or positional relationships indicated on the basis of the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element indicated must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, ordinal words (e.g., "first and second," "first through fourth," etc.) are used to distinguish between objects, and are not limited to the order, but rather are to be construed to indicate or imply relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Furthermore, the technical features mentioned in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
In an example, as shown in fig. 11, a fan-out row chip package structure specifically includes a first plastic package layer 3 for plastic-packaging a chip 1, where the first plastic package layer 3 wraps the chip 1, and a thickness of the first plastic package layer 3 is greater than or equal to a thickness of the chip 1. A first dielectric layer 8 and a second dielectric layer 11 are sequentially arranged on one surface (close to the front surface of the chip 1) of the first plastic package layer 3, a first dielectric layer 8 and a second dielectric layer 11 are arranged on the front surface of the corresponding chip 1 through the first plastic package layer 3, a redistribution layer 9RDL connected with the chip 1 is arranged in the first dielectric layer 8 and the second dielectric layer 11, and a solder ball 12 is formed on the redistribution layer 9, namely the chip 1 is electrically connected with the solder ball 12 through the redistribution layer 9, so that an interface of the corresponding chip 1 is led out. The solder ball 12 is made of any one of tin-lead, silver, copper, tin-lead alloy, etc., and is preferably a solder ball in this example.
Further, a heat dissipation module is arranged on the other side of the first plastic package layer 3, and when the first plastic package layer 3 completely wraps the reverse side of the chip 1, a heat conductor can be arranged at the moment, namely the reverse side of the chip 1 is connected with the heat dissipation module through the heat conductor, so that heat generated during the working of the chip 1 is led out, and the heat dissipation efficiency is improved; when the first plastic package layer 3 does not completely wrap the chip 1, namely the surface of the chip 1 (the reverse surface of the chip 1) is exposed, or part of the surface of the chip 1 is exposed, the surface of the chip 1, which is exposed out of the first plastic package layer 3, is contacted with the heat dissipation module, so that heat conduction is realized, and the heat dissipation efficiency is improved. In this example, the heat dissipation efficiency of the chip 1 after fan-out type packaging and plastic packaging is improved by introducing the heat dissipation module, so that the stable work of the chip 1 is ensured, and the packaging reliability is improved.
In one example, the heat dissipation module sequentially includes a first insulating layer 4, a metal layer 5, and a second insulating layer 6, and the first insulating layer 4 is connected to the chip 1. Specifically, when the first plastic package layer 3 completely wraps the reverse surface of the chip 1, the first insulating layer 4 is connected with the chip 1 through the heat conductor; when the first molding compound 3 does not completely wrap the chip 1, the first insulating layer 4 is formed on the first molding compound 3, and the first insulating layer 4 is in surface contact with the chip 1, preferably, the first insulating layer 4 is in complete contact with the entire surface of the chip 1, so as to increase the heat dissipation contact area. In order to ensure the heat dissipation effect, the length of the heat dissipation module is greater than that of the chip 1 and slightly smaller than that of the first plastic package layer 3. In this example, the heat dissipation coefficient of the heat dissipation module formed by the first insulating layer 4, the metal layer 5 and the second insulating layer 6 is much larger than that of the plastic package layer, so that the heat dissipation efficiency of the fan-out package structure is greatly improved.
In an example, the package structure further includes a second plastic package layer 7 for plastic packaging of the heat dissipation module, and the second plastic package layer 7 covers the heat dissipation module, that is, the thickness of the first plastic package layer 3 is greater than or equal to the thickness of the heat dissipation module (the sum of the thicknesses of the first insulating layer 4, the metal layer 5, and the second insulating layer 6), so as to protect the chip 1. In this example, the heat dissipation module is plastic-packaged by the second plastic package layer 7, so that the packaging reliability of the whole plastic package structure is further improved. Further, the thickness of the metal layer 5 occupies the main thickness of the entire heat dissipation package structure (the heat dissipation module and the second molding compound layer 7), so as to ensure the heat dissipation performance of the entire heat dissipation package structure.
In an example, the thickness of the first plastic package layer 3 is equal to the thickness of the chip 1, the surface of the chip 1 is flush with the surface of the first plastic package layer, namely, the front pin (interface) of the chip 1 is exposed out of the first plastic package layer 3 at the moment, the back surface of the chip 1 is exposed out of the first plastic package layer 3, the front surface of the chip 1 is stably and effectively connected with the redistribution layer 9 at the moment, the back surface of the chip 1 is fully contacted with the heat dissipation module, the heat dissipation performance is guaranteed, and the size of the packaging structure is effectively reduced.
In an example, the thickness of the second plastic package layer 7 is greater than or equal to the thickness of the heat dissipation module, preferably, the thickness of the second plastic package layer 7 is greater than the thickness of the heat dissipation module, at this time, the second insulation layer 6 in the heat dissipation module is completely wrapped by the second plastic package layer, the first insulation layer 4 and the second plastic package layer 7 are flush with the second plastic package layer 7, when the reverse side of the chip 1 is flush with the first plastic package layer 3, the first insulation layer 4 is fully contacted with the reverse side of the chip 1 at this time, and the size of the chip 1 is reduced while effective heat dissipation is ensured.
In one example, the first plastic package layer 3 and the second plastic package layer 7 are both plastic package layers made of epoxy resin, have the characteristics of light weight, high strength, good corrosion resistance, excellent electrical property, shock absorption and the like, and can better meet the packaging requirements of the chip 1.
In one example, the first dielectric layer 8 is epoxy, PBO, al 2 O 3 、SiO 2 And SiNx; the second dielectric layer 11 is made of epoxy resin, PBO, al 2 O 3 、SiO 2 And SiNx.
In one example, the redistribution layer 9 is one or more redistribution sub-layers, depending on the circuit design of the chip 1 and the functional interfaces that need to be brought out.
In one example, the metal layer 5 is any one of Cu, ti, al, ni, and Au, preferably Cu, which has good electrical and thermal conductivity and low cost.
In one example, the first insulating layer 4 is AlN, al 2 O 3 Any one or a combination thereof, preferably AlN; the second insulating layer 6 is AlN or Al 2 O 3 Any one or a combination thereof, preferably AlN.
The above examples are combined to obtain the preferable example of the present invention, and at this time, the package structure includes the first plastic package layer 3 for plastic packaging the chip 1, and the first plastic package layer 3 is flush with the surface of the chip 1; a first medium layer 8 and a second medium layer 11 are sequentially arranged on one surface of the first plastic package layer 3, a rewiring layer 9 connected with the chip 1 is arranged in the first medium layer 8 and the second medium layer 11, a solder ball 12 is formed on the rewiring layer 9, and a pad 10 of the chip 1 is connected with the solder ball 12 through the rewiring layer 9, so that a functional pin of the chip 1 is led out; the other side of the first plastic package layer 3 is provided with a heat dissipation module, the heat dissipation module sequentially comprises a first insulation layer 4, a metal layer 5 and a second insulation layer 6, the first insulation layer 4 is connected with the chip 1, the whole heat dissipation module is plastically packaged through a second plastic package layer 7, and the surface of the second plastic package layer 7 is flush with the surface of the whole heat dissipation module.
To illustrate the technical concept of the present invention, a method for manufacturing a fan-out chip package structure in a preferred embodiment will now be described, the method comprising the steps of:
s1: the chip 1 is pasted on the carrier plate 2; as shown in fig. 1, the front surface of the chip 1 is adhered to the surface of the carrier plate 2 by temporary bonding glue, and the carrier plate 2 includes, but is not limited to, a steel plate, a glass plate, and the like.
S2: carrying out plastic package on the chip 1 to form a first plastic package layer 3; as shown in fig. 2, the chip 1 is completely covered by the first plastic package layer 3, so as to protect the chip 1;
s3: thinning the first plastic packaging layer 3; as shown in fig. 3, the thickness of the first molding compound layer 3 is equal to the thickness of the chip 1, i.e. the front and back sides of the chip 1 are flush with the first molding compound layer 3.
S4: manufacturing a heat dissipation module; specifically, as shown in fig. 4, a first insulating layer 4, a metal layer 5 and a second insulating layer 6 are sequentially deposited on the first molding layer 3, and the first insulating layer 4 is in contact with the reverse surface of the chip 1.
S5: carrying out plastic package on the heat dissipation model to form a second plastic package layer 7; as shown in fig. 5, the heat dissipation module is coated by the second plastic package layer 7, so as to ensure the reliability of the package.
S6: thinning the second plastic packaging layer 7; as shown in fig. 6, the thickness of the second plastic package layer 7 is equal to the thickness of the heat dissipation module, and the heat dissipation module is flush with the second plastic package layer 7.
S7: as shown in fig. 7, the carrier plate 2 is removed, specifically, the carrier plate 2 is removed by removing the temporary bonding glue;
s8: as shown in fig. 8, a first dielectric layer 8 is formed on the first molding compound layer 3, so as to facilitate the rewiring of the subsequent chip 1;
s9: forming a rewiring layer 9; as shown in fig. 9, a corresponding redistribution layer 9 is fabricated based on functional pins to be led out, that is, a pad 10 of the chip 1 is connected to the redistribution layer 9, and the redistribution layer 9 may be one or more sub-redistribution layers 9, and an interface of the chip 1 is provided through the redistribution layer 9.
S10: forming a second dielectric layer 11; as shown in fig. 10, in order to secure the stability of the rewiring layer 9, a second dielectric layer 11 is prepared on the basis of the formation of the rewiring layer 9.
S11: solder balls 12 are fabricated. As shown in fig. 11, a solder ball is formed on the second dielectric layer 11, so as to lead out the functional pin of the chip 1, thereby obtaining the packaging structure of the fan trip chip 1 of the present invention.
The above detailed description is the detailed description of the present invention, and it can not be considered that the detailed description of the present invention is limited to these descriptions, and to the ordinary skilled person in the art to which the present invention belongs, without departing from the concept of the present invention, a plurality of simple deductions and replacements can be made, which should be regarded as belonging to the protection scope of the present invention.
Claims (10)
1. The utility model provides a fan-out line chip package structure which characterized in that: the chip packaging structure comprises a first plastic packaging layer for carrying out plastic packaging on a chip, wherein a first medium layer and a second medium layer are sequentially arranged on one surface of the first plastic packaging layer; the other side of the first plastic package layer is provided with a heat dissipation module.
2. The fan-out row die package structure of claim 1, wherein: the heat dissipation module sequentially comprises a first insulating layer, a metal layer and a second insulating layer, wherein the first insulating layer is connected with the chip.
3. The fan-out row die package structure of claim 1, wherein: the packaging structure further comprises a second plastic packaging layer for plastic packaging of the heat dissipation module.
4. The fan-out row chip package structure of claim 1, wherein: the thickness of the first plastic package layer is equal to that of the chip, and the surface of the chip is flush with the surface of the first plastic package layer.
5. The fan-out row die package structure of claim 3, wherein: the thickness of the second plastic package layer is larger than or equal to that of the heat dissipation module.
6. The fan-out row chip package structure of claim 3, wherein: the first plastic package layer and the second plastic package layer are both plastic package layers made of epoxy resin materials.
7. The fan-out row die package structure of claim 1, wherein: the first dielectric layer is made of epoxy resin, PBO and Al 2 O 3 、SiO 2 And SiNx; the second dielectric layer is made of epoxy resin, PBO and Al 2 O 3 、SiO 2 And SiNx.
8. The fan-out row die package structure of claim 1, wherein: the rewiring layer is one or more rewiring sublayers.
9. The fan-out row die package structure of claim 2, wherein: the metal layer is any one of Cu, ti, al, ni and Au.
10. The fan-out row die package structure of claim 2, wherein: the first insulating layer is AlN or Al 2 O 3 Any one or a combination thereof; the second insulating layer is AlN or Al 2 O 3 Any one or a combination thereof.
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| CN202222294453.2U CN218385195U (en) | 2022-08-30 | 2022-08-30 | Fan-out row chip packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117574816A (en) * | 2024-01-15 | 2024-02-20 | 江苏中科智芯集成科技有限公司 | Stress simulation method, system, equipment and storage medium for chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117574816A (en) * | 2024-01-15 | 2024-02-20 | 江苏中科智芯集成科技有限公司 | Stress simulation method, system, equipment and storage medium for chip |
| CN117574816B (en) * | 2024-01-15 | 2024-03-29 | 江苏中科智芯集成科技有限公司 | Stress simulation method, system, equipment and storage medium for chip |
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