CN116469870A - Interposer, semiconductor package structure and forming method thereof - Google Patents

Abstract

The embodiment of the disclosure provides an interposer, a semiconductor package structure and a forming method thereof, wherein the interposer is used for transmitting electric signals among a plurality of stacked structures in the semiconductor package structure, and the interposer comprises: a core layer and a heat dissipation structure; the core layer comprises at least a first region; the heat dissipation structure penetrates through the first area at least along the first direction; the first direction is the thickness direction of the core layer.

Description

Interposer, semiconductor package structure and forming method thereof

Technical Field

The present disclosure relates to the field of semiconductor packaging technology, and relates to, but is not limited to, an interposer, a semiconductor package structure, and a method of forming the same.

Background

With the increasing integration, semiconductor devices are required to be smaller and smaller in size. Currently, the chip may be packaged by stacking multiple layers to reduce the volume of the package structure. However, when the chip works, the heat generating area is concentrated, the heat dissipation performance of the packaging structure is poor, and the performance of the packaging structure is affected.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide an interposer, a semiconductor package structure and a method of forming the same.

In a first aspect, embodiments of the present disclosure provide an interposer for transferring electrical signals between a plurality of stacked structures in a semiconductor package structure, comprising: a core layer and a heat dissipation structure;

The core layer comprises at least a first region;

the heat dissipation structure penetrates through the first area at least along a first direction; the first direction is a thickness direction of the core layer.

In some embodiments, the heat dissipating structure comprises: at least one heat dissipation post penetrating through the first region along the first direction;

the plurality of heat dissipation posts are uniformly or non-uniformly distributed at intervals in the first area.

In some embodiments, the heat dissipating structure further comprises: the first heat dissipation layer and/or the second heat dissipation layer;

the first heat dissipation layer covers the top surface of the heat dissipation post, or covers the top surfaces of the heat dissipation post and the first region;

the second heat dissipation layer covers the bottom surface of the heat dissipation post, or covers the bottom surfaces of the heat dissipation post and the first region.

In some embodiments, the heat dissipating structure further comprises: at least one heat dissipation bump positioned on the surface of the first heat dissipation layer;

the heat dissipation convex blocks are distributed on the surface of the first heat dissipation layer at intervals.

In a second aspect, embodiments of the present disclosure provide a semiconductor package structure, including: a first encapsulation unit, an interposer as described in the above embodiments, and a second encapsulation unit;

The first packaging unit, the interposer and the second packaging unit are sequentially bonded from bottom to top along the first direction; the first packaging unit at least comprises a first chip attached to the first substrate; the first area covers the first chip;

the heat dissipation structure is located on the first chip.

In some embodiments, further comprising: a heat conductive layer and a third heat dissipation layer; wherein, the liquid crystal display device comprises a liquid crystal display device,

the heat conducting layer is positioned between the first chip and the heat radiating structure and is in direct thermal contact with the first chip and the heat radiating structure;

the third heat spreader is located between the interposer and the second package unit and is in direct thermal contact with the interposer and the second package unit.

In a third aspect, an embodiment of the present disclosure provides a method for forming a semiconductor package structure, including:

providing a first packaging unit, a second packaging unit and an interposer; the first packaging unit at least comprises a first chip attached to the first substrate; the interposer includes at least a core layer and a heat dissipation structure extending through a first region of the core layer in at least a first direction;

Stacking the interposer and the second packaging unit to the surface of the first packaging unit in sequence; wherein the first region covers the first chip;

the first direction is a thickness direction of the first substrate.

In some embodiments, the method of forming the interposer includes:

providing a core layer, the core layer comprising at least a first region;

etching the first region to form at least one blind hole structure penetrating through the first region;

forming a heat dissipation column in the blind hole structure; wherein, the heat dissipation post constitutes heat radiation structure.

In some embodiments, the method for forming an interposer further includes:

forming a first heat dissipation layer covering the top surface of the heat dissipation post and the top surface of the first region, and a second heat dissipation layer covering the bottom surface of the heat dissipation post and the bottom surface of the first region; the heat dissipation column, the first heat dissipation layer and the second heat dissipation layer form the heat dissipation structure.

In some embodiments, the method for forming an interposer further includes:

and forming a heat dissipation bump on the surface of the first heat dissipation layer.

In some embodiments, before the interposer is stacked to the surface of the first packaging unit, the method further comprises:

Forming a heat conduction layer on the surface of the first chip; the thermally conductive layer is in direct thermal contact with the first chip.

In some embodiments, the method further comprises:

forming a third heat dissipation layer on the surface of the interposer before stacking the second packaging unit to the interposer;

or alternatively, the process may be performed,

after stacking the second package unit to the interposer, a gap between the second package unit and the interposer constitutes the third heat dissipation layer.

The embodiment of the disclosure provides an interposer, a semiconductor packaging structure and a forming method thereof, wherein the provided interposer comprises: a core layer and a heat dissipation structure; the core layer comprises at least a first region; the heat dissipation structure penetrates through the first area at least along the first direction. Because the heat dissipation structure is arranged in the interposer in the semiconductor packaging structure, the heat emitted by the chip can be conducted out through the heat dissipation structure in the interposer, so that the heat accumulation in the semiconductor packaging structure is reduced, and the performance of the semiconductor packaging structure is improved.

Drawings

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

FIG. 1 is a schematic diagram of a semiconductor package structure in the related art;

fig. 2 to 9 are schematic structural diagrams of an interposer according to an embodiment of the disclosure;

fig. 10 and 11 are schematic structural views of a semiconductor package structure provided in an embodiment of the present disclosure;

fig. 12 is a flowchart illustrating a method for forming a semiconductor package according to an embodiment of the disclosure;

fig. 13 to 21 are schematic structural views during the formation of a semiconductor package structure according to an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Currently, POP (Package on Package) packages are mainly applied to application (Application Processor, AP) chips of mobile phones and tablet computers. POP packaging is limited by the packaging structure and the performance of the packaging material, resulting in poor heat dissipation performance of the chip, thereby limiting the maximum power consumption of the chip, and finally limiting the performance of the packaging structure.

Fig. 1 is a schematic structural diagram of a semiconductor package structure in the related art, and as shown in fig. 1, a semiconductor package structure 100 includes: a chip 110 and an interposer 120. Wherein, the plastic package 130 is generally filled between the chip 110 and the interposer 120. Because of the poor heat conducting property of the molding compound 130, the heat generated by the chip 110 during operation is not easy to be dissipated.

In addition, the outer surface of the interposer 120 is typically formed with a solder resist layer 140. Since the material of the solder mask layer 140 is an organic polymer composite material, the heat dissipation of the chip 110 is further prevented, so that the heat in the semiconductor package structure 100 is concentrated to affect the performance of the chip 110.

Based on this, embodiments of the present disclosure provide an interposer, a semiconductor package structure, and a method of forming the same, wherein the provided interposer includes: a core layer and a heat dissipation structure; the core layer comprises at least a first region; the heat dissipation structure penetrates through the first area at least along the first direction. Because the heat dissipation structure is arranged in the interposer in the semiconductor packaging structure, the heat emitted by the chip can be conducted out through the heat dissipation structure in the interposer, so that the heat accumulation in the semiconductor packaging structure is reduced, and the performance of the semiconductor packaging structure is improved.

The interposer, semiconductor package structure, and method of forming the same in embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

In some embodiments, please refer to fig. 2 to 9, which illustrate schematic structural diagrams of an interposer provided by an embodiment of the present disclosure. As shown in fig. 2 to 9, the interposer 200 includes: a core layer 210 and a heat dissipating structure 220; the core layer 210 includes at least a first region a; the heat dissipation structure 220 penetrates through the first area a along at least the first direction.

It should be noted that the interposer 200 in the embodiments of the present disclosure may be used to transfer electrical signals between multiple stacked structures in a semiconductor package structure. Here, the plurality of stacked structures may be a plurality of chips, a circuit board, or a chip and a circuit board; the semiconductor package structure may be a POP package or a 2.5D package, a 3D package, or the like. The interposer 200 can improve heat dissipation performance in the semiconductor package structure, thereby improving reliability of the semiconductor package structure.

In the embodiment of the disclosure, the heat dissipation structure in the interposer is used for performing heat dissipation treatment on the member to be heat-dissipated, and therefore, the heat dissipation structure is located on (or directly above) the surface of the member to be heat-dissipated. Here, the heat dissipation member may be, for example, a chip.

It should be further noted that, the heat dissipation structure 220 penetrating the first area a along the first direction means: the heat dissipating structure 220 is connected to the bottom surface at least from the top surface of the first region a. The portion of the heat dissipation structure 220 penetrating the first region a may be linear, U-shaped, L-shaped, or curved. The material of the heat dissipating structure 220 may be copper, gold, cobalt, or any other suitable thermally conductive material.

It should be noted that the first direction is a thickness direction of the core layer 210, for example, an X-axis direction in fig. 2 to 9.

In the embodiment of the present disclosure, the material of the core layer 210 may be any suitable dielectric material, and may be a non-organic dielectric material, for example, silicon oxide, silicon nitride, or the like, and may be an organic dielectric material, for example, an organic polymer, including Polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (Poly-p-phenylene benzobisoxazole, PBO), or the like.

In the embodiment of the present disclosure, the core layer 210 may have a single-layer structure or a multi-layer stacked structure. The multi-layer stacked structure can be formed by stacking non-organic dielectric material layers, and can also comprise an organic dielectric material layer and a non-organic dielectric material layer.

Because the heat dissipation structure is arranged in the interposer in the semiconductor packaging structure, the heat emitted by the chip can be conducted out through the heat dissipation structure in the interposer, so that the heat accumulation in the semiconductor packaging structure is reduced, and the performance of the semiconductor packaging structure is improved.

In some embodiments, referring to fig. 2 to 9, the core layer 210 further includes: and a second region B surrounding the first region a, i.e., the first region a and the second region B together form the core layer 210. The interposer 200 further includes: and a first interconnection structure disposed in the second region B. Illustratively, in this embodiment, the first interconnect structure includes a first connection pad 240 and a first connection wire 230; the first connection wire 230 penetrates through the second region B, and the first connection pad 240 is located on the top and bottom surfaces of the second region B and is electrically connected with the first connection wire 230. The first connection pads 240 are used to electrically connect with package units subsequently formed on or under the interposer 200, and electrical connection between different package units may be achieved through the first connection pads 240 and the first connection wires 230.

It should be noted that the structures in fig. 2 to 9 are only simple illustrations of the first interconnect structure in the interposer 200. In some embodiments, the first interconnect structure in the second region B may further include a horizontal interconnect line parallel to the surface direction of the interposer 200 in addition to a vertical interconnect column perpendicular to the thickness direction (i.e., X-axis direction) of the interposer 200 to form a re-wiring structure.

In the embodiment of the present disclosure, the material of the first connection pad 240 and the first connection wire 230 in the first interconnection structure may be any material with better electrical conductivity, for example, copper.

In some embodiments, the materials of the heat dissipation structure 220, the first connection pad 240, and the first connection wire 230 may be the same material, such as copper. In this way, the heat dissipation structure 220, the first connection pad 240 and the first connection wire 230 may be formed at the same time, and thus, the manufacturing process of the interposer 200 may be simplified, and the cost may be saved.

In some embodiments, referring to fig. 2 to 9, the interposer 200 further includes: the first solder mask 250. The first solder resist layer 250 covers the top and bottom surfaces of the core layer 210 and covers a portion of the first connection pad 240. The first solder resist layer 250 serves to insulate adjacent first connection pads 240 from short circuits. The first solder mask 250 may be composed of a polymer composite material.

In some embodiments, referring to fig. 2 and 3, the heat dissipating structure 220 includes: at least one heat dissipation post 220a penetrating the first region a in the X-axis direction; the plurality of heat radiation pillars 220a are uniformly or non-uniformly spaced in the first region a.

Specifically, referring to fig. 2, the heat dissipation structure 220 includes a plurality of heat dissipation pillars 220a penetrating the first region a along the X-axis direction; the plurality of heat radiation pillars 220a are uniformly spaced apart in the first region a. In this way, the heat can be uniformly diffused out.

In other embodiments, the plurality of heat dissipation pillars 220a may be unevenly disposed in the first region a according to the region where heat is concentrated. For example, when the heat generated in the center of the heat dissipation member is large, the heat dissipation columns 220a in the center area of the heat dissipation structure 220 may be densely arranged, and the arrangement density of the surrounding heat dissipation columns 220a may be smaller than that of the heat dissipation columns 220a in the center area, so that the heat dissipation of the heat dissipation structure 220 in the area with higher heat is faster, thereby realizing different heat dissipation rates for different areas, and improving the heat dissipation efficiency of the heat dissipation structure 220.

With continued reference to fig. 3, the heat dissipating structure 220 includes a single heat dissipating stud 220a extending through the first area a along the X-axis direction. In this way, the area of contact of the heat dissipating structure 220 with the piece to be heat dissipated can be made larger, thereby facilitating heat dissipation more.

In some embodiments, referring to fig. 4 to 8, the heat dissipation structure 220 further includes a first heat dissipation layer 220b and/or a second heat dissipation layer 220c; the first heat dissipation layer 220b covers the top surfaces of the heat dissipation pillars 220a, or covers the top surfaces of the heat dissipation pillars 220a and the first region a; the second heat dissipation layer 220c covers the bottom surface of the heat dissipation pillar 220a, or covers the bottom surfaces of the heat dissipation pillar 220a and the first region a.

Specifically, with continued reference to fig. 4, the heat dissipating structure 220 includes: a first heat dissipation layer 220b and a plurality of heat dissipation pillars 220a; the plurality of heat dissipation posts 220a penetrate through the first area a along the X-axis direction, and the plurality of heat dissipation posts 220a are uniformly arranged at intervals in the first area a; the first heat dissipation layer 220b covers the heat dissipation pillars 220a and the top surface of the first region a. In this way, the heat dissipation area of the heat dissipation structure 220 can be increased by the first heat dissipation layer 220b, and heat can be more effectively transferred. And the first heat dissipation layer 220b covers the surface of the first area a, so that the mechanical strength of the interposer can be increased, the reliability when the interposer is used in a semiconductor package structure can be improved, and the warpage and other problems can be improved.

With continued reference to fig. 5, the heat dissipation structure 220 includes a first heat dissipation layer 220b and a plurality of heat dissipation pillars 220a; the plurality of heat dissipation posts 220a penetrate through the first area a along the X-axis direction, and the plurality of heat dissipation posts 220a are uniformly arranged at intervals in the first area a; the first heat dissipation layer 220b covers the top surface of the heat dissipation pillar 220 a. In this way, the heat dissipation area of the heat dissipation structure 220 can be increased by the first heat dissipation layer 220b, and heat can be more effectively transferred.

With continued reference to fig. 6, the heat dissipation structure 220 includes a second heat dissipation layer 220c and a plurality of heat dissipation pillars 220a; the plurality of heat dissipation posts 220a penetrate through the first area a along the X-axis direction, and the plurality of heat dissipation posts 220a are uniformly arranged at intervals in the first area a; the second heat dissipation layer 220c covers the heat dissipation pillars 220a and the bottom surface of the first region a. In this way, the thermal contact surface between the interposer 200 and the heat dissipation member can be improved, so that the heat of the heat dissipation member can be transferred to the heat dissipation structure 220 as soon as possible, and the whole plane of the heat dissipation member can be provided with better heat dissipation uniformity.

With continued reference to fig. 7 and 8, the heat dissipating structure 220 includes: a first heat dissipation layer 220b, a second heat dissipation layer 220c, and a plurality of heat dissipation posts 220a; the plurality of heat dissipation posts 220a penetrate through the first area a along the X-axis direction, and the plurality of heat dissipation posts 220a are uniformly arranged at intervals in the first area a; the first heat dissipation layer 220b covers the heat dissipation pillars 220a and the top surface of the first region a; the second heat dissipation layer 220c covers the heat dissipation pillars 220a and the bottom surface of the first region a. In this way, the heat dissipation structure 220 in the intermediate layer 200 and the heat-dissipation member to be thermally contacted with each other can be larger, so that the heat of the heat-dissipation member to be dissipated is transferred to the heat dissipation structure 220 as soon as possible, which is beneficial to diffusing the heat, and the mechanical strength of the intermediate layer can be increased through the first heat dissipation layer 220b and the second heat dissipation layer 220c, thereby improving the reliability when the semiconductor package structure is used, and improving the warpage and other problems.

In some embodiments, referring to fig. 2 to 7, the dimension of the second region B in the X-axis direction may be equal to the dimension of the first region a in the X-axis direction. In this way, the first region a and the second region B may be simultaneously prepared, so that the preparation process of the core layer 210 may be simplified and the cost may be reduced.

In other embodiments, the dimension d2 of the second region B in the X-axis direction may be larger than the dimension d1 of the first region a in the X-axis direction (as shown in fig. 8). In this way, the thickness of the first heat dissipation layer 220b and/or the second heat dissipation layer 220c may be set thicker while maintaining the maximum thickness of the interposer 200, which is more advantageous for heat transfer and dissipation.

In other embodiments, the surfaces of the first heat dissipation layer 220B and the second heat dissipation layer 220c may be flush with the surface of the second region B on the basis of the heat dissipation structure 220 shown in fig. 8. Thus, the thickness of the interposer can be further reduced, and the size of the semiconductor package structure formed later can be further reduced.

It should be noted that, the surfaces of the first heat dissipation layer 220B and the second heat dissipation layer 220c may be flush with the surface of the second area B, which may include the following two cases: first, the surfaces of the first heat dissipation layer 220B and the second heat dissipation layer 220c may be flush with the surface of the core layer 210 in the second region B; second, the surfaces of the first heat dissipation layer 220B and the second heat dissipation layer 220c may be flush with the surface of the first solder resist layer 250 of the surface of the core layer 210 in the second region B.

In some embodiments, please continue with reference to fig. 9, the heat dissipation structure 220 further includes: at least one heat dissipation bump 220d located on the surface of the first heat dissipation layer 220 b; the plurality of heat dissipation bumps 220d are arranged at intervals on the surface of the first heat dissipation layer 220 b.

In the embodiment of the disclosure, by disposing the heat dissipation bump 220d on the surface of the first heat dissipation layer 220b, the heat dissipation area of the heat dissipation structure 220 can be larger, so that heat dissipation is facilitated.

In some embodiments, the plurality of heat dissipation bumps 220d are uniformly spaced apart on the surface of the first heat dissipation layer 220 b. Therefore, the heat of the piece to be radiated can be uniformly diffused, and the whole plane of the piece to be radiated can be provided with better radiating uniformity.

In some embodiments, the heat dissipating bump 220d may be a cylindrical bump, a spherical bump, or other shape that may be implemented, which is not limited by the present disclosure.

In some embodiments, the heat dissipation bump 220d may be different from the material of the heat dissipation layer (the first heat dissipation layer 220b and/or the second heat dissipation layer 220 c), for example, the material of the heat dissipation bump 220d may be tin and the material of the heat dissipation layer may be copper; alternatively, the heat dissipation bump 220d may be the same material as the heat dissipation layer (the first heat dissipation layer 220b and/or the second heat dissipation layer 220 c), for example, the heat dissipation bump 220d and the heat dissipation layer may each be copper.

It should be noted that, in other embodiments, the plurality of heat dissipation bumps 220d may be unevenly distributed on the surface of the first heat dissipation layer 220 b. For example, when the heat generated in the center of the heat dissipating member is large, the heat dissipating bumps 220d in the center area of the heat dissipating structure 220 may be densely arranged, and the arrangement density of the heat dissipating bumps 220d around the heat dissipating structure may be smaller than that of the heat dissipating bumps 220d in the center area, so that the heat dissipating structure 220 has a larger heat dissipating area in the area with higher heat, thereby realizing different heat dissipating rates for different areas, and improving the heat dissipating efficiency of the heat dissipating structure 220.

It should be further noted that, in the embodiments of the present disclosure, only some representative embodiments are illustrated, and other possible embodiments are actually included, for example, a combination of the foregoing embodiments is not limited to the foregoing embodiments, and any reasonable modification based on the embodiments of the present application falls within the scope of protection of the embodiments of the present application.

In another embodiment of the present disclosure, please refer to fig. 10 and 11, which illustrate a schematic structural diagram of a semiconductor package structure. As shown in fig. 10 and 11, the semiconductor package structure 300 includes: the first encapsulation unit 310, the interposer 200 in the above embodiment, and the second encapsulation unit 330; the first packaging unit 310, the interposer 200, and the second packaging unit 330 are sequentially bonded from bottom to top along the X-axis direction; the first packaging unit 310 at least includes a first chip 311 attached to a first substrate 312; the first region a covers the first chip 311.

It should be noted that, in fig. 10 of the embodiment of the disclosure, the specific structure of the interposer 200 may refer to fig. 7 in the above embodiment; in fig. 11, the specific structure of the interposer 200 may refer to fig. 9 in the above embodiment, and will not be described in detail here.

It should be noted that the structure of the interposer 200 in the embodiment of the disclosure may be any of the above embodiments, which is not limited herein.

In some embodiments, referring to fig. 10 and 11, the second packaging unit 330 includes at least a second chip 331 attached to the second substrate 332.

The first substrate 312 and the second substrate 332 may be inorganic package substrates or organic package substrates. The first Chip 311 and the second Chip 331 may be a System On Chip (SOC) or a memory Chip; the Memory chip includes a static random access Memory (Static Random Access Memory, SRAM) chip, a dynamic random access Memory (Dynamic Random Access Memory, DRAM) chip, a Phase-Change Memory (PCM) chip, a NAND Flash (Flash) chip, or a norflash chip. It should be noted that the first chip 311 and the second chip 331 may be different.

In one embodiment, the first chip 311 may be an SOC chip, which consumes more power and generates more heat during operation; the second chip 331 may be a memory chip. In this way, the heat generated by the first chip 311 is greater than that generated by the second chip 331, so that the heat dissipation structure is closer to the first chip 311, which is beneficial to heat dissipation of the first chip 311.

In other embodiments, when the heat generation of the second chip 331 is greater than that of the first chip 311, the heat dissipation structure may be reversed. For example, the heat dissipation structure 220 in fig. 9 may be disposed in reverse, that is, the heat dissipation bump 220d is disposed near the first chip 311, so that heat may be dissipated from the second chip 331, thereby improving the overall heat dissipation of the semiconductor package structure 300.

The first chip 311 is electrically connected to the first substrate 312. Specifically, the first chip 311 may be flip-chip bonded to the surface of the first substrate 312, or the first chip 311 may be electrically connected to the first substrate 312 by wire bonding.

The second chip 331 is electrically connected to the second substrate 332. Specifically, the second chip 331 may be flip-chip bonded to the surface of the second substrate 332, or the second chip 331 may be electrically connected to the second substrate 332 by wire bonding.

In some embodiments, please continue to refer to fig. 10 and 11, the heat dissipation structure is located on the first chip 311. Specifically, the heat dissipation structure is located on the surface of the first chip 311, or the heat dissipation structure is located directly above the first chip 311 and is not in contact with the first chip 311. In this way, the first chip 311 can be effectively heat-dissipated by the heat dissipation structure.

In some embodiments, referring to fig. 10 and 11, the semiconductor package structure 300 further includes: a thermally conductive layer 340; the heat conductive layer 340 is located between the first chip 311 and the heat dissipation structure, and is in direct thermal contact with the first chip 311 and the heat dissipation structure. The heat conducting layer 340 is used for directly transferring heat of the first chip 311 to the heat dissipation structure, so that the heat transferring speed can be increased, and the heat on the first chip 311 can be effectively dissipated.

For some embodiments, the material of the thermally conductive layer 340 may be a thermal interface material (Thermal Interface Materials, TIM), the main components of which may include an organic thermally conductive paste and a metal powder.

In some embodiments, referring to fig. 10 and 11, the semiconductor package structure 300 further includes: a third heat dissipation layer 350; the third heat spreader 350 is located between the interposer 200 and the second package unit 330, and is in direct thermal contact with the interposer 200 and the second package unit 330. The third heat dissipation layer 350 can conduct out the heat inside the heat dissipation structure, so as to indirectly conduct out the heat on the first chip, and improve the reliability of the semiconductor package structure.

In some embodiments, the third heat dissipation layer 350 may be a void, or may be any suitable high thermal conductive material layer, for example, the third heat dissipation layer 350 is a conductive layer or a thermal conductive adhesive layer, where the material of the conductive layer may include copper, gold, cobalt, or any other suitable conductive material.

It should be noted that, when the third heat dissipation layer 350 is a conductive layer, insulation between the third heat dissipation layer 350 and the solder balls and the horizontal interconnection lines on the surface of the interposer 200 is required to prevent the semiconductor package structure from being shorted.

In some embodiments, please continue to refer to fig. 10 and 11, the first packaging unit 310 further includes: a second interconnect structure and a second solder resist layer 251; illustratively, in this embodiment, the second interconnect structure includes a second connection pad 241 and a second connection wire 231. The second connection wire 231 penetrates through the first substrate 312, and the second connection pad 241 is located on the top and bottom surfaces of the first substrate 312 and is electrically connected to the second connection wire 231. The second connection pads 241 are used for electrical connection with an interposer subsequently formed above or below the first package unit 310, and electrical connection between different package units may be achieved through the second connection pads 241 and the second connection wires 231.

It should be noted that the structure in fig. 10 and 11 is only a simple illustration of the second interconnection structure in the first package unit 310. In some embodiments, the second interconnection structure may include horizontal interconnection lines parallel to the surface direction of the first encapsulation unit 310 in addition to vertical interconnection columns perpendicular to the thickness direction (X-axis direction) of the first encapsulation unit 310 to form a re-wiring structure.

In an embodiment of the present disclosure, please continue to refer to fig. 10 and 11, the first encapsulation unit 310 further includes: an adhesive layer 313 between the first substrate 312 and the first chip 311. The material of the adhesive layer 313 may be a mold resin such as epoxy resin, a composite of epoxy resin and alumina, a composite of epoxy resin and silica, or the like. The adhesive layer 313 is filled between the first chip 311 and the first substrate 312 for fixing the first chip 311 while protecting the reliability of the flip-chip connection structure between the first chip 311 and the first substrate 312.

In some embodiments, please continue to refer to fig. 10 and 11, the second packaging unit 330 further includes: a third interconnect structure and a third solder resist layer 252; illustratively, in this embodiment, the third interconnect structure includes a third connection pad 242 and a third connection wire 232. The third connection wire 232 penetrates through the second substrate 332, and the third connection pad 242 is located on the top surface and the bottom surface of the second substrate 332 and is electrically connected to the third connection wire 232. The third connection pads 242 are used for electrical connection with an interposer subsequently formed above or below the second package unit 330, and electrical connection between different package units may be achieved through the third connection pads 242 and the third connection wires 232.

It should be noted that the structure in fig. 10 and 11 is only a simple illustration of the third interconnection structure in the second package unit 330. In some embodiments, the third interconnection structure may include horizontal interconnection lines parallel to the surface direction of the second encapsulation unit 330 in addition to vertical interconnection pillars perpendicular to the thickness direction of the second encapsulation unit 330 to form a re-routing structure.

In some embodiments, referring to fig. 10 and 11, the semiconductor package structure 300 further includes: and a connection member 360 located on the surfaces of the first, second and third connection pads 240, 241 and 242. The first package unit 310, the interposer 200, and the second package unit 330 are sequentially bonded from bottom to top in the X-axis direction by the connection element 360, where the connection element 360 may be a solder ball, such as a solder ball.

The semiconductor packaging structure provided in the embodiment of the disclosure includes the interposer in the above embodiment, and since the heat dissipation structure is disposed in the interposer, the heat emitted by the chip can be conducted out through the heat dissipation structure in the interposer, so that the heat collection in the semiconductor packaging structure is reduced, and the performance of the semiconductor packaging structure is improved.

Table 1 below shows the thermal conductivity comparisons of the different materials:

TABLE 1 thermal conductivity of different materials

Material	Plastic packaging material	Solder mask	Copper (Cu)	TIM
					Coefficient of thermal conductivity (W/m. Degree)	0.7～0.9	0.2	400	3.8～4.7

As can be seen from the above table, the copper has the greatest thermal conductivity, the best thermal conductivity, the second TIM, the smaller thermal conductivity of the solder mask layer and the plastic molding compound, and the worse thermal conductivity, so copper may be used to form the heat dissipation structure 220, and copper or TIM may be used as the third heat dissipation layer 350 in the embodiment. In this way, a better heat dissipation effect can be achieved.

In yet another embodiment of the present disclosure, please refer to fig. 12, which illustrates a method for forming a semiconductor package structure, and refer to fig. 13 to 21, which illustrate schematic structural diagrams during the forming process of the semiconductor package structure 300 illustrated in fig. 10 and 11 in the above embodiment. The process of forming the semiconductor package 300 is described in detail below with reference to fig. 12-21.

As shown in fig. 12, the method for forming the semiconductor package 300 includes step S101 and step S102.

First, referring to fig. 12 to 21, step S101 is performed to provide a first encapsulation unit 310, a second encapsulation unit 330, and an interposer 200; the first packaging unit 310 at least includes a first chip 311 attached to a first substrate 312; the interposer 200 at least includes a core layer 210 and a heat dissipation structure 220, and the heat dissipation structure 220 penetrates through a first area a of the core layer 210 along at least an X-axis direction.

In some embodiments, please continue to refer to fig. 13, providing the first packaging unit 310 includes the following steps one and two.

Step one, providing a first substrate 312 and a first chip 311; the first substrate 312 includes a second connection pad 241, a second connection wire 231, a second solder resist layer 251, and a connection element 360.

Step two, the first chip 311 is fixed on the first substrate 312.

In practice, the first chip 311 is flip-chip fixed to the top surface of the first substrate 312 by the adhesive layer 313, and the bonding structure 315 of the first chip 311 is bonded to the second connection pad 241 on the top surface of the first substrate 312 by bonding or soldering.

In some embodiments, please continue to refer to fig. 14, providing the second packaging unit 330 includes the following steps three and four.

Step three, providing a second substrate 332 and a second chip 331; the second substrate 332 includes a third connection pad 242, a third connection wire 232, a third solder resist layer 252, and a connection element 360.

Step four, the second chip 331 is fixed on the second substrate 332.

In practice, the second chip 331 is flip-chip fixed to the top surface of the second substrate 332 by an adhesive layer (not shown), and a bonding structure (not shown) of the second chip 331 is bonded to the third connection pad 242 on the top surface of the second substrate 332 by bonding or soldering or the like.

In some embodiments, referring to fig. 15 to 16, the method for forming the interposer 200 includes the following steps 1 to 3.

Step 1, providing a core layer 210, wherein the core layer 210 at least comprises a first area a;

step 2, etching the first area A to form at least one blind hole structure penetrating through the first area A;

step 3, forming a heat dissipation post 220a in the blind hole structure; wherein the heat dissipation post 220a constitutes the heat dissipation structure 220.

In implementation, first, a core layer 210 as shown in fig. 15 is provided, and the core layer 210 includes a first area a and a second area B; a first seed layer 410 and a second seed layer 420 as shown in fig. 15 are formed by electroplating a metal material on the top and bottom surfaces of the core layer 210. Wherein the metallic material may be copper.

It should be noted that, in the embodiment of the present disclosure, the dimension d1 of the first area a in the X-axis direction is equal to the dimension d2 of the second area B in the X-axis direction; in other embodiments, the first area a may be etched to thin the dimension d1 of the first area a, so that the dimension d2 of the second area B in the X-axis direction is greater than the dimension d1 of the first area a in the X-axis direction, and thus, the interposer 200 as shown in fig. 8 may be formed.

In some embodiments, after the first seed layer 410 and the second seed layer 420 are formed, moisture on the surfaces of the first seed layer 410 and the second seed layer 420 may be removed by high temperature baking to facilitate subsequent process steps.

Next, the first seed layer 410 and the core layer 210 are etched to form a plurality of blind via structures C located in the first and second regions a and B as shown in fig. 16. In embodiments of the present disclosure, first seed layer 410 and core layer 210 may be etched using any suitable method, such as plasma etching or laser etching.

Finally, forming an initial heat dissipation structure by using the first seed layer 410 and the second seed layer 420 as growth substrates, wherein the initial heat dissipation structure is located in the blind hole structure C and covers the top surface and the bottom surface of the first area A; etching back the initial heat dissipation structure until the core layer 210 and the initial heat dissipation structure in the blind via structure C are exposed, forming a heat dissipation pillar 220a in the first region a and a first connection wire 230 in the second region B (please understand with reference to fig. 2); the heat dissipation pillars 220a constitute a heat dissipation structure 220 as shown in fig. 2.

In the embodiment of the disclosure, the initial heat dissipation structure may be formed by a pattern plating process, and the initial heat dissipation structure may be etched back by a wet etching process, a dry etching process, or a planarization process, to form the heat dissipation structure 220 having a flat surface.

It should be noted that, in other embodiments, a blind hole structure C may be formed in the first area a, and the heat dissipation structure 220 shown in fig. 3 may be formed in the blind hole structure C.

In some embodiments, referring to fig. 17, the method for forming the interposer 200 further includes: forming a first heat dissipation layer 220b covering the top surface of the heat dissipation post 220a and the top surface of the first region a, and a second heat dissipation layer 220c covering the bottom surface of the heat dissipation post 220a and the bottom surface of the first region a; the heat dissipation post 220a, the first heat dissipation layer 220b, and the second heat dissipation layer 220c constitute a heat dissipation structure 220.

In some embodiments, after forming the initial heat dissipating structure, the method further comprises: the heat dissipation pillars 220a, the first heat dissipation layer 220b, and the second heat dissipation layer 220c shown in fig. 17 are formed by etching back a portion of the initial heat dissipation structure along the top and bottom surfaces of the initial heat dissipation structure as etching starting points. Wherein the heat dissipation post 220a, the first heat dissipation layer 220b, and the second heat dissipation layer 220c constitute a heat dissipation structure 220 as in fig. 10.

In some embodiments, the initial heat dissipation structure may also be directly planarized to form the heat dissipation pillars 220a, the first heat dissipation layer 220b, and the second heat dissipation layer 220c as shown in fig. 17.

It should be noted that, in addition to the first heat dissipation layer 220B and the second heat dissipation layer 220c, a first connection pad 240 located in the second region B is formed.

It should be further noted that, in other embodiments, the formed heat dissipation structure 220 may further include: forming a first heat dissipation layer 220b and/or a second heat dissipation layer 220c; the first heat dissipation layer 220b covers the top surfaces of the heat dissipation pillars 220a, or covers the top surfaces of the heat dissipation pillars 220a and the first region a; the second heat dissipation layer 220c covers the bottom surface of the heat dissipation pillar 220a, or covers the bottom surfaces of the heat dissipation pillar 220a and the first region a.

In some embodiments, referring to fig. 18, the method for forming the interposer 200 further includes: forming a heat dissipation bump 220d on the surface of the first heat dissipation layer 220 b; the heat dissipation post 220a, the first heat dissipation layer 220b, the second heat dissipation layer 220c, and the heat dissipation bump 220d constitute a heat dissipation structure 220 as in fig. 11.

In practice, after the initial heat dissipation structure is formed, the initial heat dissipation structure is etched back to form the heat dissipation bump 220d, the heat dissipation post 220a, the first heat dissipation layer 220b, and the second heat dissipation layer 220c as shown in fig. 18. Wherein the heat dissipation bump 220d, the heat dissipation post 220a, the first heat dissipation layer 220b, and the second heat dissipation layer 220c constitute the heat dissipation structure 220 as in fig. 11.

In some embodiments, the heat dissipation pillars 220a, the first heat dissipation layer 220b, the second heat dissipation layer 220c, and the heat dissipation bumps 220d may also be formed by: after the above step 2, first, a metal material may be deposited or plated in the etched holes C to form the heat dissipation pillars 220a located in the first region a; next, the first seed layer 410, the second seed layer 420, and the heat dissipation pillars 220a located on the surface (i.e., the top and bottom surfaces) of the first region a may be exposed through a photoimaging process, and the first heat dissipation layer 220b and the second heat dissipation layer 220c shown in fig. 17 may be grown on the exposed surfaces of the first seed layer 410, the second seed layer 420, and the heat dissipation pillars 220a through an electroplating process. Finally, the first heat dissipation layer 220b is used as a growth substrate, and the heat dissipation bump 220d shown in fig. 18 is grown on the surface of the first heat dissipation layer 220 b.

It should be noted that, in other embodiments, the heat dissipation bump 220d may also be formed by an etching process. For example, a whole layer structure may be formed on a surface lower than the first heat dissipation layer 220b, and then the whole layer structure is etched to form the heat dissipation bump 220d.

In the embodiment of the disclosure, after forming the heat dissipation structure 220, the method for forming the interposer 200 further includes the following steps:

first, the exposed first seed layer 410 and second seed layer 420 are removed, forming the structure shown in fig. 19.

Next, a first solder mask layer 250 (see fig. 20) is formed on the top and bottom surfaces of the core layer 210 and exposing a portion of the first connection wire 230;

finally, the interposer 200 is subjected to surface treatment. For example, nickel, gold, or electroless nickel, palladium, gold.

In some embodiments, referring to fig. 21, before stacking the interposer 200 on the surface of the first package unit 310, the method of the semiconductor package structure 300 further includes: forming a heat conductive layer 340 on a surface of the first chip 311; the thermally conductive layer 340 is in direct thermal contact with the first chip.

In implementation, a first heat conductive material may be coated on the surface of the first chip 311 to form a first heat conductive layer 340; the thermally conductive material may be a TIM, or any other suitable material.

In some embodiments, the method of the semiconductor package structure 300 further comprises: depositing a second thermally conductive material on the surface of the interposer 200 before stacking the second package unit 330 onto the interposer 200, forming a third heat spreader 350; the second thermally conductive material may be any suitable high thermal conductive material.

In other embodiments, the interposer 200 may be directly bonded to the second package unit 330 without depositing the second heat conductive material on the surface of the interposer 200, and the gap between the interposer 200 and the second package unit 330 may form the third heat dissipation layer 350.

Next, referring to fig. 12, 11 and 21, step S102 is performed to sequentially stack the interposer 200 and the second encapsulation unit 330 to the surface of the first encapsulation unit 310; wherein the first area a covers the first chip.

In the embodiment of the disclosure, referring to fig. 11, a thermocompression bonding (thermal compression bonding, TCB) process may be used to bond the interposer 200 to the first package unit 310 through the connection element 360, so as to implement interconnection between the interposer 200 and the first package unit 310; next, the second package unit 330 may be soldered to the surface of the interposer 200 through the connection element 360 by a surface mount technology (Surface Mounted Technology, SMT). Wherein, after interconnection of the interposer 200 and the first encapsulation unit 310, the gap between the interposer 200 and the first encapsulation unit 310 may be filled with the molding compound 130.

Note that, the interposer 200 may be any of the above embodiments, for example, when the interposer 200 is configured as shown in fig. 7, a semiconductor package structure as shown in fig. 10 may be formed.

In some embodiments, referring to fig. 21, before stacking the interposer 200 on the surface of the first package unit 310, the method of the semiconductor package structure 300 further includes: forming a heat conductive layer 340 on a surface of the first chip 311; the thermally conductive layer 340 is in direct thermal contact with the first chip.

In implementation, a first heat conductive material may be coated on the surface of the first chip 311 to form a first heat conductive layer 340; the thermally conductive material may be a TIM, or any other suitable material.

In the embodiment of the present disclosure, the interposer 200 and the second encapsulation unit 330 may be sequentially stacked to the first encapsulation unit 310 through the connection element 360 through a thermal compression bonding (Thermal Compression Bonding, TCB) process, and the electrical connection between the first encapsulation unit 310, the interposer 200, and the second encapsulation unit 330 is achieved.

In some embodiments, the method of the semiconductor package structure 300 further comprises: depositing a second thermally conductive material on the surface of the interposer 200 before stacking the second package unit 330 onto the interposer 200, forming a third heat spreader 350; the second thermally conductive material may be any suitable high thermal conductive material.

In other embodiments, the interposer 200 may be directly bonded to the second package unit 330 without depositing the second heat conductive material on the surface of the interposer 200, and the gap between the interposer 200 and the second package unit 330 may form the third heat dissipation layer 350.

The semiconductor package structure formed in the embodiment of the present disclosure is similar to the semiconductor package structure in the above embodiment, and for technical features that are not fully disclosed in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and a detailed description is omitted here.

The semiconductor packaging structure provided by the embodiment of the disclosure comprises the interposer, and the interposer is provided with the heat dissipation structure, and because the heat dissipation structure is positioned on the first chip, the heat dissipation treatment can be carried out on the first chip through the heat dissipation structure, so that the performance of the formed semiconductor packaging structure is improved.

In several embodiments provided by the present disclosure, it should be understood that the disclosed structures and methods may be implemented in a non-targeted manner. The above-described structural embodiments are merely illustrative, and for example, the division of units is merely a logic function division, and there may be other division manners in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.

Features disclosed in the several method or structure embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or structure embodiments.

The above is merely some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present disclosure, and should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (12)

1. An interposer for transferring electrical signals between a plurality of stacked structures in a semiconductor package, comprising: a core layer and a heat dissipation structure;

the core layer comprises at least a first region;

the heat dissipation structure penetrates through the first area at least along a first direction; the first direction is a thickness direction of the core layer.

2. The interposer of claim 1, the heat dissipation structure comprising: at least one heat dissipation post penetrating through the first region along the first direction;

the plurality of heat dissipation posts are uniformly or non-uniformly distributed at intervals in the first area.

3. The interposer of claim 2, the heat dissipation structure further comprising: the first heat dissipation layer and/or the second heat dissipation layer;

The first heat dissipation layer covers the top surface of the heat dissipation post, or covers the top surfaces of the heat dissipation post and the first region;

the second heat dissipation layer covers the bottom surface of the heat dissipation post, or covers the bottom surfaces of the heat dissipation post and the first region.

4. The interposer of claim 3, the heat spreading structure further comprising: at least one heat dissipation bump positioned on the surface of the first heat dissipation layer;

the heat dissipation convex blocks are distributed on the surface of the first heat dissipation layer at intervals.

5. A semiconductor package structure, comprising: a first encapsulation unit, an interposer according to any one of claims 1 to 4, and a second encapsulation unit;

the first packaging unit, the interposer and the second packaging unit are sequentially bonded from bottom to top along the first direction; the first packaging unit at least comprises a first chip attached to the first substrate; the first area covers the first chip;

the heat dissipation structure is located on the first chip.

6. The semiconductor package structure of claim 5, further comprising: a heat conductive layer and a third heat dissipation layer; wherein, the liquid crystal display device comprises a liquid crystal display device,

the heat conducting layer is positioned between the first chip and the heat radiating structure and is in direct thermal contact with the first chip and the heat radiating structure;

The third heat spreader is located between the interposer and the second package unit and is in direct thermal contact with the interposer and the second package unit.

7. A method of forming a semiconductor package, the method comprising:

providing a first packaging unit, a second packaging unit and an interposer; the first packaging unit at least comprises a first chip attached to the first substrate; the interposer includes at least a core layer and a heat dissipation structure extending through a first region of the core layer in at least a first direction;

stacking the interposer and the second packaging unit to the surface of the first packaging unit in sequence; wherein the first region covers the first chip;

the first direction is a thickness direction of the first substrate.

8. The method of claim 7, the method of forming the interposer comprising:

providing a core layer, the core layer comprising at least a first region;

etching the first region to form at least one blind hole structure penetrating through the first region;

forming a heat dissipation column in the blind hole structure; wherein, the heat dissipation post constitutes heat radiation structure.

9. The method of claim 8, the method of forming an interposer further comprising:

forming a first heat dissipation layer covering the top surface of the heat dissipation post and the top surface of the first region, and a second heat dissipation layer covering the bottom surface of the heat dissipation post and the bottom surface of the first region; the heat dissipation column, the first heat dissipation layer and the second heat dissipation layer form the heat dissipation structure.

10. The method of claim 9, the method of forming an interposer further comprising:

and forming a heat dissipation bump on the surface of the first heat dissipation layer.

11. The method of any of claims 7 to 10, prior to stacking the interposer to the surface of the first packaging unit, the method further comprising:

forming a heat conduction layer on the surface of the first chip; the thermally conductive layer is in direct thermal contact with the first chip.

12. The method of claim 11, the method further comprising:

forming a third heat dissipation layer on the surface of the interposer before stacking the second packaging unit to the interposer;

or alternatively, the process may be performed,

after stacking the second package unit to the interposer, a gap between the second package unit and the interposer constitutes the third heat dissipation layer.