CN113948500A - Semiconductor packaging structure - Google Patents
Semiconductor packaging structure Download PDFInfo
- Publication number
- CN113948500A CN113948500A CN202111159588.1A CN202111159588A CN113948500A CN 113948500 A CN113948500 A CN 113948500A CN 202111159588 A CN202111159588 A CN 202111159588A CN 113948500 A CN113948500 A CN 113948500A
- Authority
- CN
- China
- Prior art keywords
- stacked
- passive
- semiconductor package
- passive element
- package structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The semiconductor package structure provided by the present disclosure integrates Discrete elements (Discrete components) in advance to form a stacked passive element integrated body, and the stacked passive element integrated body can provide a signal transmission path in the Z-axis direction, so that an internal signal transmission path between the Discrete elements can be shortened, and the signal transmission loss between the Discrete elements can be reduced. In addition, when the stacked passive element integrated body is embedded in the substrate and the dielectric material is pressed, the generation of cavities can be avoided, and the productivity and the yield are improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor package structure.
Background
Fig. 1-3 show a method for integrating passive devices, first referring to fig. 1, providing a substrate 1 having a cavity 101, then referring to fig. 2, using a pick-up device to embed a plurality of passive devices 2 into the cavity 101, and finally referring to fig. 3, after laminating a dielectric material 3, forming a via hole by laser and forming a circuit layer 4 by electroplating.
However, the planar placement method integrates the embedded passive devices, resulting in an increase in the dimension in the X-Y plane. In addition, the connection path between the passive elements 2 is long, resulting in a large signal loss. When the passive devices 2 are repeatedly picked and placed, the spacing between the passive devices 2 is inconsistent due to the picking and placing process error, and when the spacing is small, the dielectric material 3 is not easy to be pressed, and voids (void) are easily generated in the dielectric material 3.
Disclosure of Invention
The present disclosure provides a semiconductor package structure.
In a first aspect, the present disclosure provides a semiconductor package structure, including: the stacked passive element integrated body is provided with a plurality of passive elements which are stacked from bottom to top, and the stacked passive element integrated body provides a signal transmission path in a first direction.
In some optional embodiments, a first conductive layer is disposed between the passive elements adjacent to each other along the first direction in the stacked passive element integrated body, so as to achieve electrical connection in the first direction.
In some optional embodiments, the passive element has a pair of terminal electrodes, and the first conductive layer is disposed on the terminal electrodes.
In some alternative embodiments, a non-conductive layer is disposed between the passive elements adjacent to each other along the first direction in the stacked passive element integrated body.
In some alternative embodiments, the passive element has a pair of terminal electrodes, and the non-conductive layer is disposed on the terminal electrodes.
In some alternative embodiments, an insulating layer is disposed between the passive elements adjacent to each other along the first direction in the stacked passive element integrated body.
In some alternative embodiments, an insulating layer is disposed between the passive elements adjacent to each other along the second direction in the stacked passive element integrated body.
In some alternative embodiments, an insulating layer is disposed between the passive elements adjacent to each other along the third direction in the stacked passive element integrated body.
In some alternative embodiments, a second conductive layer is disposed between the passive elements adjacent to each other along the second direction in the stacked passive element integrated body.
In some alternative embodiments, a second conductive layer is disposed between the passive elements adjacent to each other along the third direction in the stacked passive element integrated body.
In some optional embodiments, the stacked passive element integration body includes a plurality of stacked layers along the first direction, each of the stacked layers includes a plurality of passive elements, and each of the passive elements in each of the stacked layers is in an equal-pitch arrangement/unequal-pitch arrangement.
In some optional embodiments, the stacked layers along the first direction in the stacked passive element integrated body are a first capacitance layer, an inductance layer and a second capacitance layer in sequence, the first/second capacitance layers comprise a plurality of capacitors, and the inductance layer comprises a plurality of inductors.
In some alternative embodiments, the stacked passive element integration includes a plurality of stack groups, each stack group includes a plurality of passive elements, and a spacing between the passive elements within each stack group is different from a spacing between the stack groups.
In some optional embodiments, the first direction is a Z direction, the second direction is an X direction and the third direction is a Y direction.
In some optional embodiments, the stacked passive element integration further comprises:
the first molding sealing layer coats the plurality of passive elements and the gaps filled between the passive elements.
In some optional embodiments, the semiconductor package structure further comprises:
the substrate is provided with a cavity, and the stacked passive element integrated body is arranged in the cavity.
In some optional embodiments, the semiconductor package structure further comprises:
and the dielectric material is filled between the stacked passive element integrated body and the cavity.
In some optional embodiments, the semiconductor package structure further comprises:
the stacked passive element integrated body is arranged on the power management chip, and the stacked passive element is electrically connected with the power management chip.
In some optional embodiments, the semiconductor package structure further comprises:
and the second molding layer coats the power management chip.
In some optional embodiments, the semiconductor package structure further comprises:
and the rewiring layer is arranged between the second molding layer and the stacked passive element integrated body and is respectively and electrically connected with the stacked passive element integrated body and the power management chip.
The semiconductor packaging structure provided by the disclosure integrates the passive elements in advance to form the stacked passive element integrated body, and the stacked passive element integrated body can provide a signal transmission path in the Z-axis direction, so that the internal signal transmission path between the passive elements can be shortened, and the signal transmission loss between the passive elements can be reduced. In addition, when the stacked passive element integrated body is embedded in the substrate and the dielectric material is pressed, the generation of cavities can be avoided, and the productivity and the yield are improved.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIGS. 1-3 are schematic structural diagrams of integrated passive devices during fabrication;
fig. 4-7 are first through fourth schematic structural views of a semiconductor package structure according to the present disclosure;
fig. 8 to 15 are schematic structural views in the manufacturing process of the semiconductor package structure according to the present disclosure.
Description of the symbols:
1-substrate, 101-cavity, 2-passive element, 21-terminal electrode, 3-laminating material, 4-circuit layer, 5-stacked passive element integrated body, 6-first conducting layer, 7-non-conducting layer, 8-insulating layer, 9-second conducting layer, 10-first molding layer, 11-dielectric material, 12-power management chip, 13-second molding layer, 14-rewiring layer, 15-adhesive layer and 16-carrier.
Detailed Description
The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.
It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In addition, the terms "above", "first", "second" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present disclosure, and changes or modifications of the relative relationship may be made without substantial changes in the technical content.
It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.
It should be readily understood that the meaning of "in.. on," "over,", and "above" in this disclosure should be interpreted in the broadest sense such that "in.. on" not only means "directly on something," but also means "on something" including an intermediate member or layer between the two.
Furthermore, spatially relative terms, such as "below," "lower," "over," "upper," and the like, may be used in this disclosure to describe one element or component's relationship to another element or component as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used in this disclosure interpreted accordingly as such.
In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 4 is a first structural schematic of a semiconductor package structure according to the present disclosure. The semiconductor package structure shown in fig. 4 includes a stacked passive component integrated body 5. The stacked passive element integrated body 5 may have a plurality of passive elements 2 stacked from bottom to top. The stacked passive component integrated body 5 can provide a signal transmission path in a first direction. The stacked passive component integrated body 5 may include a first molding layer 10. The first molding compound 10 may cover the plurality of passive elements 2 and fill gaps between the passive elements 2.
In the present embodiment, the passive element 2 may be a Discrete element (Discrete Component), such as a resistor, a capacitor, and an inductor. The first direction may be a Z-axis direction. The first direction may be a direction perpendicular to the upper surface of any one of the passive elements 2. A first conductive layer 6 may be disposed between the passive elements 2 adjacent to each other along the first direction in the stacked passive element integrated body 5 to realize the electrical connection along the first direction. Specifically, the passive element 2 may have a pair of terminal electrodes, and the first conductive layer 6 may be provided on the terminal electrodes. The first conductive layer 6 may use a conductive material of metal or metal alloy, such as gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof. The first conductive layer 6 may be made of conductive paste, such as silver-based conductive paste, gold-based conductive paste, or copper-based conductive paste. The conductive adhesive is an adhesive which has certain conductivity after being cured or dried. The conductive adhesive has conductive performance and adhesive strength. The passive elements 2 in the first direction can be connected by means of a conductive glue and an electrical path is formed between the passive elements 2. The resistance between the passive element 2 and the passive element 2 can be reduced by the conductive adhesive. In addition, compared with the reliability problem of using solder to connect the passive element in some cases (the melting point of the solder is low, and multiple thermal processing processes may cause the solder to melt, so that the reliability problem occurs), the present disclosure uses the conductive material to realize the electrical connection of the passive element 2 along the first direction, and still has good connection characteristics and reliability after multiple thermal processing processes.
In this embodiment, an insulating layer 8 may be disposed between the passive elements 2 adjacent to each other along the first direction in the stacked passive element integrated body 5. In a top view, an insulating layer 8 may be disposed between the passive elements 2 adjacent to each other along the second direction in the stacked passive element integrated body 5 (as shown in fig. 10 (a)). An insulating layer 8 may be disposed between the passive elements 2 adjacent to each other in the third direction in the stacked passive element integrated body 5. The first direction, the second direction, and the third direction may be perpendicular to each other. The first direction may be a Z direction, the second direction may be an X direction, and the third direction may be a Y direction. Insulating layers 8 can be arranged between the adjacent passive elements 2 in all directions, so that the bonding strength between the passive elements 2 can be enhanced, and the short circuit can be avoided by effectively blocking when the connection is carried out through electroplating.
In this embodiment, from a top view, a second conductive layer 9 may be disposed between the passive elements 2 adjacent to each other along the second direction in the stacked passive element integrated body 5 (as shown in fig. 14 (b)). A second conductive layer 9 may be disposed between the passive elements 2 adjacent to each other along the third direction in the stacked passive element integrated body 5 (as shown in fig. 14 (b)). Therefore, signal transmission paths in all directions can be formed, and the requirement of electrical connection in all directions is met.
In this embodiment, the stacked passive element integrated body 5 may include a plurality of stacked layers along the first direction. Each stack may comprise a plurality of passive elements 2. The passive elements 2 in each stacked layer may be arranged at equal intervals (as shown in fig. 8 (a)) or at unequal intervals (as shown in fig. 8 (b)) from a top view. The stacked passive element integration 5 may include a plurality of stacked groups. Each stack group may comprise a plurality of passive elements 2. The spacing between the passive elements 2 in each of the stacked groups is different from the spacing between the stacked groups (as shown in fig. 8 (b)).
In a practical application scenario, the stacked layers of the stacked passive device integrated body 5 along the first direction may be a first capacitor layer, an inductor layer, and a second capacitor layer in sequence. The first/second capacitive layer may comprise a plurality of capacitors. The inductive layer may include a plurality of inductors.
Fig. 5 is a second structural schematic of a semiconductor package structure according to the present disclosure. According to the requirement of electrical connection between the passive elements 2 adjacent to each other along the first direction in the stacked passive element integrated body 5, the first conductive layer 6 or the non-conductive layer 7 is determined to be arranged between the adjacent passive elements 2. As shown in fig. 5, when no electrical connection is required, a non-conductive layer 7 may be disposed between the passive components adjacent to each other along the first direction in the stacked passive component integrated body 5. A non-conductive layer 7 may be disposed between the passive elements adjacent to each other along the first direction in the stacked passive element assembly 5. Specifically, the passive element 2 may have a pair of terminal electrodes, and the non-conductive layer 7 may be provided on the terminal electrodes. The non-conductive layer 7 may be formed by bonding the adjacent passive elements 2 with a non-conductive paste (NCP). As shown in fig. 5, when electrical connection is required, a first conductive layer 6 may be disposed between the passive elements 2 adjacent to each other along the first direction in the stacked passive element integrated body 5. The conductive material is used to realize the electrical connection of the passive component 2 along the first direction, and the non-conductive material is used to block the electrical connection of the passive component 2 along the first direction, so that various internal conductive connection circuits can be formed in the stacked passive component integrated body 5 to achieve the electrical requirement design of different purposes.
Fig. 6 is a third structural schematic of a semiconductor package structure according to the present disclosure. The semiconductor package structure shown in fig. 6 may include a substrate 1, a stacked passive device integrated body 5, and a dielectric material 11. The substrate 1 may have a cavity 101. The stacked passive element integrated body 5 can be placed in the cavity 101 as an integrated body. The dielectric material 11 may be filled between the stacked passive component integrated body 5 and the cavity 101.
In the present embodiment, the substrate 1 may be, for example, a Printed Circuit Board (PCB). The first molding layer 10 in the stacked integrated passive device 5 can cover a plurality of passive devices and fill the gaps between the passive devices 2, and the insulating layer 8 in the stacked integrated passive device 5 can fill the gaps between the passive devices 2, so that in the subsequent process, after the stacked integrated passive device 5 is taken and placed into the cavity 101 of the substrate 1, and the dielectric material 11 is pressed, the generation of voids can be avoided, and the process yield can be increased. Therefore, the situation that the dielectric material is not easy to press due to the small distance between the passive elements 2 and further the dielectric material is easy to generate holes can be avoided.
Fig. 7 is a fourth structural schematic of a semiconductor package structure according to the present disclosure. The semiconductor package structure shown in fig. 7 may include a stacked passive device integrated body 5, a power management chip 12, a redistribution layer 14, and a second molding compound layer 13. The second molding layer 13 may encapsulate the power management chip 12. The second molding layer 13 may be substantially spaced apart from the first molding layer 10. The stacked passive component assembly 5 may be disposed on the power management chip 12/the second molding layer 13. The redistribution layer 14 may be disposed between the second molding layer 13 and the stacked passive component integrated body 5, and electrically connects the stacked passive component integrated body 5 and the power management chip 12, respectively. The stacked passive component integrated body 5 can be electrically connected with the power management chip 12 through the rewiring layer 14. The redistribution layer 14 and the power management chip 12 can be used as a substrate, and the stacked passive component integrated body 5 is disposed to shorten the electrical path between the power management chip 12 and the stacked passive component integrated body 5.
Referring to fig. 8 to 15, fig. 8 to 15 are schematic structural diagrams illustrating a manufacturing process of a semiconductor package structure according to the present disclosure.
In a first step, as shown in fig. 8, the passive component 2 is picked up and placed on the carrier 16 provided with the glue layer 15 to form a first stack.
From the top view, as shown in fig. 8 (a), the passive elements 2 in the first stacked layer may be arranged at equal intervals. As shown in fig. 8 (b), the passive elements 2 in the first stacked layer may be arranged at unequal intervals. Specifically, the passive elements 2 in the first stacked layer may be distributed at different positions, for example, the first group a, the second group B, and the third group C may be distributed, and the distance between the passive element 2 and the passive element 2 in each group may be different from the distance between the groups.
In a second step, as shown in fig. 9, a first conductive layer 6 is provided on each passive element 2 of the first stacked layer (in the Z-axis direction). Fig. 9 (a) and (b) are top views of the semiconductor package shown in fig. 9.
In a third step, as shown in fig. 10, an insulating layer 8 is provided on each passive element 2 of the first stacked layer (in the Z-axis direction). Here, the order between the second step and the third step may also be reversed, i.e. the insulating layer 8 may be provided first and then the first conductive layer 6.
From a top view, as shown in fig. 10 (a), the insulating layer 8 may be disposed between the passive elements 2 adjacent to each other along the Y-axis direction, so as to enhance the bonding strength between the passive elements 2, and also effectively block the short circuit when the subsequent connection is performed by electroplating.
In the fourth step, as shown in fig. 11, the passive element 2 is placed on the first stacked layer to form a second stacked layer. Fig. 11 (a) and (b) are top views of the semiconductor package shown in fig. 11.
In a fifth step, as shown in fig. 12A, a first conductive layer 6 is provided on each passive element 2 of the second stacked layer. An insulating layer 8 is provided on each passive element 2 of the second stack. Fig. 12A (a) and (b) are top views of the semiconductor package shown in fig. 12A. The fifth step may also be to provide a first conductive layer 6 and/or a non-conductive layer 7 on each passive element 2 of the second stack as shown in fig. 12B. An insulating layer 8 is provided on each passive element 2 of the second stack.
In the sixth step, as shown in fig. 13, the passive element 2 is placed on the second stacked layer to form a third stacked layer. Fig. 13 (a) and (b) are top views of the semiconductor package shown in fig. 13.
In the seventh step, as shown in fig. 14, the second conductive layer 9 is formed in the X-axis direction, the Y-axis direction, and the Z-axis.
Fig. 14 (a) and (b) are top views of the semiconductor package shown in fig. 14. As shown in fig. 14 (b), the second conductive layer 9 is formed between the passive elements 2 in each group, and the second conductive layer 9 is not formed between the groups, which can be realized by selective plating. Specifically, the groups may be spaced far enough apart (the distance between the groups is greater than the distance between the passive elements 2 in the group), and the electrical connection between the adjacent passive elements 2 close enough to each other may be completed by the selective electroplating method, and the electrical connection between the adjacent passive elements 2 far enough to each other may not be completed, so that the second conductive layer 9 is only formed between the passive elements 2 in each group, and is not formed between the groups. The selective plating can be realized not only by controlling the distance between the adjacent passive elements 2, but also by controlling the process parameters (such as current density/time/temperature, etc.), or by pre-setting the insulating material to separate the plating, so as to form a plurality of internal conductive traces in the stacked passive element integrated body 5 to achieve different electrical requirements.
In addition, the passive elements 2 within each group may be electrically interconnected in the X-Y plane. The passive elements in each group may not be electrically connected to each other in the X-Y plane, for example, one passive element 2 may be electrically connected to the passive element 2 on the diagonal side, and no electrical connection may be made between the adjacent passive elements 2. In each group, a first conductive layer 6 may be provided for electrical connection between the passive elements 2 adjacent to each other in the Z-axis direction, and a non-conductive layer 7 may be provided for electrical isolation.
Eighth, as shown in fig. 15, a first molding layer 10 is formed to cover the passive device 2, and then the first molding layer 10 is thinned to expose the upper surface of the passive device 2 in the third stacked layer, so as to obtain the stacked passive device integrated body 5. Here, the thinning may be, for example, a grinding (grinding) or Chemical Mechanical Polishing (CMP) process. The first molding layer 10 is thinned to expose the terminal electrode of the passive element 2, which can be used as a connecting point for the stacked passive element integrated body 5 to be electrically connected up and down. Fig. 15 (a) and (b) are top views of the semiconductor package shown in fig. 15.
The semiconductor package structure provided by the present disclosure integrates the passive elements 2 in advance to form the stacked passive element integrated body 5, and the stacked passive element integrated body 5 can provide a signal transmission path in the Z-axis direction, so that the internal signal transmission path between the passive elements 2 can be shortened, and the signal transmission loss between the passive elements 2 can be reduced. In addition, when the stacked passive component integrated body 5 is embedded in the substrate 1 and then the dielectric material 11 is pressed, the generation of voids can be avoided, and the productivity and the yield can be improved.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present disclosure and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed in this disclosure have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated in the present disclosure, the order and grouping of the operations is not a limitation of the present disclosure.
Claims (10)
1. A semiconductor package structure, comprising:
the stacked passive element integrated body is provided with a plurality of passive elements which are stacked from bottom to top, and the stacked passive element integrated body provides a signal transmission path in a first direction.
2. The semiconductor package structure of claim 1, wherein a first conductive layer is disposed between adjacent passive devices along the first direction in the stacked passive device integration body to achieve electrical connection in the first direction.
3. The semiconductor package structure of claim 2, wherein an insulating layer is disposed between adjacent passive elements along the first direction, the second direction, or the third direction in the stacked passive element integration.
4. The semiconductor package structure of claim 2 or 3, wherein a second conductive layer is disposed between the passive elements adjacent to each other along the second direction or the third direction in the stacked passive element integrated body.
5. The semiconductor package structure of claim 4, wherein the stacked passive element assembly comprises a plurality of stack groups, each stack group comprising a plurality of passive elements, a pitch between passive elements within each stack group being different from a pitch between stack groups.
6. The semiconductor package structure of claim 1, wherein the stacked passive element integration further comprises:
the first molding sealing layer coats the plurality of passive elements and the gaps filled between the passive elements.
7. The semiconductor package structure of claim 6, wherein the semiconductor package structure further comprises:
the substrate is provided with a cavity, and the stacked passive element integrated body is arranged in the cavity;
and the dielectric material is filled between the stacked passive element integrated body and the cavity.
8. The semiconductor package structure of claim 7, wherein the semiconductor package structure further comprises:
the stacked passive element integrated body is arranged on the power management chip, and the stacked passive element is electrically connected with the power management chip.
9. The semiconductor package structure of claim 8, wherein the semiconductor package structure further comprises:
and the rewiring layer is arranged between the power management chip and the stacked passive element integrated body and is respectively and electrically connected with the stacked passive element integrated body and the power management chip.
10. The semiconductor package structure of claim 9, wherein the semiconductor package structure further comprises:
and the second molding sealing layer coats the power management chip and is substantially separated from the first molding sealing layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111159588.1A CN113948500A (en) | 2021-09-30 | 2021-09-30 | Semiconductor packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111159588.1A CN113948500A (en) | 2021-09-30 | 2021-09-30 | Semiconductor packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113948500A true CN113948500A (en) | 2022-01-18 |
Family
ID=79329029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111159588.1A Pending CN113948500A (en) | 2021-09-30 | 2021-09-30 | Semiconductor packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113948500A (en) |
-
2021
- 2021-09-30 CN CN202111159588.1A patent/CN113948500A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103715166B (en) | Device and method for component package | |
| KR101614960B1 (en) | Chip scale stacked die package | |
| US7706148B2 (en) | Stack structure of circuit boards embedded with semiconductor chips | |
| US20070235865A1 (en) | Semiconductor module havingdiscrete components and method for producing the same | |
| CN105826209B (en) | Packaging structure and manufacturing method thereof | |
| KR20110084444A (en) | Flexible and stackable semiconductor die packages, systems using the same, and methods of making the same | |
| CN211150513U (en) | Package body | |
| CN103460822A (en) | Multilayer substrate with integrated chip component and method for manufacturing same | |
| CN107154388B (en) | Semiconductor package and method of manufacturing the same | |
| TW200828523A (en) | Multi-component package with both top and bottom side connection pads for three-dimensional packaging | |
| CN115312402B (en) | Laser-based redistribution and multi-stack packaging | |
| US20040029312A1 (en) | Integrated circuit and laminated leadframe package | |
| CN103229293A (en) | Semiconductor chip package, semiconductor module, and method for manufacturing same | |
| CN112701115B (en) | Three-dimensional heterogeneous integrated packaging structure of radio frequency front-end module and manufacturing method thereof | |
| CN106935517B (en) | Framework encapsulation structure of integrated passive devices and preparation method thereof | |
| CN114758994A (en) | Semiconductor device package and method of manufacturing the same | |
| CN101770994A (en) | Semiconductor package substrate with metal bumps | |
| CN110858582A (en) | Semiconductor package and method of manufacturing the same | |
| KR20230113491A (en) | Semiconductor package including a chip-substrate composite semiconductor device | |
| CN113948500A (en) | Semiconductor packaging structure | |
| CN115547850A (en) | Three-dimensional core particle packaging process and structure integrated on back of deep groove device | |
| US10991656B2 (en) | Semiconductor device package | |
| CN112435996A (en) | Semiconductor package device and method of manufacturing the same | |
| CN113496901A (en) | Chip embedded substrate structure, chip packaging structure and manufacturing method thereof | |
| CN113299626B (en) | Conductive assembly for multi-chip packaging and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |