CN111799251B - Power discrete device adopting multi-chip stacking structure and preparation method thereof - Google Patents

Power discrete device adopting multi-chip stacking structure and preparation method thereof Download PDF

Info

Publication number
CN111799251B
CN111799251B CN202010655248.7A CN202010655248A CN111799251B CN 111799251 B CN111799251 B CN 111799251B CN 202010655248 A CN202010655248 A CN 202010655248A CN 111799251 B CN111799251 B CN 111799251B
Authority
CN
China
Prior art keywords
chip
heat dissipation
dissipation substrate
lead frame
silver paste
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010655248.7A
Other languages
Chinese (zh)
Other versions
CN111799251A (en
Inventor
杨伊杰
蒋卫娟
缑娟
孙炎权
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huayi Microelectronics Co ltd
Original Assignee
Huayi Microelectronics Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huayi Microelectronics Co ltd filed Critical Huayi Microelectronics Co ltd
Priority to CN202010655248.7A priority Critical patent/CN111799251B/en
Publication of CN111799251A publication Critical patent/CN111799251A/en
Application granted granted Critical
Publication of CN111799251B publication Critical patent/CN111799251B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention belongs to the technical field of power device packaging structures, and particularly relates to a power discrete device adopting a multi-chip stacking structure and a preparation method thereof, wherein the power discrete device adopting the multi-chip stacking structure comprises a heat dissipation substrate; at least two chips adhered to the heat dissipation substrate respectively, or adhered to the heat dissipation substrate in a stacked manner; wherein, the conductive silver paste layer is arranged between the at least two chips and the heat dissipation substrate or between the at least two chips; the dispensing pattern of the conductive silver paste layer is star-shaped or cross-shaped. The preparation method of the power discrete device adopting the multi-chip stacking structure can prepare the power discrete device adopting the multi-chip stacking structure. The power discrete device adopting the multi-chip stacking structure and the preparation method thereof provided by the invention can ensure the heat dissipation requirement of the power device and realize the purpose of miniaturization of the packaging structure of the high-power device.

Description

Power discrete device adopting multi-chip stacking structure and preparation method thereof
Technical Field
The invention belongs to the technical field of power device packaging structures, and particularly relates to a power discrete device adopting a multi-chip stacking structure and a preparation method thereof.
Background
In recent years, third generation semiconductor materials (mainly including SiC, gaN, diamond, etc.) are becoming the focus of global semiconductor market competition by virtue of their superior performance and tremendous market prospects. Compared with the first-generation and second-generation semiconductor materials, the third-generation semiconductor material has the advantages of high heat conductivity, high breakdown field strength, high saturated electron drift rate, high bonding energy and the like, can meet the new requirements of modern electronic technology on severe conditions such as high temperature, high power, high voltage, high frequency, radiation resistance and the like, and is a material with prospect in the field of semiconductor materials.
The third generation semiconductor material is mostly applied to power devices, along with the development of the power devices, the requirements on packaging products are higher and higher, the thickness of the products is thinned, the volume is miniaturized, the functional polytypy is mainstream, the market of high-power and small-volume packaging technology is larger and larger, and the development trend of the power devices is met by the high-power, high-heat dissipation and small-volume packaging technology. The power of the product is increased, the functions are increased, the integration level of the packaged chips, the number of chips and the heat dissipation performance of devices are required to be continuously improved, the packaging volume tends to be miniaturized, and a multi-chip stacked packaging structure is required to be adopted and high heat conduction materials are required to be selected as packaging materials to achieve the purpose.
In the packaging process of power discrete devices adopting a multi-chip stacked structure by GaN (gallium nitride) or SiC (silicon nitride), due to the existence of large current and large voltage, the common adhesive sheet can not meet the heat conduction requirement, and the stacked packaging of chips is difficult to realize by using a welding material adhesive sheet.
In order to solve the problems, the invention provides a power discrete device adopting a multi-chip stacking structure and a preparation method thereof.
Disclosure of Invention
It is an object of the present invention to address at least the above problems and/or disadvantages and to provide at least the advantages described below.
It is still another object of the present invention to provide a power discrete device employing a multi-chip stacked structure, which can not only ensure the heat dissipation requirement of the power device, but also achieve miniaturization of the package structure of the high-power device.
The invention also aims to provide a preparation method of the power discrete device adopting the multi-chip stacking structure, the preparation process is simple and easy to operate, the environment is protected, no pollution is caused, and the prepared power discrete device can ensure the heat dissipation requirement of the power device and realize the miniaturization of the packaging structure of the high-power device.
To achieve these objects and other advantages and in accordance with the purpose of the invention, there is provided a power discrete device employing a multi-chip stack structure, comprising:
a heat-dissipating substrate;
at least two chips adhered to the heat dissipation substrate respectively, or adhered to the heat dissipation substrate in a stacked manner;
wherein, the conductive silver paste layer is arranged between the at least two chips and the heat dissipation substrate or between the at least two chips;
the dispensing pattern of the conductive silver paste layer is star-shaped or cross-shaped.
Preferably, the conductive silver paste layer is a nano-sintered silver paste layer, and the thickness of the nano-sintered silver paste layer is 25-50 um.
Preferably, the at least two chips comprise a first chip and a second chip, and the first chip and the second chip are respectively adhered to the heat dissipation substrate through the nano-sintered silver paste layer; or the first chip is adhered to the heat dissipation substrate, the second chip is adhered to the first chip, the first chip is adhered to the heat dissipation substrate, and the second chip is adhered to the first chip through the nano-sintering silver paste layer.
Preferably, a via hole is arranged on the heat dissipation substrate, and a metal layer is electroplated in the via hole or a copper column is added in the via hole;
the heat dissipation substrate is one of an insulating aluminum substrate, a ceramic substrate and a ceramic copper-clad substrate.
Preferably, the heat dissipation substrate is an ALN ceramic copper-clad substrate with a three-layer structure or Si with a three-layer structure 3 N 4 Ceramic copper-clad substrate or ALN ceramic with nine-layer structurePorcelain copper-clad substrate, or Si of nine-layer structure 3 N 4 A ceramic copper-clad substrate.
Preferably, the heat dissipation substrate is adhered to the lead frame through the conductive silver paste layer, the at least two chips are connected with the electric connection part, and the electric connection part is connected with the outer pins on the lead frame.
The invention also provides a preparation method of the power discrete device, which comprises the following steps:
a heat dissipation substrate is adhered on the lead frame by adopting star-shaped or cross-shaped dispensing patterns of conductive silver paste, and baking is carried out;
bonding a first chip on the heat dissipation substrate by adopting star-shaped or cross-shaped dispensing patterns of conductive silver paste, baking, bonding a second chip on the first chip, and sequentially bonding and baking if the number of the chips exceeds two; or the first chip and the second chip are respectively adhered to the heat dissipation plate and baked at the same time, and if the number of the chips exceeds two, the chips are respectively adhered and baked at the same time, so that the upper core baking is completed;
Wherein the baking temperature is 200-250 ℃, and the baking is performed by adopting a temperature curve.
Preferably, the conductive silver paste is nano-sintered silver paste.
Preferably, the heat dissipation substrate is bonded on the lead frame by using star-shaped or cross-shaped dispensing patterns of conductive silver paste, and before baking, the method further comprises:
wafer thinning and scribing are carried out on the chip for standby;
when the selected frame is a bare copper frame, plasma cleaning is required to be carried out on the bare copper frame before the core is put on; carrying out plasma cleaning on the lead frame by utilizing argon and argon-hydrogen mixed gas for standby;
preferably, the method further comprises:
after the core is arranged, carrying out plasma cleaning on the lead frame by utilizing argon and argon-hydrogen mixed gas;
carrying out aluminum ribbon bonding connection on the parts of the chip, the heat-dissipating substrate and the lead frame, which need to bear large current, by using an aluminum ribbon bonding machine, and carrying out bonding connection on the parts, which bear small current, by using one of gold wires, copper wires and aluminum wires, so as to finish the pressure welding of the electric connection parts; or alternatively, the process may be performed,
the lead-free soldering paste is dotted on the corresponding positions of the chip, the lead frame and the heat dissipation substrate, then copper clips are placed on the soldering paste, and the copper clips are soldered through reflow soldering; after the copper Clip is welded, bonding connection is carried out on the areas of the chip, the heat dissipation substrate and the lead frame, which need to bear small current, by using gold wires, copper wires or aluminum wires, so as to finish the pressure welding of the electric connection parts; ultrasonic cleaning or weather cleaning is carried out on the frame after copper Clip welding, and residues after soldering paste welding are cleaned;
After pressure welding, uniformly spraying a layer of tackifier on the carrier of the lead frame and the wire-bonding tube leg, and finishing glue spraying after drying;
after glue spraying, the lead frame, the chip, the heat dissipation substrate and the electric connection part which are electrically connected are subjected to plastic packaging, so that the plastic packaging is completed;
after plastic packaging, electroplating a layer of tin with the thickness of 10-25 micrometers on the part of the lead frame which is not plastic-packaged, and drying for later use;
cutting and separating the tin-plated lead frame into individual devices, and forming pins to form a power discrete device;
and after testing the functional parameters of the power discrete devices, packaging and warehousing.
The invention at least comprises the following beneficial effects:
1. the power discrete device adopting the multi-chip stacking structure provided by the invention realizes high-power multi-chip stacking technology packaging by adopting the heat dissipation substrate and nano-sintering silver paste, and the packaging structure has high heat dissipation efficiency and can meet the requirements of high power, high reliability, multiple functions and miniaturization of the discrete device.
2. The power discrete device adopting the multi-chip stacking structure adopts the ALN or Si with nine-layer structure 3 N 4 The ceramic copper-clad substrate enables the discrete device to better realize the electric connection of products and improves the reliability of the products.
3. The ceramic copper-clad substrate adopted by the power discrete device adopting the multi-chip stacking structure can be further provided with the through holes, so that the upper metal layer and the lower metal layer are conducted, the wireless circuit connection is realized, the influence of glue overflow is avoided, and the reliability of a product is ensured.
4. The power discrete device adopting the multi-chip stacking structure provided by the invention adopts the nano-sintering silver paste layer as the bonding material layer, has ultrahigh heat conductivity which is several times or even hundreds of times that of other bonding sheet materials, and can greatly improve the reliability of products by adopting the nano-sintering silver paste as the bonding material.
5. According to the power discrete device adopting the multi-chip stacking structure, the aluminum strips or copper clips are used as electric connection materials for connection of the chips, the lead frames and the heat dissipation substrate to replace the traditional wire bonding technology, so that the power discrete device has better heat conduction performance, and the press welding or welding reliability of electric connection parts of products can be improved.
6. The power discrete device adopting the multi-chip stacking structure provided by the invention uses copper Clip welding, and the pin welding part of the frame can be free from silver plating, so that the cost caused by silver plating and poor silver plating is saved.
7. The preparation method of the power discrete device adopting the multi-chip stacking structure provided by the invention has the advantages that the process is simple and controllable, and the preparation method is suitable for mass production: bonding between the chip and the heat dissipation substrate and between the chips is performed by using nano-sintering silver paste as a sticky material, and a pressureless sintering process is adopted, so that the production process is simple and well controlled; the aluminum strip pressure welding and the aluminum wire pressure welding can be realized by the same equipment, so that the purchasing cost can be saved.
Drawings
FIG. 1 is a schematic view of a first embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a first embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a second embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a third embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of a third embodiment of the present invention;
FIG. 6 is a schematic diagram of a fourth embodiment of the present invention;
FIG. 7 is a schematic cross-sectional view of a fourth embodiment of the present invention;
fig. 8 is a schematic diagram of a solder paste according to a fourth embodiment of the present invention;
FIG. 9 is a graph of baking temperature for nano-sintered silver paste;
the semiconductor package comprises a 1-lead frame, a 2-heat dissipation substrate, a 3-first chip, a 4-second chip, a 5-plastic package, a 6-nano sintered silver paste layer, a 7-first aluminum strip, an 8-second aluminum strip, a 9-third aluminum strip, a 10-fourth aluminum strip, an 11 aluminum wire, a 12-first outer pin, a 13-second outer pin, a 14-third outer pin, a 15-functional area of the heat dissipation substrate, a 16-via hole, a 17-first copper Clip, a 18-second copper Clip and a 19-soldering paste.
Detailed Description
The present invention is described in further detail below with reference to the drawings to enable those skilled in the art to practice the invention by referring to the description.
The present invention provides a power discrete device employing a multi-chip stack structure, as shown in fig. 1 to 8, comprising:
A heat dissipation substrate 2;
at least two chips bonded to the heat dissipation substrate 2;
wherein, it is adhered to the said heat-dissipating base plate separately, or said at least two chips are adhered to the said heat-dissipating base plate in a mode of piling up;
wherein, the conductive silver paste layer is arranged between the at least two chips and the heat dissipation substrate or between the at least two chips;
the dispensing pattern of the conductive silver paste layer is star-shaped or cross-shaped.
Specifically, the heat dissipation substrate is adhered to the lead frame through the conductive silver paste layer or the conductive adhesive tape layer, at least two chips are connected with the electric connection part, and the electric connection part is connected with the outer pins on the lead frame.
The discrete device realizes the stacking and packaging of chips by repeatedly feeding the chips, and has the following specific structure: the lead frame 1 is adhered with a heat dissipation substrate 2, the heat dissipation substrate is adhered with a first chip 3, the first chip 3 is adhered with a second chip 4, or the first chip and the second chip are adhered on the heat dissipation substrate, then the circuit connection is realized through an electric connection component, and the plastic package 5 is used for protecting the circuit.
In the invention, the two chips can be two power chips, one power chip and one control chip, and the types of the chips can be any one or more of silicon, silicon carbide and gallium nitride.
The number of chips can be determined according to actual conditions, so that the actual working requirements are met.
Based on the above situation, the nano-sintered silver paste layer 6 is preferably used as the bonding material in the invention, because the nano-sintered silver paste has ultrahigh heat conductivity and has more excellent and reliable performances than other bonding materials, such as the control of the dispensing amount and thickness, the coverage rate of the adhesive, the adhesive climbing height, the adhesive climbing width and the like.
The nano sintered silver paste has an ultrahigh heat conductivity coefficient, the heat conductivity is 100W/mK-200W/mK, the traditional silver paste has the heat conductivity of only 1.3W/mK-3.7W/mK, the heat conductivity of the high heat conductivity silver paste can only reach 20W/mK-25W/mK, and the heat conductivity of the nano sintered silver paste is several times or even hundreds of times that of other sticky sheet materials; and the nano-sintered silver paste has stable performance, the online service life is longer than 12 hours, under the same conditions, the thrust test and the thermal resistance change are superior to those of common adhesive sheet glue or solder, and the reliability of the product can be greatly improved by adopting the nano-sintered silver paste as an adhesive material. Specifically, the thickness of the nano-sintered silver paste layer is 25-50 um.
Based on the above, specifically, the heat dissipation substrate 2 is an ALN ceramic copper-clad substrate, or Si 3 N 4 A ceramic copper-clad substrate. Can be of a common three-layer structure or can be optimized into a nine-layer structure, wherein the nine-layer structure is Au-Pd-Ni-Cu-ALN (Si) 3 N 4 ) -Cu-Ni-Pd-Au, wherein ALN or Si 3 N 4 The ceramic has the functions of insulating heat dissipation and improvingPressure resistance of the product; the upper and lower copper layers are of a conventional ceramic copper-clad substrate structure and are used for circuit wiring and heat dissipation; the purpose of electroless nickel-palladium immersion gold on the Cu layer is to make the surface of the heat dissipation substrate have excellent soldering reliability and wire bonding reliability at the same time, and also to prevent the Cu layer from oxidizing. Of course, the ceramic material can also be selected from Al 2 O 3 Any of ALN, beO, ZTA, si3N4, but ALN or Si 3 N 4 The effect of the ceramic is the best. Of course, the heat dissipation substrate may also be an insulating aluminum substrate or a ceramic substrate.
The packaging form of the discrete device can be semi-packaging or full-packaging, the pins can be single-column direct-insertion type or surface-mounted type, the packaging structure with the heat dissipation substrate and the multi-chip stack type packaging structure can be suitable for packaging forms of various power discrete devices, and the compatibility of a packaging platform is good.
On the basis of the above circumstances, the present invention provides a first embodiment, as shown in fig. 1 and 2, the at least two chips include a first chip 3 and a second chip 4, and the first chip 3 and the second chip 4 are respectively adhered to the heat dissipation substrate 2 through the nano-sintered silver paste layer 6.
As shown in fig. 1 and 2, the power discrete device includes: the lead frame 1, the multi-layer heat dissipation substrate 2, the first chip 3 and the second chip 4, the adhesive material nano-sintered silver paste layer 6, and aluminum strips with different specifications comprise a first aluminum strip 7, a second aluminum strip 8, a third aluminum strip 9, a fourth aluminum strip 10, aluminum wires 11 and a plastic package 5; the lead frame 1 includes 3 outer pins, namely a first outer pin 12, a second outer pin 13 and a third outer pin 14. In the embodiment, a bare copper lead frame or a point nickel plating lead frame is adopted, a multi-layer heat dissipation substrate 2 is adhered to the lead frame 1 by using a nano sintering silver paste layer 6, and after baking, a first chip 3 and a second chip 4 are respectively adhered to a functional area 15 of the heat dissipation substrate 2 by using the nano sintering silver paste layer 6, and baking is performed at the same time; the circuit connection parts of the first power chip and the second power chip, which are required to bear high current, adopt aluminum belts (a first aluminum belt to a fourth aluminum belt) as electric connection materials, and the Gate electrode circuit connection of the second power chip adopts a thin aluminum wire 11 as the electric connection materials. Finally, the plastic package material is adopted for packaging, and the plastic package shell 5 with the insulation protection function is formed. The heat dissipation substrate 2 in this embodiment is a nine-layer ceramic copper-clad substrate.
In the embodiment, one aluminum strip is used for replacing a plurality of aluminum wires, and an electric connection mode of combining the aluminum wires for carrying small current with the aluminum strips for carrying large current is adopted, so that the production cost is low, the production process is simple, and the production efficiency of products is improved; the aluminum strip has smaller internal resistance than the aluminum wires, and the aluminum strip used in heavy current has better electric conduction and heat conduction performance than a plurality of aluminum wires, so that the reliability of the press welding of the electric connection part of the product is improved.
On the basis of the above embodiment, the present invention provides a second embodiment, as shown in fig. 3, a via hole 16 is provided on the heat dissipation substrate, and a metal layer is electroplated in the via hole, or a copper pillar is added in the via hole.
The ceramic copper-clad substrate is provided with the through holes 16, so that the upper metal layer and the lower metal layer are conducted, the wireless circuit connection is realized, the chip on the heat-dissipating substrate and the circuit which needs to be electrically connected with the lead frame are possibly reduced in a wire bonding area due to glue overflow of the chip and the heat-dissipating substrate, the wire bonding force is reduced, the circuit failure problem is caused, the wireless connection can be realized through the arrangement of the through holes, the influence of glue overflow is avoided, and the reliability of a product is ensured.
The power discrete device includes: the lead frame 1, the multi-layer heat dissipation substrate 2, the two power chips and the adhesive sheet are made of nano-sintered silver paste layers 6 (not shown in the figure, refer to fig. 1 and 2), and aluminum belts with different specifications comprise a first aluminum belt 7, a second aluminum belt 8, a third aluminum belt 9, a fourth aluminum belt 10, fine aluminum wires 11 and a plastic package (not shown in the figure, refer to fig. 2); wherein the lead frame comprises 3 outer pins, namely a first outer pin 12, a second outer pin 13 and a third outer pin 14; the multi-layered heat-dissipating substrate 2 includes via holes 16. In the embodiment, a bare copper lead frame or a point nickel plating lead frame is adopted, a multi-layer heat dissipation substrate 2 is adhered to the lead frame by nano sintering silver paste, after baking, two power chips are respectively adhered to a functional area 15 of the heat dissipation substrate 2 by nano sintering silver paste, and baking is carried out simultaneously; the circuit connection part of the two power chips, which is required to bear large current, adopts an aluminum belt as an electric connection material, and the Gate electrode circuit connection of the power chips adopts a thin aluminum wire as the electric connection material. It is particularly proposed that the second aluminum strip 8 and the third aluminum strip 9 are welded on the heat-dissipating substrate 2, and the circuit is led out to the carrier of the lead frame 1 through the via hole 16 arranged on the heat-dissipating substrate and led out from the third outer pin 14, and the conductive function can be realized by electroplating a metal layer in the via hole 16, and also can be realized by adding a copper column. Finally, the plastic package material is adopted for packaging, and the plastic package shell 5 with the insulation protection function is formed. The heat dissipation substrate 2 in this embodiment is a nine-layer ceramic copper-clad substrate.
In the first embodiment, as shown in fig. 1, the first power chip and the second power chip are directly connected with the lead frame by the second aluminum tape 8 and the third aluminum tape 9, and when the heat dissipation substrate is adhered on the lead frame carrier, the adhesive overflows, so that the welding reliability of the aluminum tape is affected. In the process of core feeding, the glue climbing and glue overflowing control of nano-sintering silver paste of a chip and a radiating substrate are required to be very strict, and if the glue overflowing exceeds the range, the welding area of an aluminum strip is affected, so that poor welding of the aluminum strip is caused, and the circuit is invalid. According to the embodiment, through design optimization of the heat dissipation substrate, the through holes are formed in the edge of the heat dissipation substrate, so that the upper metal layer and the lower metal layer are conducted, wireless circuit connection is achieved, the influence of glue overflow is avoided, and the reliability of products is guaranteed.
The upper metal layer and the lower metal layer are conducted to realize wireless circuit connection, and the chip on the heat dissipation substrate and the lead frame need to be electrically connected to a circuit, so that the bonding area of the chip and the heat dissipation substrate can be reduced due to glue overflow, the bonding force of the bonding wire is reduced, the problem of circuit failure is caused, the wireless connection can be realized through the arrangement of the conducting holes, the influence of glue overflow is avoided, and the reliability of products is ensured.
Furthermore, as shown in fig. 4 and 5, the present invention provides a third embodiment, where the at least two chips include a first chip 3 and a second chip 4, the first chip is adhered to the heat dissipation substrate 2, the second chip 4 is adhered to the first chip 3, the first chip 3 is adhered to the heat dissipation substrate 2, and the second chip 4 and the first chip 3 are adhered to each other through the nano-sintered silver paste layer 6.
The power discrete device includes: the lead frame 1, the multi-layer heat dissipation substrate 2, the two power chips 3 and 4, the sticky material nano-sintering silver paste 6 and aluminum strips with different specifications, wherein the lead frame comprises a first aluminum strip 7, a third aluminum strip 9, thin aluminum wires 11 and a plastic package 5; wherein the lead frame comprises 3 outer pins, a first outer pin 12, a second outer pin 13 and a third outer pin 14; the multi-layered heat-dissipating substrate 2 includes via holes 16. In the embodiment, a bare copper lead frame or a point nickel plating lead frame is adopted, a heat dissipation substrate 2 is adhered to a lead frame 1, a first power chip is adhered to the heat dissipation substrate 2 after baking, baking is continued, and a second power chip is adhered to the first power chip and baking is continued. The circuit connection part of the two power chips, which is required to bear large current, adopts an aluminum belt as an electric connection material, and the circuit connection part of the two power chips, which is required to bear small current, adopts a thin aluminum wire as an electric connection material. It should be specifically mentioned that the circuits on the two power chips, which need to be led out through the third outer pin 14 of the lead frame, are led out to the lead frame carrier through the via hole 16 provided on the heat dissipation substrate and led out through the outer pin 14, wherein the first power chip realizes the circuit connection by welding 4 thin aluminum wires 11 to the PAD where the via hole 16 is located, and the second power chip realizes the circuit connection by welding an aluminum tape to the PAD where the via hole is located. The conductive function can be achieved by electroplating a metal layer in the via hole 16, or can be achieved by adding copper pillars. Finally, the plastic package material is adopted for packaging, and the plastic package shell 11 with the insulation protection function is formed.
As can be seen from fig. 5, the longitudinal structure of the present embodiment has a stack of 4 layers of materials, namely, a lead frame 1, a heat dissipation substrate 2, a first power chip 3, and a second power chip 4. The aim of miniaturizing the power device structure is achieved through stacking of the multi-layer structure, the technical process of the embodiment is simple, the heat dissipation performance of the device is good, the product performance is stable, and the market prospect is wide. The heat dissipation substrate 2 in this embodiment is a nine-layer ceramic copper-clad substrate.
On the basis of the above embodiment, the present invention provides a fourth embodiment, as shown in fig. 6 and 7, the power discrete device includes a lead frame 1, a multi-layer heat dissipation substrate 2, two power chips 3,4, a sticky material nano-sintered silver paste 6 (not shown in the figure, refer to fig. 4 and 5), a first copper Clip17, a second copper Clip18, a soldering paste 19 for soldering the copper clips, a fine aluminum wire 11, and a plastic package 5 with different specifications; the lead frame comprises 3 outer pins, namely a first outer pin 12, a second outer pin 13 and a third outer pin 14; the multi-layered heat-dissipating substrate 2 includes via holes 16. In the embodiment, a bare copper lead frame or a point nickel plating lead frame is adopted, a heat dissipation substrate 2 is adhered to a lead frame 1, a first power chip is adhered to the heat dissipation substrate 2 after baking, baking is continued, and a second power chip is adhered to the first power chip and baking is continued. Referring to fig. 8, solder paste 19 is uniformly dispensed on the areas where copper clips are required to be soldered on the surfaces of two power chips, solder paste 19 is uniformly dispensed on the corresponding soldering areas of the lead frame outer pins 13 and the heat dissipation substrate 2, then the copper clips are soldered to realize circuit connection, and the lead frame soldering pins of the copper clips do not need to be plated with nickel. The circuit connection part of the two power chips, which is required to bear large current, adopts copper clips as an electric connection material, and the circuit connection part of the two power chips, which is required to bear small current, adopts fine aluminum wires as the electric connection material. It should be specifically mentioned that the circuits on the two power chips, which need to be led out through the outer pins 14 of the lead frame, are led out to the lead frame carrier through the via holes 16 provided on the heat dissipation substrate and led out through the outer pins 14, wherein the first power chip realizes the circuit connection by welding 4 fine aluminum wires 11 to PADs where the via holes are located, and the second power chip realizes the circuit connection by welding copper clips to PADs where the via holes are located. The conductive function can be realized by electroplating a metal layer in the via hole 16, and also can be realized by adding a copper column, and finally, the plastic package material is adopted for packaging, so that the plastic package shell 5 with the insulation protection function is formed.
In the embodiment, the copper Clip replaces a plurality of aluminum wires, and an electric connection mode of combining the aluminum wires for carrying small current with the copper clips for carrying large current is adopted, so that the production cost is low, the production implementation is easier, the internal resistance of the copper Clip is small, the copper Clip has better electric conduction and heat conduction properties, and the copper Clip is a main electric connection mode of a power device in the future. In which fig. 7, the second power chip and copper Clip 18 are omitted for clarity.
In the above embodiments of the present invention, the nano-sintered silver paste layer uses a star-shaped or cross-shaped dispensing manner, so that the generation of voids can be avoided, and the bonding void ratio of the nano-sintered silver paste can reach 0%; meanwhile, the nano-sintered silver paste has an ultra-high heat conductivity coefficient which is several times or even hundreds of times that of other adhesive sheet materials, and the reliability of the product can be greatly improved by adopting the nano-sintered silver paste as an adhesive material.
In addition, the electrical connection component used in the invention can be a bonding wire, comprising Jin Tongxian and aluminum wires, and can also be an aluminum tape or copper Clip, and the embodiment of the invention adopts the aluminum tape or copper Clip as the electrical connection material for carrying the high current part. The aluminum tape or the copper Clip is used as the electric connecting material, so that the aluminum tape or the copper Clip has high current carrying density, and one wire-against-multiple wire connecting material can greatly improve the process efficiency. The aluminum tape or copper Clip has better heat conduction performance than the bonding wire, and can improve the press welding or welding reliability of the electric connecting component of the product. The copper Clip welding is used, the pin welding position of the frame is not plated with the spot, and the cost caused by the spot plating and poor spot plating is saved.
The power discrete device adopting the multi-chip stacking structure, namely the power discrete device with the heat dissipation substrate and packaged by adopting the multi-chip stacking structure, provided by the invention, realizes packaging by adopting the heat dissipation substrate and nano-sintering silver paste or high-heat-conductivity silver paste by adopting a chip stacking technology, can also ensure the heat dissipation requirement of the power device, and achieves the purpose of miniaturization of the packaging structure of the high-power device.
The invention also provides a preparation method of the power discrete device adopting the multi-chip stacking structure, which comprises the following steps:
step 101, bonding a heat dissipation substrate on a lead frame by adopting a star-shaped dispensing pattern of conductive silver paste, and baking;
102, bonding a first chip on the heat dissipation substrate by adopting star-shaped or cross-shaped dispensing patterns of conductive silver paste, baking, bonding a second chip on the first chip, baking, and sequentially bonding and baking if the number of the chips exceeds two; or the first chip and the second chip are respectively adhered to the heat dissipation plate and baked at the same time, and if the number of the chips exceeds two, the chips are respectively adhered and baked at the same time, so that the upper core baking is completed;
Wherein the baking temperature is 200-250 ℃, baking is performed by adopting a temperature curve, and baking is performed for 90 minutes at the highest temperature;
step 103, carrying out plasma cleaning on the lead frame subjected to the upper core baking, and waiting for pressure welding;
104, carrying out aluminum ribbon bonding connection on the parts of the chip, the heat-dissipating substrate and the lead frame, which need to bear large current, by using an aluminum ribbon bonding machine, and carrying out bonding connection on the parts, which bear small current, by using one of gold wires, copper wires and aluminum wires, so as to finish the pressure welding of the electric connection parts; or alternatively, the process may be performed,
the lead-free soldering paste is dotted on the corresponding positions of the chip, the lead frame and the heat dissipation substrate, then copper clips are placed on the soldering paste, and the copper clips are soldered through reflow soldering; after the copper Clip is welded, the chip, the heat dissipation substrate and the part of the lead frame which needs to bear small current are bonded and connected by gold wires, copper wires or aluminum wires, so that the press welding of the electric connection part is completed; after copper Clip welding, a weather cleaner is required to clean the welded frame to remove residues after welding of soldering paste.
In this application, the current greater than 100A is a large current, and the current less than 100A is a small current, and of course, the definition of the large and small currents is merely exemplary, and the large and small currents are determined according to specific designs.
Specifically, the conductive silver paste is nano-sintered silver paste.
The nano-sintered silver paste is preferably used as the bonding material, and the nano-sintered silver paste has more excellent properties of controlling the dispensing amount and thickness, covering rate of the adhesive, height of the adhesive, width of the adhesive and the like than other adhesive materials, and is shown in table 1. The star-shaped or cross-shaped pattern dispensing mode is used, the generation of cavities can be avoided, the bonding cavity rate of the nano-sintering silver paste can reach 0%, the comparison data are shown in table 2, meanwhile, the nano-sintering silver paste has an ultrahigh heat conductivity coefficient which is several times or even hundreds of times that of other adhesive sheet materials, and the reliability of a product can be greatly improved by adopting the nano-sintering silver paste as an adhesive material.
TABLE 1 comparison of Nano-sintered silver paste with other die bonding materials
Figure BDA0002576531770000131
The composition characteristics of the nano sintered silver paste determine that the viscosity of the nano sintered silver paste is higher than that of common silver paste, so that the control of the dispensing amount and thickness of the nano sintered silver paste is better than that of other silver pastes; the coverage rate of the adhesive is required to be 100%, the nano sintered silver paste can meet the requirement, and other silver pastes cannot meet the requirement if cavities exist; the paste climbing height and the paste climbing width are related to the characteristics of nano-sintered silver paste, and as can be seen from the table 1, the requirements of the nano-sintered silver paste and the high-heat-conductivity silver paste on the paste climbing height are different, the nano-sintered silver can be controlled to be 20% -80% of the chip height, and the high-heat-conductivity silver paste is qualified without exceeding the upper surface of the chip; the creeping width of the nano-sintering silver paste can be controlled within the range of 200-300 mu m, and the high heat conduction silver paste is controlled within the range of 200-400 mu m, which is not as accurate as the nano-sintering silver paste.
Table 2 comparison of nano sintered silver paste dispensing modes
Dispensing pattern Adhesive void ratio
Star-shaped 0％
Cross shape
0％
Punctiform
2％～5％
Z-shape 0.5％～1％
N-shaped 0.5％～1％
Step 104, the aluminum tape or copper Clip is used as an electric connection material to replace the traditional wire bonding technology, and has the advantages that the aluminum tape or copper Clip has high current carrying density and better heat conducting property, and one piece of wire connection material is abutted against a plurality of wires, so that the process efficiency can be greatly improved; the aluminum tape or copper Clip has better heat conduction performance than the bonding wire, and can improve the press welding or welding reliability of the electric connecting component of the product. Specifically, before step 101, the method further includes:
step 001, thinning and scribing the wafer for standby;
step 002, when the selected frame is a bare copper frame, plasma cleaning is required to be carried out on the bare copper frame before the core is put on; carrying out plasma cleaning on the lead frame by utilizing argon and argon-hydrogen mixed gas for standby;
when nano-sintered silver paste is used as a bonding sheet material, a silver-plated frame is generally used as a carrier to realize a reliable connection structure, and a bare copper frame cannot realize reliable connection. According to the invention, before the chip is bonded, the bare copper frame is subjected to plasma cleaning treatment, and copper protection agent or oxide on the surface of the frame is removed, so that the bare copper frame can be well combined with nano silver, the patch requirement is met, and the aim of saving cost is achieved.
Specifically, after step 102, the method further includes:
step 201, after the electric connection part is pressed and welded, uniformly spraying a layer of tackifier on a carrier of a lead frame and wire tube legs, and finishing glue spraying after drying; can prevent or improve layering of products and increase reliability of products.
Step 202, after glue spraying, carrying out plastic packaging on the lead frame, the chip, the heat dissipation substrate and the electric connection part which are electrically connected, so as to finish plastic packaging;
step 203, electroplating a layer of tin with the thickness of 10-25 micrometers on the part of the lead frame which is not subjected to plastic packaging after plastic packaging, and drying for later use;
step 204, cutting and separating the tin-plated lead frame into individual devices, and forming pins on pins to form power discrete devices;
and 205, packaging and warehousing after testing the functional parameters of the power discrete devices.
Embodiment one comprises the following specific steps:
1. wafer thinning
In this embodiment, the thickness of the gallium nitride wafer reaches about 1000 μm, and the surface of the wafer is uneven, in order to meet the thinning requirement, a UV film with high viscosity and high thickness is stuck on the surface of the gallium nitride wafer, the thickness of the UV film reaches 200 μm, the UV film completely wraps the wafer, the surface of the wafer is flat, water is prevented from entering, and the wafer is thinned to 350 μm by using a thinning machine by using a wet polishing process. Since gallium nitride chips are brittle and easily cracked, the thinning speed is one half to one third of that of a common wafer, and the pressure is doubled. The polishing quantity reaches more than 1.5 microns, so that the damage and stress caused by polishing the back of the wafer can be eliminated, and the cracking condition is improved. In the invention, the silicon chip and the silicon carbide chip do not need to be thinned.
2. Scribing
When the selected chip is a gallium nitride or silicon carbide chip, a UV film is stuck on the back of the wafer before scribing, a diamond cutter for a scribing cutter adopts single-cutter scribing, the extension of the cutter blade is 640-700 mu m, the thickness of the cutter blade is 25-30 mu m, the scribing channel width is more than or equal to 80 mu m, the scribing feed speed is more than or equal to 5mm/s, and the wafer is cleaned and dried in time after scribing. Dicing of the silicon chip is achieved by a generally conventional process.
3. Plasma cleaning
Before the upper core, the bare copper frame is subjected to plasma treatment by a plasma cleaning machine, the radio frequency power of the plasma is 200W-350W, the cleaning time is 5s-15s, and the gas used for plasma cleaning is the mixed gas of argon and nitrogen and hydrogen. When nano sintered silver paste is generally used as a bonding material, a silver plating frame is generally used as a carrier to realize a reliable connection structure.
4. Core loading and post-core loading baking
The stacking and packaging of the chips are realized by adopting the process of three times of core loading, and the specific process is as follows: the chip loading machine adopts a general chip loading machine, the adhesive sheet is nano sintered silver paste, the frame adopts a bare copper frame cleaned by plasma, a heat dissipation substrate is bonded on the lead frame, the lead frame is baked in a nitrogen charging oven after bonding, a first power chip is bonded on the heat dissipation substrate, a second power chip is bonded, the lead frame and the heat dissipation substrate are all bonded and then are baked in the nitrogen charging oven, and the chip mounting materials used for loading the chip for multiple times are the same, and the chip loading is performed for multiple times. The thickness of the nano sintered silver is controlled between 25um and 50um. The problems of glue thickness control, glue coverage rate, glue climbing height, bridging, void ratio and the like exist during core feeding, and the glue dispensing quality of the adhesive sheet glue is ensured by adopting an optimized glue dispensing tool and related process parameters. The dispensing mode of the large chip adopts a star shape, the small chip adopts a star shape or a cross pattern, and the bonding void ratio of the sintered silver paste can reach 0% by adopting a proper dispensing mode and optimized technological parameters.
The nano-sintered silver was baked in a nitrogen-filled oven using a low temperature-high temperature-low temperature baking curve, which was maintained at a high temperature of 250 ℃ for 90 minutes, and the baking curve was as shown in fig. 9.
5. Plasma cleaning
And (3) carrying out plasma cleaning on the lead frame after the upper core is baked, cleaning away some impurities generated in the baking process of the adhesive sheet material, ensuring the activity of the connecting points, wherein the gas used for the plasma cleaning is argon and nitrogen-hydrogen mixed gas, the radio frequency power of the plasma is 200-350W, and the cleaning time is 5-15 s.
6. Pressure welding
In order to ensure the reliability of welding spots, the lead frame which is subjected to core loading and plasma cleaning needs to be subjected to pressure welding within two hours, otherwise, the pressure welding effect is affected. Referring to fig. 1, the first power chip is connected to the circuit of the lead frame 1 by a second aluminum tape, and the circuit is led out from the third external pin 14; a fourth aluminum strip 10 for circuit connection between the first power chip and the heat dissipation substrate, i.e., the second power chip, and a first aluminum strip 7 for connection between the second outer lead 13; the second power chip is connected with the circuit of the lead frame 1 through a third aluminum strip 9, and the circuit is led out through a third outer pin 14; and a connection aluminum wire 11 connected to the first outer lead 12. The press welding sequence is as follows: the aluminum strips are pressed and welded by an aluminum wire welding machine, wherein the aluminum strip pressing and welding sequence is that the narrow aluminum strips are pressed and welded after the wide aluminum strips are pressed and welded, and finally the thin aluminum wires are pressed and welded.
7. Glue spraying
In order to prevent or improve product layering, a layer of tackifier is uniformly sprayed on a carrier of a lead frame and wire-bonding tube legs by a glue spraying machine before plastic packaging after pressure welding, and the glue is placed in a nitrogen cabinet for more than 2 hours after glue spraying is finished, so that a glue film is ensured to be dried, and plastic packaging is carried out within 24 hours.
8. Plastic packaging, curing and flash removing
Placing the lead frame which is well electrically connected on a plastic packaging machine, and packaging the chip, the heat dissipation substrate, part of the lead frame and the electrical connection material in a molten state by using plastic packaging materials, so as to provide physical and electrical protection and prevent external interference; placing the plastic package in an oven at 175+/-5 ℃ for baking for 6 hours+/-10 minutes; and removing the flash beyond the required range after baking.
9. Tin-plating and post tin-plating bake
And electroplating a layer of tin on the exposed radiating fins and pins of the lead frame after plastic packaging by using a high-speed tin wire and using a metal and chemical method, wherein the thickness of the plated layer is controlled to be 10-25 microns. And (5) putting the molten steel into a baking oven at 150+/-5 ℃ to bake for 90 minutes after the tin melting is finished.
10. Cutting/shaping
And cutting and separating the tin-plated lead frame into a single device by using a special rib cutting die, and forming pins on the pins.
11. Test printing
And testing functional parameters of the discrete devices after the ribs are cut by using a special testing machine, printing and sorting according to the requirements of customers, and finally packaging and warehousing.
In the embodiment, one aluminum strip is used for replacing a plurality of aluminum wires, and an electric connection mode of combining the aluminum wires for carrying small current with the aluminum strips for carrying large current is adopted, so that the production cost is low, the production process is simple, and the production efficiency of products is improved; the aluminum strip has smaller internal resistance than the aluminum wires, and the aluminum strip used in heavy current has better electric conduction and heat conduction performance than a plurality of aluminum wires, so that the reliability of the press welding of the electric connection part of the product is improved.
The specific preparation method of the second embodiment is the same as that of the first embodiment.
The specific steps involved in the packaging of the third embodiment refer to the first embodiment, but when the first chip is mounted, the first chip is bonded to the heat dissipation substrate, the second chip is bonded to the first chip after baking, and then baking is performed, and the rest of the process flows are the same as those of the first embodiment.
The fourth embodiment comprises the following specific steps:
1. wafer thinning
In this embodiment, the thickness of the gallium nitride wafer reaches about 1000 μm, and the surface of the wafer is uneven, in order to meet the thinning requirement, a UV film with high viscosity and high thickness is stuck on the surface of the gallium nitride wafer, the thickness of the UV film reaches 200 μm, the UV film completely wraps the wafer, the surface of the wafer is flat, water is prevented from entering, and the wafer is thinned to 350 μm by using a thinning machine by using a wet polishing process. Since gallium nitride chips are brittle and easily cracked, the thinning speed is one half to one third of that of a common wafer, and the pressure is doubled. The polishing quantity reaches more than 1.5 microns, so that the damage and stress caused by polishing the back of the wafer can be eliminated, and the cracking condition is improved. In the invention, the silicon chip and the silicon carbide chip do not need to be thinned.
2. Scribing
When the selected chip is a gallium nitride or silicon carbide chip, a UV film is stuck on the back of the wafer before scribing, a diamond cutter for a scribing cutter adopts single-cutter scribing, the extension of the cutter blade is 640-700 mu m, the thickness of the cutter blade is 25-30 mu m, the scribing channel width is more than or equal to 80 mu m, the scribing feed speed is more than or equal to 5mm/s, and the wafer is cleaned and dried in time after scribing. Dicing of the silicon chip is achieved by a generally conventional process.
3. Plasma cleaning
Before the upper core, the bare copper frame is subjected to plasma treatment by a plasma cleaning machine, the radio frequency power of the plasma is 200W-350W, the cleaning time is 5s-15s, and the gas used for plasma cleaning is the mixed gas of argon and nitrogen and hydrogen. When nano sintered silver paste is generally used as a bonding material, a silver plating frame is generally used as a carrier to realize a reliable connection structure.
4. Core loading and post-core loading baking
The stacking and packaging of the chips are realized by adopting the process of three times of core loading, and the specific process is as follows: the core feeding machine adopts a general core feeding machine, the adhesive sheet glue adopts nano sintering silver paste, the oven adopts a nitrogen charging oven, and the frame adopts a bare copper frame cleaned by plasma. Firstly bonding a heat dissipation substrate (a via hole is formed in the heat dissipation substrate), putting the heat dissipation substrate into an oven for baking after bonding, bonding a first power chip, bonding a second power chip after baking, and putting the heat dissipation substrate into the oven for baking. The thickness of the nano sintered silver is controlled between 25um and 50um. The problems of glue thickness control, glue coverage rate, glue climbing height, bridging, void ratio and the like exist during core feeding, and the glue dispensing quality of the adhesive sheet glue is ensured by adopting an optimized glue dispensing tool and related process parameters. The large chip adopts star-shaped dispensing patterns, the small chip adopts star-shaped or cross-shaped patterns, and the bonding void ratio of the sintered silver paste can reach 0% by adopting a proper dispensing mode and optimized technological parameters.
The nano-sintered silver was baked in a nitrogen-filled oven using a low temperature-high temperature-low temperature baking curve, which was maintained at a high temperature of 250 ℃ for 90 minutes, and the baking curve was as shown in fig. 9.
5. Plasma cleaning
And (3) carrying out plasma cleaning on the lead frame after the upper core is baked, cleaning away some impurities generated in the baking process of the adhesive sheet material, ensuring the activity of the connecting points, wherein the gas used for the plasma cleaning is argon and nitrogen-hydrogen mixed gas, the radio frequency power of the plasma is 200-350W, and the cleaning time is 5-15 s.
6. Copper Clip welding
When the copper Clip technology is used, the welding area on the surface of the chip needs to be treated by electroless nickel plating and gold immersion or electroless nickel plating and palladium immersion; passivation layers are used between the bonding pads to protect the die from mechanical damage and to prevent shorting of the bonding pads. Referring to fig. 8, the dispensing apparatus uniformly dispenses solder paste 19 on the areas where copper clips are to be soldered on the surfaces of the first and second chips, uniformly dispenses solder paste 19 on the second outer leads 13 of the lead frame and the corresponding soldering areas on the heat dissipating substrate 2, and then places copper clips 17 and 18 on the solder paste, reflows, and welds the copper clips.
7. Post-weld cleaning
And cleaning the frame welded by the copper Clip by using a weather cleaner, and cleaning residues after welding the soldering paste.
8. Pressure welding
After the clips are welded and cleaned, the remaining wires are bonded by an aluminum wire bonding machine, the first chip is connected with the heat dissipation substrate by bonding aluminum wires, the first chip is electrically connected with the lead frame through a via hole on the heat dissipation substrate and led out of the circuit through a third outer pin, and the Gate electrode of the second power chip is connected with the first pin by aluminum wires.
9. Glue spraying
In order to prevent or improve product layering, a layer of tackifier is uniformly sprayed on a carrier of a lead frame and wire-bonding tube legs by a glue spraying machine before plastic packaging after pressure welding, and the lead frame is placed in a nitrogen cabinet for more than 2 hours after glue spraying is finished, so that a glue film is ensured to be dried, and the lead frame is molded and packaged within 24 hours.
10. Plastic packaging, curing and flash removing
Placing the lead frame which is well electrically connected on a plastic packaging machine, and packaging the chip, the heat dissipation substrate, part of the lead frame and the electrical connection material in a molten state by using plastic packaging materials, so as to provide physical and electrical protection and prevent external interference; placing the plastic package into a baking oven at 175+/-5 ℃ for baking for 6 hours+/-10 minutes; and removing the flash beyond the required range after baking.
11. Tin-plating and post tin-plating bake
And electroplating a layer of tin on the exposed radiating fins and pins of the lead frame after plastic packaging by using a high-speed tin wire and using a metal and chemical method, wherein the thickness of the plated layer is controlled to be 10-25 microns. And (5) putting the molten steel into a baking oven at 150+/-5 ℃ to bake for 90 minutes after the tin melting is finished.
12. Cutting/shaping
And cutting and separating the tin-plated lead frame into a single device by using a special rib cutting die, and forming pins on the pins.
13. Test printing
And testing functional parameters of the discrete devices after the ribs are cut by using a special testing machine, printing and sorting according to the requirements of customers, and finally packaging and warehousing.
In the embodiment, the copper Clip replaces a plurality of aluminum wires, and an electric connection mode of combining the aluminum wires for carrying small current with the copper clips for carrying large current is adopted, so that the production cost is low, the production implementation is easier, the internal resistance of the copper Clip is small, the copper Clip has better electric conduction and heat conduction properties, and the copper Clip is a main electric connection mode of a power device in the future. The pin welding position for welding the copper Clip can be free from point nickel plating, so that the cost caused by point nickel plating and poor point nickel plating is saved.
It is apparent that those skilled in the art can obtain various effects not directly mentioned according to the various embodiments without trouble from various structures according to the embodiments of the present invention.
Although embodiments of the invention have been disclosed above, they are not limited to the use listed in the specification and embodiments. It can be applied to various fields suitable for the present invention. Additional modifications will readily occur to those skilled in the art. Therefore, the invention is not to be limited to the specific details and illustrations shown and described herein, without departing from the general concepts defined in the claims and their equivalents.

Claims (7)

1. A power discrete device employing a multi-chip stacked structure, comprising:
a heat-dissipating substrate;
at least two chips adhered to the heat dissipation substrate respectively, or adhered to the heat dissipation substrate in a stacked manner;
wherein, the conductive silver paste layer is arranged between the at least two chips and the heat dissipation substrate or between the at least two chips;
the dispensing pattern of the conductive silver paste layer is star-shaped or cross-shaped;
the conductive silver paste layer is a nano-sintered silver paste layer, and the thickness of the nano-sintered silver paste layer is 25-50 um;
the heat dissipation substrate is adhered to the lead frame through the conductive silver paste layer, the at least two chips are connected with the electric connection part, and the electric connection part is directly connected with the outer pins at the outer side of the lead frame;
the heat dissipation substrate is characterized by further comprising an additional electric connection component, a bonding pad is arranged on the outer sides of at least two chips on the heat dissipation substrate, the at least two chips are respectively connected with the bonding pad through the additional electric connection component, a plurality of through holes are formed in the bonding pad, a metal layer is electroplated in the through holes, or copper columns are added in the through holes, and the bonding pad is electrically connected with outer pins extending from the lead frame.
2. The power discrete device employing a multi-chip stacked configuration as claimed in claim 1, wherein the at least two chips comprise a first chip and a second chip, the first chip and the second chip being bonded to the heat-dissipating substrate through the nano-sintered silver paste layer, respectively; or the first chip is adhered to the heat dissipation substrate, the second chip is adhered to the first chip, the first chip is adhered to the heat dissipation substrate, and the second chip is adhered to the first chip through the nano-sintering silver paste layer.
3. The power discrete device employing a multi-chip stacked configuration as recited in claim 1, wherein,
the heat dissipation substrate is one of an insulating aluminum substrate, a ceramic substrate and a ceramic copper-clad substrate.
4. The power discrete device adopting the multi-chip stacked structure as claimed in claim 3, wherein the heat dissipation substrate is an ALN ceramic copper-clad substrate of a three-layer structure or Si of a three-layer structure 3 N 4 A ceramic copper-clad substrate, or an ALN ceramic copper-clad substrate with nine-layer structure or Si with nine-layer structure 3 N 4 A ceramic copper-clad substrate.
5. The preparation method of the power discrete device adopting the multi-chip stacking structure is characterized by comprising the following steps of:
The conductive silver paste is glued by adopting a star pattern, and a heat dissipation substrate is bonded on the lead frame for baking; the heat dissipation substrate is characterized in that a bonding pad is arranged on the outer sides of at least two chips on the heat dissipation substrate, a plurality of through holes are formed in the bonding pad, and a metal layer is electroplated in the through holes or copper columns are added in the through holes; the bonding pad is electrically connected with an outer pin extending from the lead frame;
the conductive silver paste adopts star-shaped or cross-shaped dispensing patterns, a first chip is bonded on the heat dissipation substrate, baking is carried out, a second chip is bonded on the first chip, baking is carried out, and if the number of the chips exceeds two, bonding and baking are carried out sequentially; or the first chip and the second chip are respectively adhered to the heat dissipation substrate and baked at the same time, and if the number of the chips exceeds two, the first chip and the second chip are respectively adhered and baked at the same time, so that the core loading baking is completed; wherein the baking temperature is 200-250 ℃, and a temperature curve is adopted for baking;
plasma cleaning is carried out on the lead frame after the upper core is baked, and the lead frame is subjected to pressure welding;
carrying out aluminum ribbon bonding connection on the parts, which need to bear large current, of the chip, the heat-radiating substrate and the outer pins on the outer sides of the lead frames by using an aluminum ribbon bonding machine, and carrying out bonding connection on the parts which bear small current by using one of gold wires, copper wires and aluminum wires to finish the pressure welding of the electric connection parts; or alternatively, the process may be performed,
The lead-free soldering paste is dotted on the corresponding positions of the outer pins on the outer sides of the chip and the lead frame and the heat dissipation substrate, then the copper Clip is placed on the soldering paste, and the soldering is performed to the copper Clip; after the copper Clip is welded, the chip, the heat dissipation substrate and the part of the outer pin on the outer side of the lead frame, which is required to bear small current, are bonded and connected by gold wires, copper wires or aluminum wires, so that the press welding of the electric connection part is completed;
wherein the chip includes the bonding pad bonded to the heat-dissipating substrate, an electrical path electrically connected to an outer lead extending from the leadframe through the bonding pad;
wherein the conductive silver paste is nano sintered silver paste.
6. The method for manufacturing a power discrete device using a multi-chip stacked structure as claimed in claim 5, wherein, before bonding the heat dissipation substrate on the lead frame and baking, the method further comprises:
wafer thinning and scribing are carried out on the chip for standby;
when the selected frame is a bare copper frame, plasma cleaning is required to be carried out on the bare copper frame before the core is put on; and (3) performing plasma cleaning on the lead frame by utilizing argon and argon-hydrogen mixed gas for standby.
7. The method of manufacturing a power discrete device of claim 5, further comprising:
After the electric connection part is pressed and welded, a layer of tackifier is uniformly sprayed on the carrier of the lead frame and the wire tube legs, and after the electric connection part is dried, the glue spraying is completed;
after glue spraying, the lead frame, the chip, the heat dissipation substrate and the electric connection part which are electrically connected are subjected to plastic packaging, so that the plastic packaging is completed;
after plastic packaging, electroplating a layer of tin with the thickness of 10-25 micrometers on the part of the lead frame which is not plastic-packaged, and drying for later use;
cutting and separating the tin-plated lead frame into individual devices, and forming pins to form a power discrete device;
and after testing the functional parameters of the power discrete devices, packaging and warehousing.
CN202010655248.7A 2020-07-09 2020-07-09 Power discrete device adopting multi-chip stacking structure and preparation method thereof Active CN111799251B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010655248.7A CN111799251B (en) 2020-07-09 2020-07-09 Power discrete device adopting multi-chip stacking structure and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010655248.7A CN111799251B (en) 2020-07-09 2020-07-09 Power discrete device adopting multi-chip stacking structure and preparation method thereof

Publications (2)

Publication Number Publication Date
CN111799251A CN111799251A (en) 2020-10-20
CN111799251B true CN111799251B (en) 2023-06-02

Family

ID=72811321

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010655248.7A Active CN111799251B (en) 2020-07-09 2020-07-09 Power discrete device adopting multi-chip stacking structure and preparation method thereof

Country Status (1)

Country Link
CN (1) CN111799251B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112599425A (en) * 2020-12-14 2021-04-02 苏州华太电子技术有限公司 Hybrid packaging method and hybrid packaging structure applied to electronic device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06334059A (en) * 1993-05-20 1994-12-02 Toppan Printing Co Ltd Semiconductor mounting board and production thereof
JPH07142632A (en) * 1993-11-17 1995-06-02 Toppan Printing Co Ltd Holding jig for semiconductor device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101592327B (en) * 2009-07-07 2012-07-25 天津大学 Power type LED lamp, encapsulation process and reflow soldering process equipment thereof
US9888568B2 (en) * 2012-02-08 2018-02-06 Crane Electronics, Inc. Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module
CN104392942A (en) * 2014-11-05 2015-03-04 天津大学 Method for encapsulating high-power IGBT device through performing non-pressure low-temperature sintering on nano silver soldering paste
CN204243026U (en) * 2014-11-06 2015-04-01 天水华天微电子股份有限公司 A kind of high heat conduction DAF film packaging part
CN107887368A (en) * 2017-10-13 2018-04-06 天津大学 Using the method for the two-sided interconnection silicon substrate IGBT module of low-temperature sintering Nano Silver
CN108091582B (en) * 2017-11-29 2019-11-08 上海无线电设备研究所 A kind of assembly method of high power density complex combination system microwave components
CN111081671A (en) * 2018-10-19 2020-04-28 珠海格力电器股份有限公司 Low-stress semiconductor chip fixing structure, semiconductor device and manufacturing method thereof
CN208923094U (en) * 2018-11-23 2019-05-31 华进半导体封装先导技术研发中心有限公司 A kind of multilayer power device stack encapsulating structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06334059A (en) * 1993-05-20 1994-12-02 Toppan Printing Co Ltd Semiconductor mounting board and production thereof
JPH07142632A (en) * 1993-11-17 1995-06-02 Toppan Printing Co Ltd Holding jig for semiconductor device

Also Published As

Publication number Publication date
CN111799251A (en) 2020-10-20

Similar Documents

Publication Publication Date Title
TWI502682B (en) Semiconductor package and method of mounting semiconductor die to opposite sides of tsv substrate
KR101204187B1 (en) Power Module using Sintering die attach And Manufacturing Method Thereof
WO2007058854A2 (en) Semiconductor package including a semiconductor die having redistributed pads
CN108550566B (en) SiC device three-dimensional stacking interconnection structure based on nano-silver solder paste and preparation method
JP2003124400A (en) Semiconductor power module and manufacturing method therefor
CN114743947B (en) TO-form-based power device packaging structure and packaging method
CN107393882A (en) Silicon carbide device encapsulating structure and manufacture method based on three layers of DBC substrates
WO2018084980A1 (en) Stacked electronics package and method of manufacturing thereof
CN111799251B (en) Power discrete device adopting multi-chip stacking structure and preparation method thereof
WO2018085020A1 (en) Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
CN113937009A (en) Packaging method of surface-mounted double-sided heat dissipation semiconductor power device
TWI775075B (en) Ceramic substrate assemblies and components with metal thermally conductive bump pads
CN212587507U (en) Power discrete device adopting multi-chip stacking structure
TWI706857B (en) Ceramic substrate assembly and element with metal thermal conductive bump pads and manufacturing method thereof
KR101074550B1 (en) Power module and manufacturing method thereof
CN108581168B (en) Solid welding process of heat dissipation chip
CN102244021B (en) Low-k chip encapsulating method
KR20110058061A (en) A die mounting substrate and a fabricating method the same
CN206639791U (en) Chip package device
JP4088394B2 (en) Insulated circuit board and semiconductor device using the same
CN220774344U (en) Car rule level power semiconductor module structure and encapsulation module
US20240145336A1 (en) Interface interconnect structure for efficient heat dissipation of power electronic device and preparation method therefor
CN115732450B (en) Novel high-density packaging structure of power module and manufacturing method thereof
CN115050656B (en) Gallium nitride power device integrated with flywheel diode and packaging method
CN219998213U (en) Power semiconductor module

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant