CN203423177U - Three-dimensional packaged SDRAM having 64M*48bit capacity - Google Patents

Abstract

The utility model relates to a three-dimensional packaged SDRAM (Synchronous Dynamic Random Access memory) having a 64M*48bit capacity. The three-dimensional packaged SDRAM includes six SDRAM chips having a capacity of 64M*8bit each. The three-dimensional packaged SDRAM is characterized by comprising a lead frame layer and six chip layers piled from bottom up as well. The lead frame layer is provided with pins used for external connection and the six SRAM chips are arranged on the six chip layers in a one-to-one corresponding manner. Electric connection pins are exposed on the periphery of the lead frame layer and the six chip layers being encapsulated and cut and outer surfaces of the lead frame layer and the six chip layers are provided with gold-plating connection lines. The gold-plating connection lines perform corresponding connection of the electric connection pins exposed on the lead frame layer and the six chip layers. The pins serve as physic connectors for external access signals and external output signals of the three-dimensional packaged SDRAM. By adopting the three-dimensional packaged SDRAM, occupancy of plane space of a printed circuit board can be reduced comparatively.

Description

A kind of capacity is the three-dimensional encapsulation SDRAM memory of 64M * 48bit

[technical field]

The utility model relates to memory device, and relating in particular to a kind of capacity is the three-dimensional encapsulation SDRAM memory of 64M * 48bit.

[background technology]

At present, on a lot of printed circuit board (PCB)s (PCB), all need to be equipped with SDRAM chip (SDRAM: dynamic random data storage), finite capacity due to each SDRAM storage chip, if be to use very large SDRAM memory space in a certain application, will expand the area of printed circuit board (PCB) so, then post a plurality of SDRAM chips in the above.

Due at some particular places, to some, use the shared plane space of equipment of printed circuit board (PCB) to have certain restriction, may just need to reduce the area of plane of printed circuit board (PCB); Like this, relative difficult ground expands the memory space on SDRAM printed circuit board (PCB) (PCB).

[utility model content]

The technical problems to be solved in the utility model is to provide the three-dimensional encapsulation SDRAM memory that a kind of capacity is 64M * 48bit, and it can reduce the plane space that takies printed circuit board (PCB) relatively.

For solving the problems of the technologies described above, the utility model provides following technical scheme:

A kind of capacity is the three-dimensional encapsulation SDRAM memory of 64M * 48bit, comprise the SDRAM chip that six capacity are 64M * 8bit, it is characterized in that, also comprise and carry out from bottom to up stacking a lead frame rack-layer and six chip layer, lead frame rack-layer is provided with the pin connecting for externally, and six SDRAM chips arrange respectively in six chip layer correspondingly; Described stacking a lead frame rack-layer and six chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out corresponding connection by the electrical connection pin exposing in a described lead frame rack-layer and six chip layer, and the pin of lead frame rack-layer is the physical connection thing with external output signal as external access signal.

The address wire of six SDRAM chips, write signal line, CLK clock, CKE clock enable signal, BA block selection signal, RAS row address latch, CAS column address latch corresponding compound respectively, the data/address bus juxtaposition of six SDRAM chips.

The technology that connects into capacity between the SDRAM chip that is 64M * 8bit by six capacity and be the SDRAM memory of 64Mx48bit belongs to the technology that the art personnel grasp conventionally, creation point of the present utility model is to utilize six storing chip layer to put SDRAM chip, then by stacking, embedding, after cutting, at outer surface, gold-plated connecting line is set putting six chip layer of chip and the pin wiring of a lead frame rack-layer connects into a three-dimensional encapsulation SDRAM memory, logical three-dimensional encapsulation mode avoids carrying out all SDRAM chips of juxtaposition in a chip layer, reduced the plane space that takies printed circuit board (PCB), thereby reduced the plane space of printed circuit board (PCB), especially be applicable to being applied to aviation, space industry.

[accompanying drawing explanation]

Fig. 1 is sectional view of the present utility model;

Fig. 2 is six SDRAM chip connection diagrams of the present utility model.

[embodiment]

As depicted in figs. 1 and 2, the three-dimensional encapsulation SDRAM memory that a kind of capacity that the present embodiment provides is 64M * 48bit, comprise and carry out from bottom to up a stacking lead frame rack-layer and six chip layer: one is provided with the pin chip layer 1 of the pin 11 for being externally connected, one is pasted with the chip layer 2 of SDRAM chip 21, one is pasted with the chip layer 3 of SDRAM chip 31, one chip layer 4, that is pasted with SDRAM chip 41 is pasted with the chip layer 5 of SDRAM chip 51; One chip layer 6, that is pasted with SDRAM chip 61 is pasted with the chip layer 7 of SDRAM chip 71; The SDRAM chip of SDRAM chip 21,31,41,51,61,71 TSOP-54 that all employing capacity is 64Mb * 8bit (54 pins) encapsulation; Stacking a lead frame rack-layer and six chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line by the electrical connection pin exposing in chip layer carry out corresponding connection take form a capacity as 64M * 48bit, pin package be the three-dimensional encapsulation SDRAM memory of QFP-114 (114 pins) encapsulation, the pin 11 of lead frame rack-layer 1 is as the external access signal of three-dimensional encapsulation SDRAM memory and the external physical connection thing of output signal.

Wherein, the address wire of six SDRAM chips, write signal line, CLK clock, CKE clock enable signal, BA block selection signal, RAS row address latch, CAS column address latch corresponding compound respectively, the data/address bus juxtaposition of six SDRAM chips.

Lead frame rack-layer and six chip layer can adopt printed circuit board (PCB).

The preparation process of above-mentioned three-dimensional encapsulation SDRAM memory is as follows:

(1) pin 11 is welded in lead frame rack-layer 1; SDRAM chip 21,31,41,51,61,71 is arranged on respectively in chip layer 2,3,4,5,6,7 correspondingly;

(2) lead frame rack-layer 1, lamella 2, chip layer 3, chip layer 4, chip layer 5, chip layer 6, chip layer 7 are carried out stacking from bottom to up;

(3) use epoxy resin to carry out embedding to a lead frame rack-layer and six chip layer, a lead frame rack-layer and six chip layer after embedding are cut, to allow a lead frame rack-layer and six chip layer expose electrical connection pin on periphery separately;

(4) a lead frame rack-layer and six chip layer are carried out to surface gold-plating to form Gold plated Layer, now, the electrical connection pin that Gold plated Layer is exposed on periphery separately with six chips is connected, and all interconnects and also connect pin simultaneously between the electrical connection pin exposing;

(5) for this separated signal node is separated, Gold plated Layer is carried out to surperficial line engraving to form gold-plated connecting line, gold-plated connecting line carries out corresponding connection by the electrical connection pin exposing in lead frame rack-layer and chip layer take and form a capacity as being the three-dimensional encapsulation SDRAM memory of QFP-114 (114 pins) encapsulation as 64M * 48bit, pin package, and the pin 11 of lead frame rack-layer 1 is as the external access signal of three-dimensional encapsulation SDRAM memory and the external physical connection thing of output signal.

The concrete purposes of 114 pins of this three-dimensional encapsulation SDRAM memory is as table 1.

The concrete purposes of table 1 pin

The utility model is not limited to above-described embodiment, based on simple replacement above-described embodiment, that do not make creative work, should belong to the scope that the utility model discloses.

Claims (2)

1. the three-dimensional encapsulation SDRAM memory that capacity is 64M * 48bit, comprise the SDRAM chip that six capacity are 64M * 8bit, it is characterized in that, also comprise and carry out from bottom to up stacking a lead frame rack-layer and six chip layer, lead frame rack-layer is provided with the pin connecting for externally, and six SDRAM chips arrange respectively in six chip layer correspondingly; Described stacking a lead frame rack-layer and six chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out corresponding connection by the electrical connection pin exposing in a described lead frame rack-layer and six chip layer, and the pin of lead frame rack-layer is the physical connection thing with external output signal as external access signal.

2. three-dimensional encapsulation SDRAM memory according to claim 1, it is characterized in that, the address wire of six SDRAM chips, write signal line, CLK clock, CKE clock enable signal, BA block selection signal, RAS row address latch, CAS column address latch corresponding compound respectively, the data/address bus juxtaposition of six SDRAM chips.

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