CN203644770U - Three-dimensional packaging NAND FLASH memory with capacity of 8Gx8bit - Google Patents
Three-dimensional packaging NAND FLASH memory with capacity of 8Gx8bit Download PDFInfo
- Publication number
- CN203644770U CN203644770U CN201320682924.5U CN201320682924U CN203644770U CN 203644770 U CN203644770 U CN 203644770U CN 201320682924 U CN201320682924 U CN 201320682924U CN 203644770 U CN203644770 U CN 203644770U
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- nand flash
- chip
- layer
- lead frame
- signal
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- 238000004806 packaging method and process Methods 0.000 title abstract 2
- 150000001875 compounds Chemical class 0.000 claims description 22
- 238000005538 encapsulation Methods 0.000 claims description 21
- 239000002994 raw material Substances 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 5
- 239000010931 gold Substances 0.000 abstract description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- 238000007747 plating Methods 0.000 abstract description 3
- 239000002131 composite material Substances 0.000 abstract 2
- 238000007789 sealing Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Abstract
The utility model relates to a three-dimensional packaging NAND FLASH memory with capacity of 8Gx8bit. The memory is characterized by comprising two 4Gx8bit NAND FLASH composite chips, and a lead frame layer and two chip layers which are stacked from bottom up. The lead frame layer is provided with pins used for external connection. The two NAND FLASH composite chips are respectively disposed on the two chip layers in a one-to-one manner. Electrical connection pins are exposed from the periphery of the stacked lead frame layer and the two chip layers after the lead frame layer and the two chip layers are processed by filling and sealing and cutting, and an outer surface is provided with gold plating connecting lines. The gold plating connecting lines correspondingly connect the electrical connection pins which are exposed from the lead frame layer and the two chip layers. The pins of the lead frame layer are used as physical connection objects for external access signals and external output signals. The NAND FLASH memory can relatively reduce plane space of a printed circuit board.
Description
[technical field]
The utility model relates to memory device, the three-dimensional encapsulation NAND FLASH memory that the capacity of relating in particular to is 8G × 8bit.
[background technology]
At present, on a lot of printed circuit board (PCB)s (PCB), all need to be equipped with NAND FLASH storage chip, due to the finite capacity of each NAND FLASH storage chip, if be to use very large NANDFLASH memory space in a certain application, will expand so the area of printed circuit board (PCB), then post multiple NANDFLASH storage chips in the above.
Due at some particular places, use the shared plane space of equipment of printed circuit board (PCB) to have certain restriction to some, may just need to reduce the area of plane of printed circuit board (PCB); Like this, relative difficult ground expands the memory space on NAND FLASH printed circuit board (PCB) (PCB).
[utility model content]
The technical problems to be solved in the utility model is to provide the three-dimensional encapsulation NANDFLASH memory that capacity is 8G × 8bit, and it can reduce the plane space that takies printed circuit board (PCB) relatively.
Above-mentioned technical problem is achieved through the following technical solutions:
Capacity is the three-dimensional encapsulation NAND FLASH memory of 8G × 8bit, it is characterized in that, comprises the NAND FLASH compound chip of two 4G × 8bit, carries out from bottom to up stacking a lead frame rack-layer and two chip layer; Lead frame rack-layer is provided with the pin connecting for externally, and two NAND FLASH compound chips are located at respectively in two chip layer correspondingly; Described stacking a lead frame rack-layer and two chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out correspondence by a described lead frame rack-layer with the electrical connection pin exposing in two chip layer and is connected, and the pin of lead frame rack-layer is the physical connection thing with external output signal as external access signal.
Correspondence is compound respectively for the data wire of two NAND FLASH compound chips, #RE reading signal lines, #WE write signal line, #WP write protect signal, ALE address latch signal, CLE order enable signal; The equal juxtaposition of chip selection signal of two NAND FLASH compound chips.
The NAND FLASH compound chip of each 4G × 8bit is made up of two NAND FLASH raw material chips, and it is that 2Gb, data-bus width are the encapsulation NAND FLASH chip of 8,48 pins that described NAND FLASH raw material chip all adopts memory capacity.
Between NAND FLASH compound chip by two 4G × 8bit, connect into capacity and be the technology that the technology of the NAND FLASH memory of 8G × 8bit can adopt the art personnel conventionally to grasp, primary creation point of the present utility model is to utilize two chip layer to put NAND FLASH chip, then by gold-plated connecting line being set to connect into a three-dimensional encapsulation NAND FLASH memory by putting two chip layer of chip and the pin wiring of a lead frame rack-layer at outer surface after stacking, embedding, cutting.Visible, the logical three-dimensional encapsulation mode of the utility model avoids carrying out all NAND FLASH of juxtaposition chip in a chip layer, reduce the plane space that takies printed circuit board (PCB), thereby reduced the plane space of printed circuit board (PCB), be especially applicable to being applied to Aeronautics and Astronautics field.Annexation between the NANDFLASH compound chip of two 4G × 8bit of the application's design that the utility model is further concrete.
[accompanying drawing explanation]
Fig. 1 is the sectional view of the present utility model of embodiment mono-;
Fig. 2 is the internal structure schematic diagram of the present utility model of embodiment mono-.
[embodiment]
Embodiment mono-
As depicted in figs. 1 and 2, a kind of three-dimensional encapsulation NAND FLASH memory that the present embodiment provides, comprise and carry out from bottom to up a stacking lead frame rack-layer and two chip layer: one is provided with the lead frame rack-layer 1 of the pin 11 for being externally connected, one the first chip layer 2, that is pasted with NAND FLASH compound chip 21 is pasted with the second chip layer 3 of NAND FLASH compound chip 31; Stacking a lead frame rack-layer and two chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out lead frame rack-layer and the electrical connection pin exposing in chip layer corresponding be connected to form a memory capacity and reach 64Gb, data-bus width to reach 8, pin package be TSOP-48(48 pin) the three-dimensional encapsulation NAND FLASH memory of encapsulation, the pin 11 of lead frame rack-layer 1 is as the external access signal of three-dimensional encapsulation NAND FLASH memory and the physical connection thing of external output signal.
As shown in Figure 2, the parameter of NAND FLASH compound chip 21,31 comprises that memory capacity is that 4Gb, data-bus width are 8, the NAND FLASH compound chip of each 4G × 8bit is made up of the NAND FLASH raw material chip of two 2Gb × 8bit, and it is that 2Gb, data-bus width are the encapsulation NAND FLASH chip of 8,48 pins that NAND FLASH raw material chip all adopts memory capacity.
Wherein, the data wire of two NAND FLASH compound chips, #RE reading signal lines, #WE write signal line, #WP write protect signal, ALE address latch signal, CLE order enable signal are corresponding compound respectively; The equal juxtaposition of chip selection signal of two NANDFLASH compound chips.
Lead frame rack-layer and two chip layer can adopt printed circuit board (PCB).
The preparation process of above-mentioned three-dimensional encapsulation NAND FLASH memory is as follows:
(1) pin 11 is welded in lead frame rack-layer 1; NAND FLASH compound chip 21,31 is arranged on respectively in chip layer 2,3 accordingly;
(2) lead frame rack-layer 1, the first chip layer 2, the second chip layer 3 are carried out stacking from bottom to up;
(3) use epoxy resin to carry out embedding to a lead frame rack-layer and two chip layer, a lead frame rack-layer and two chip layer after embedding are cut, to allow a lead frame rack-layer and two chip layer expose electrical connection pin on periphery separately;
(4) a lead frame rack-layer and two chip layer are carried out to surface gold-plating to form Gold plated Layer, now, the electrical connection pin that Gold plated Layer is exposed on periphery separately with two chip layer is connected, and all interconnects and also connect pin simultaneously between the electrical connection pin exposing;
(5) for the signal node this separation separates, Gold plated Layer is carried out to surperficial line engraving to form gold-plated connecting line, gold-plated connecting line carries out lead frame rack-layer and the electrical connection pin exposing in chip layer corresponding be connected to form a memory capacity and reach 64Gb, data-bus width to reach 8, pin package be TSOP-48(48 pin) the three-dimensional encapsulation NAND FLASH memory of encapsulation, the pin 11 of lead frame rack-layer 1 is as the external access signal of three-dimensional encapsulation NAND FLASH memory and the physical connection thing of external output signal.
The concrete purposes of each pin of this three-dimensional encapsulation NAND FLASH memory is as table 1.
The concrete purposes of table 1 pin
The utility model is not limited to above-described embodiment, based on simple replacement above-described embodiment, that do not make creative work, should belong to the scope that the utility model discloses.
Claims (3)
1. the three-dimensional encapsulation NAND FLASH memory that capacity is 8G × 8bit, is characterized in that, comprises the NAND FLASH compound chip of two 4G × 8bit, carries out from bottom to up stacking a lead frame rack-layer and two chip layer; Lead frame rack-layer is provided with the pin connecting for externally, and two NAND FLASH compound chips are located at respectively in two chip layer correspondingly; Described stacking a lead frame rack-layer and two chip layer are exposed electrical connection pin after embedding, cutting on periphery, and are provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out correspondence by a described lead frame rack-layer with the electrical connection pin exposing in two chip layer and is connected, and the pin of lead frame rack-layer is the physical connection thing with external output signal as external access signal.
2. the three-dimensional encapsulation NAND FLASH memory that capacity according to claim 1 is 8G × 8bit, it is characterized in that, correspondence is compound respectively for the data wire of two NAND FLASH compound chips, #RE reading signal lines, #WE write signal line, #WP write protect signal, ALE address latch signal, CLE order enable signal; The equal juxtaposition of chip selection signal of two NAND FLASH compound chips.
3. the three-dimensional encapsulation NAND FLASH memory that capacity according to claim 1 and 2 is 8G × 8bit, it is characterized in that, the NAND FLASH compound chip of each 4G × 8bit is made up of two NAND FLASH raw material chips, and it is that 2Gb, data-bus width are the encapsulation NAND FLASH chip of 8,48 pins that described NAND FLASH raw material chip all adopts memory capacity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320682924.5U CN203644770U (en) | 2013-10-30 | 2013-10-30 | Three-dimensional packaging NAND FLASH memory with capacity of 8Gx8bit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320682924.5U CN203644770U (en) | 2013-10-30 | 2013-10-30 | Three-dimensional packaging NAND FLASH memory with capacity of 8Gx8bit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203644770U true CN203644770U (en) | 2014-06-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320682924.5U Expired - Lifetime CN203644770U (en) | 2013-10-30 | 2013-10-30 | Three-dimensional packaging NAND FLASH memory with capacity of 8Gx8bit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203644770U (en) |
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2013
- 2013-10-30 CN CN201320682924.5U patent/CN203644770U/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140611 |