CN103869327A - Integrated satellite navigation chip and manufacture method thereof - Google Patents
Integrated satellite navigation chip and manufacture method thereof Download PDFInfo
- Publication number
- CN103869327A CN103869327A CN201210535687.XA CN201210535687A CN103869327A CN 103869327 A CN103869327 A CN 103869327A CN 201210535687 A CN201210535687 A CN 201210535687A CN 103869327 A CN103869327 A CN 103869327A
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- chip
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/33—Multimode operation in different systems which transmit time stamped messages, e.g. GPS/GLONASS
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/35—Constructional details or hardware or software details of the signal processing chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
The invention discloses an integrated satellite navigation chip and a manufacture method thereof. The integrated chip comprises one or multiple substrates, bare chips, components, bonding wires and a BGA solder ball array, wherein the substrates are used for supporting functional chips to realize electrical connection between the functional chips, the bare chips and components of the baseband, radiofrequency, Flash memory, EEPROM, ARM processor and other functional chips are laid on the substrates in a stacked or planar manner, the bonding wires are used for realizing electrical connection among the functional chips as well as between the functional chips and the substrates, and the BGA solder ball array is formed at the back sides of the substrates via backflow in a C4 technology. The bare chips and components of the multiple functional chips for realizing Beidou&GPS dual-mode satellite navigation are integrated in a packaging body via a series of substrate and micro-assembly technologies to form a small electronic product with high performance, high density and low loss, reception and processing of Beidou&GPS dual-mode satellite navigation are realized, and the problems that a present satellite navigation product module is large in size, high in wring difficulty, high in cost and the like are solved.
Description
Technical field
The present invention relates to satellite navigation field, particularly a kind of structure that multi-chip package technology realizes the high integrated Big Dipper & GPS bimodulus satellite navigation integrated chip of a high density and preparation method thereof of utilizing.
Background technology
Beidou satellite navigation system is the GPS (Global Position System) that has China's independent intellectual property right.Along with the progressively construction of Beidou satellite navigation system is perfect, satellite navigation, precision time service and location-based service industry taking the Big Dipper as core just plays an increasingly important role in national economy life, become vital new industry, development prospect is very wide.
High-performance satellite navigation terminal and chip are the cores of satellite navigation system, are also the bases of whole navigation Service industrial chain.The terminal applies exploitation of current domestic Beidou satellite navigation all has skewed popularity, have taking development radio frequency chip as core, have taking baseband processing chip as research core, autonomous radio frequency and baseband processing chip integrative solution seldom can be provided, thereby cause radio frequency chip to be connected not in place with baseband processing chip core algorithm, also greatly reduced the performance of Development of Module.Realize Beidou satellite navigation function owing to adopting at present packaged radio frequency, base band separate chip to carry out secondary development, there is the problems such as size is large, power consumption is high, cost of development is high in module more simultaneously,, be unfavorable for applying.In addition, the confidentiality of its technical scheme is also poor, has restricted to a certain extent the high speed development of Beidou satellite navigation industry.
And the variety of problems that the proposition of this patent brings based on classic method just, by the multiple bare chip of realizing Big Dipper & GPS bimodulus satellite navigation function, be integrated in a packaging body by a series of substrate process and micro-packaging technology, form a high density, low-loss, small-sized integrated navigation chip cheaply, and realize reception and the processing capacity of the Big Dipper and GPS bimodulus satellite-signal simultaneously.
Summary of the invention
(1) technical matters that will solve
In view of this, fundamental purpose of the present invention is to provide a kind of Big Dipper & GPS bimodulus satellite navigation integrated chip encapsulating structure and method, this structure is based on plane MCP technology, by the die package of the multiple different chips in system in a substrate, and complete internal logic connect and fan-out interface.
(2) technical scheme
For achieving the above object, the technical solution used in the present invention is as follows:
A structure for integrated satellite navigation chip product, is characterized in that, comprising: one or more layers is for realizing logic between multi-chip and connect and the substrate of supporting role; Be placed on substrate for realizing the components and parts such as the various chips nude film of Big Dipper & GPS bimodulus satellite navigation function and resistance, electric capacity, inductance; Realize the bonding wire that each chip is connected with substrate electricity; Be covered in the plastic packaging glue on multiple different chip and lead-in wire; And be formed at the BGA welded ball array of substrate back.
Say further, described for realizing, logic between multi-chip connects and the substrate of supporting role, is double-deck compound printed wiring board, and its surface and inside are provided with following microstructure: (1) metal pad; (2) micro wiring; (3) through-hole structure etc., substrate size shape and above-mentioned microstructure need be carried out specialized designs manufacture according to the electricity annexation of several functions chip/components and parts.
Furthermore, described be placed on substrate for realizing the multiple different nude films of Big Dipper & GPS bimodulus satellite navigation function, refer to the bare chip of un-encapsulated from wafer factory completes flow, scribing process, its upper surface has the metal pad for electrical connection, bare chip upper surface is upwards positioned over top layer upper surface of base plate, with substrate connected mode be Bonding.
Furthermore, described be placed on substrate for realizing the various chips nude film of Big Dipper & GPS bimodulus satellite navigation function, comprising: baseband chip, radio frequency chip and storage chip, and carry out interconnectedly according to certain logical relation, realize satellite navigation signals receiving function.And described storage chip comprises Flash storage chip and eeprom chip, for storage program and satellite data.
Furthermore, describedly realize the bonding wire that each chip is connected with substrate electricity, according to certain electricity logic, one end is connected in the pad on bare chip, and the other end is connected in and on substrate, is distributed in chip pad array around.And bonding wire can be the alloy material of the metals such as gold, copper, silver, nickel or above-mentioned metal, and the plane length of bonding line is 0.5um～5um.
Say further again, described in be covered in chip and lead-in wire on plastic packaging glue, its height and area be as the criterion with the exposed pads that is coated all chips and lead-in wire and substrate surface, described plastic packaging glue is made up of organic polymer materials.
The present invention also provides a kind of manufacture method of integrated satellite navigation chip, and it comprises the following steps:
Design and produce that logic between multi-chip connects and the multilayer printed board of supporting role for realizing;
Several functions chip nude film and components and parts Surface Mount reserved assigned address on substrate of the satellite navigation of Big Dipper & GPS bimodulus will be realized by chip mounter;
By the substrate hot setting after pasting chip, make to form firmly and connect between chip and substrate;
By wire bonder, will on the pad of each chip, draw the corresponding corresponding lead pad position that is drawn out on substrate of signal wire;
Adopt the modes such as some glue or coating on substrate/components and parts surface forms one deck plastic packaging glue heating cure;
Refluxed and formed BGA welded ball array by C4 technique in the back side at substrate;
To whole module section, and do corresponding Performance Detection.
(3) beneficial effect
The present invention has following advantage compared with common satellite navigation module:
First, the present invention has broken away from conventional satellite navigation module and has adopted many separate chip to assemble the large shortcoming of size while exploitation, and bare chip is integrated, and area and the volume of whole module all reduce greatly.
The second, this method shortens the cable run distance of each chip chamber in module, is more conducive to improve the speed of signal processing, reduces power consumption, improves the performance of module.
The 3rd, the method cost of whole process using is low, be easy to control, and under large-scale production, classic method can reduce costs relatively.
The 4th, this programme adopt integrated chip realize before the Big Dipper & GPS bimodulus satellite navigation function assembled by multiple chips, when reducing the difficulty of user's secondary development, also improved the confidentiality of product.
Brief description of the drawings
Fig. 1 a to Fig. 1 e is the flow process cross sectional representation of the concrete encapsulating structure of implementing integrated satellite navigation chip according to the present invention, wherein:
The substrate of 101-taking compound as matrix, for carrying the multiple different nude films of realizing Big Dipper & GPS bimodulus satellite navigation function;
102-upper surface pad structure, is generally made up of metals such as copper, nickel, gold, for the connection of surperficial nude film and components and parts;
103-lower surface pad structure, is generally made up of metals such as copper, nickel, gold, is used to form back side welded ball array;
104-the first functional chip, can be any one in the functional chip of realizing the satellite navigation of Big Dipper & GPS bimodulus;
105-the second functional chip, can be in the functional chip of realizing the satellite navigation of Big Dipper & GPS bimodulus except the first functional chip other any one;
106-metal lead wire, is generally metallic gold or copper, is distributed in the upper surface pad of chip surrounding for connecting drawing on chip on pad and substrate;
107-plastic packaging glue, is generally organic polymer material;
108-back side welded ball array BGA.
Fig. 2 is the final surperficial chip distribution schematic top view that completes the encapsulating structure of Big Dipper & GPS bimodulus satellite navigation integrated chip according to the present invention, wherein:
201-realizes the multiple different nude films of Big Dipper & GPS bimodulus satellite navigation function and realizes the substrate connecting each other for carrying.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
Fig. 1 a to Fig. 1 e is the concrete implementing procedure cross sectional representation that completes integrated satellite navigation chip according to the present invention.
Step 1, design and produce as shown in Figure 1a for realizing, logic between multi-chip connects and the two-layer tellite 101 of supporting role, manufacture craft adopts conventional substrate process, two-layer for realizing the redistribution layer of navigation integrated chip function electrical connection except having on this substrate, the pad structure 102 that is positioned in addition the bonding wire pad for surperficial nude film of upper surface, is generally made up of metals such as copper, nickel, gold;
Step 2, as shown in Figure 1 b, other any one functional chip 105 except the first functional chip in the various chips of any one functional chip 104 in the various chips of being integrally formed chip and being integrally formed chip is mounted on to the formulation position of substrate, attaching method adopts surface stick-mounting machine, comprise respectively preheating, gluing, to steps such as, placement, hot settings, other chip and components and parts also mount in this way and are fixed on assigned address on substrate 101;
Step 3, as shown in Fig. 1 c, completes lead-in wire 106 bonding step by wire bonder, will on each chip bonding pad, draw that signal wire is corresponding is drawn out to corresponding lead pad position on substrate, and this lead-in wire 106 is generally metal gold thread or copper cash;
Step 4, as shown in Figure 1 d, adopts the modes such as some glue or coating to form one deck plastic packaging glue 107 heating cure at upper surface of base plate.The composition of its plastic packaging glue is generally organic polymer, and height is as the criterion to cover all bare chips and lead-in wire;
Step 5, as shown in Fig. 1 e, is refluxed and is formed BGA welded ball array 108 by C4 technique at the back side of substrate;
Step 8, to whole module section, and does corresponding Performance Detection.
Fig. 2 is the final surperficial chip distribution schematic top view that completes the encapsulating structure of integrated satellite navigation chip according to the present invention, and 201 is carrying nude film and the substrate of realizing its interconnecting relation.
Fig. 2-1 and Fig. 2-2 have provided respectively two kinds of different implementations of integrated satellite navigation chip.In Fig. 2-1, provided the scheme that adopts a binary channels radio frequency chip, baseband chip, Flash storage chip, EEPROM, five kinds of bare chips of arm processor to realize Big Dipper & GPS bimodulus satellite navigation function, it adopts a binary channels radio frequency chip to realize the binary channels parallel receive of Big Dipper & gps satellite signal; Fig. 2-2 adopt baseband chip, Flash storage chip, EEPROM, arm processor and two these six nude films of single channel radio frequency chip to realize another program of Big Dipper & GPS bimodulus satellite navigation function, and it adopts two single channel radio frequency chips to realize the binary channels parallel receive function of Big Dipper & gps satellite signal.Two kinds of different modes can realize reception and the processing capacity of the Big Dipper and GPS bimodulus satellite-signal.
The distributing position of nude film can, according to magnitude function, the size etc. of the concrete placement-and-routing of substrate and nude film because usually regulating, not be subject to the restriction of schematic diagram position.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (8)
1. a structure for integrated satellite navigation chip product, is characterized in that, comprising:
One or more layers is for realizing logic between multi-chip and connect and the substrate of supporting role;
Be placed on substrate for realizing various chips nude film and the components and parts of Big Dipper & GPS bimodulus satellite navigation function;
Realize the bonding wire that each chip is connected with substrate electricity;
Be covered in the plastic packaging glue on multiple different chip and lead-in wire;
And be formed at the BGA welded ball array of substrate back.
2. integrated chip product according to claim 1, it is characterized in that, described for realizing, logic between multi-chip connects and the substrate of supporting role, is double-deck compound printed wiring board, and its surface and inside are provided with following microstructure: (1) metal pad; (2) micro wiring; (3) through-hole structure etc., substrate size shape and above-mentioned microstructure need be carried out specialized designs manufacture according to the electricity annexation of several functions chip/components and parts.
3. integrated chip product according to claim 1, it is characterized in that, described be placed on substrate for realizing the multiple different nude films of Big Dipper & GPS bimodulus satellite navigation function, refer to the bare chip of un-encapsulated from wafer factory completes flow, scribing process, its upper surface has the metal pad for electrical connection, bare chip upper surface is upwards positioned over top layer upper surface of base plate, with substrate interconnection technique be Bonding.
4. integrated chip product according to claim 1, it is characterized in that, described be placed on substrate for realizing the various chips nude film of Beidou satellite navigation function, comprise: baseband chip, radio frequency chip, storage chip and arm processor chip, and carry out interconnectedly according to certain logical relation, realize satellite navigation function.
5. storage chip according to claim 4, is characterized in that, comprises FLASH storage chip and eeprom chip, for storage program and satellite data.
6. integrated chip product according to claim 1, it is characterized in that, describedly realize the bonding wire that each chip is connected with the electricity of substrate, according to certain electricity logic, one end is connected in the pad on bare chip, and the other end is connected in and on substrate, is distributed in chip pad array around.Plane length 0.5um～the 5um of bonding wire.
7. integrated chip product according to claim 1, it is characterized in that, the described plastic packaging glue being covered on chip and lead-in wire, its height and area are as the criterion with the exposed pads that is coated all chips and lead-in wire and substrate surface, and described plastic packaging glue is made up of organic polymer materials.
8. a manufacture method for integrated satellite navigation chip, is characterized in that, comprising:
Design and produce that logic between multi-chip connects and the two-layer tellite of supporting role for realizing;
By chip mounter, several functions chip and components and parts Surface Mount are reserved to assigned address on substrate;
By the substrate hot setting after pasting chip, make to form firmly and connect between chip and substrate;
By wire bonder, will on the pad of each chip, draw the corresponding corresponding lead pad position that is drawn out on substrate of signal wire;
Adopt the modes such as some glue or coating to form one deck plastic packaging glue heating cure at upper surface of base plate;
Refluxed and formed BGA welded ball array by C4 technique in the back side at substrate;
To whole module section, and do corresponding Performance Detection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210535687.XA CN103869327A (en) | 2012-12-13 | 2012-12-13 | Integrated satellite navigation chip and manufacture method thereof |
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| CN201210535687.XA CN103869327A (en) | 2012-12-13 | 2012-12-13 | Integrated satellite navigation chip and manufacture method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105374804A (en) * | 2015-12-08 | 2016-03-02 | 深圳佰维存储科技有限公司 | Intelligent wearable device |
| CN105391823A (en) * | 2015-11-25 | 2016-03-09 | 上海新储集成电路有限公司 | Method for reducing size and power consumption of mobile device |
| CN109037974A (en) * | 2018-06-26 | 2018-12-18 | 中国电子科技集团公司第二十九研究所 | A kind of contact wide band radio-frequency interconnecting method and structure |
| CN109211224A (en) * | 2018-11-07 | 2019-01-15 | 中国电子科技集团公司第五十八研究所 | A kind of high integration navigation signal processing SIP device |
-
2012
- 2012-12-13 CN CN201210535687.XA patent/CN103869327A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105391823A (en) * | 2015-11-25 | 2016-03-09 | 上海新储集成电路有限公司 | Method for reducing size and power consumption of mobile device |
| CN105391823B (en) * | 2015-11-25 | 2019-02-12 | 上海新储集成电路有限公司 | A method of reducing mobile device size and power consumption |
| CN105374804A (en) * | 2015-12-08 | 2016-03-02 | 深圳佰维存储科技有限公司 | Intelligent wearable device |
| CN109037974A (en) * | 2018-06-26 | 2018-12-18 | 中国电子科技集团公司第二十九研究所 | A kind of contact wide band radio-frequency interconnecting method and structure |
| CN109211224A (en) * | 2018-11-07 | 2019-01-15 | 中国电子科技集团公司第五十八研究所 | A kind of high integration navigation signal processing SIP device |
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Application publication date: 20140618 |