CN203103288U - Stereoscopically encapsulated NAND-FLASH memory - Google Patents
Stereoscopically encapsulated NAND-FLASH memory Download PDFInfo
- Publication number
- CN203103288U CN203103288U CN2012205153194U CN201220515319U CN203103288U CN 203103288 U CN203103288 U CN 203103288U CN 2012205153194 U CN2012205153194 U CN 2012205153194U CN 201220515319 U CN201220515319 U CN 201220515319U CN 203103288 U CN203103288 U CN 203103288U
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- printed circuit
- nand
- circuit board
- pcb
- flash
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Semiconductor Memories (AREA)
Abstract
The utility model relates to a stereoscopically encapsulated NAND-FLASH memory. The memory comprises a plurality of NAND-FLASH chips, and a plurality of printed circuit boards stacked from bottom to top, the plurality of printed circuit boards includes a pin printed circuit board and at least two placement printed circuit boards located at an upper side of the pin printed circuit board, the pin printed circuit board is provided with pins for external connection, and the plurality of NAND-FLASH chips are arranged on the placement printed circuit boards, but are not all on the same placement printed circuit board; printed circuit lines are exposed on peripheries after the plurality of printed circuit boards are encapsulated and cut, and the outer surfaces of the plurality of printed circuit boards are provided with gold-plated connecting lines; the gold-plated connecting lines connect the printed circuit lines exposed on the plurality of printed circuit boards in an associated manner to form the stereoscopically encapsulated NAND-FLASH memory in which the plurality of NAND-FLASH chips are connected in parallel, and the pins act as physical connecting media of external input signals and external output signals of the stereoscopically encapsulated NAND-FLASH memory. The stereoscopically encapsulated NAND-FLASH memory can relatively reduce occupied planar space of the printed circuit boards.
Description
[technical field]
The utility model relates to memory device, relates in particular to a kind of three-dimensional encapsulation NAND-FLASH memory.
[background technology]
At present, all need to be equipped with the NAND-FLASH storage chip on a lot of printed circuit board (PCB)s (PCB), because the finite capacity of each NAND-FLASH storage chip, if in a certain application is to use very big NAND-FLASH memory space, will expand the area of printed circuit board (PCB) so, post a plurality of NAND-FLASH storage chips then in the above.
Owing at some particular places, use the shared plane space of equipment of printed circuit board (PCB) that certain restriction is arranged, may just need to reduce the area of plane of printed circuit board (PCB) to some; Like this, relative difficult ground expands the NAND-FLASH memory space on the printed circuit board (PCB) (PCB).
[utility model content]
The technical problems to be solved in the utility model provides a kind of three-dimensional encapsulation NAND-FLASH memory, and it can reduce the plane space that takies printed circuit board (PCB) relatively.
Above-mentioned technical problem is achieved through the following technical solutions:
A kind of three-dimensional encapsulation NAND-FLASH memory, comprise a plurality of NAND-FLASH chips, it is characterized in that, also comprise a plurality of printed circuit board (PCB)s that pile up from bottom to up, described a plurality of printed circuit board (PCB) comprises a pin printed circuit board (PCB) and is positioned at least two storing printed circuit board (PCB)s of described pin printed circuit board (PCB) top, the pin printed circuit board (PCB) is provided with and is used for the pin that externally connects, and a plurality of NAND-FLASH chips are located at and are put on the printed circuit board (PCB) but be not located at entirely on the same storing printed circuit board (PCB); The described a plurality of printed circuit board (PCB)s that pile up expose printed circuit lines on periphery after embedding, cutting, and be provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out the association connection to form with the printed circuit lines of exposing on described a plurality of printed circuit board (PCB)s: a plurality of NAND-FLASH chips become to be connected in parallel, and the pin of pin printed circuit board (PCB) is as the external access signal of solid encapsulation NAND-FLASH memory and the physical connection thing of external output signal.
A plurality of NAND-FLASH chips become to be connected in parallel, and are meant that the memory capacity of the solid encapsulation SRAM memory that can make final formation is the accumulative total of the memory capacity of a plurality of NAND-FLASH chips.
The quantity of described storing printed circuit board (PCB) is less than or equals the quantity of described NAND-FLASH chip, and each is put on the printed circuit board (PCB) and is provided with a NAND-FLASH chip at least.
The quantity of described NAND-FLASH chip is identical with the quantity of putting printed circuit board (PCB).
It is that 32Gb, data-bus width are the Plastic Package NAND-FLASH chip of 8,48 pins that described NAND-FLASH chip all adopts memory capacity.
The order latch signal line of described a plurality of NAND-FLASH chips, address latch signal line, write-protect input signal cable, read the enable signal line, to write the enable signal line respectively compound, the busy signal output signal line of described a plurality of NAND-FLASH chips and chip selection signal line are respectively and put.
As seen from the above technical solution, the utility model utilizes polylith to put printed circuit board (PCB) and puts the NAND-FLASH chip, then by piling up, at outer surface gold-plated connecting line being set after the embedding, cutting and connecting into the three-dimensional NAND-FLASH of an encapsulation memory will put printed circuit board (PCB) and pin printed circuit.As seen, the logical three-dimensional packaged type of the utility model avoids carrying out and putting all NAND-FLASH chips on a printed circuit board (PCB), reduce the plane space that takies printed circuit board (PCB), thereby reduced the plane space of printed circuit board (PCB), especially be fit to be applied to the Aeronautics and Astronautics field.
[description of drawings]
Fig. 1 is the sectional view of the present utility model of embodiment one;
Fig. 2 is five NAND-FLASH chip connection diagrams of the present utility model of embodiment one;
Fig. 3 is the sectional view of the present utility model of embodiment two;
Fig. 4 is five NAND-FLASH chip connection diagrams of the present utility model of embodiment two.
[embodiment]
Embodiment one
As depicted in figs. 1 and 2, a kind of three-dimensional encapsulation NAND-FLASH memory that present embodiment provides, comprise six printed circuit board (PCB)s that pile up from bottom to up: one is provided with the pin printed circuit board (PCB) 1 that is used for the external pin 11 that connects, one is pasted with first of NAND-FLASH chip 21 puts printed circuit board (PCB) 2, one is pasted with second of NAND-FLASH chip 31 puts printed circuit board (PCB) 3, one is pasted with the 3rd of NAND-FLASH chip 41 puts printed circuit board (PCB) 4, one is pasted with the 4th of NAND-FLASH chip 51 puts printed circuit board (PCB) 5, and one is pasted with the 5th of NAND-FLASH chip 61 and puts printed circuit board (PCB) 6; It is that 32Gb (bit), data-bus width are the Plastic Package NAND-FLASH chip of 8 TSOP-48 (48 pins) that NAND- FLASH chip 21,31,41,51,61 all adopts memory capacity; Six printed circuit board (PCB)s that pile up expose printed circuit lines on periphery after embedding, cutting, and be provided with gold-plated connecting line 7 at outer surface; Gold-plated connecting line 7 carries out the printed circuit lines of exposing on the printed circuit board (PCB) related the connection to form a memory capacity to reach 160Gb, data-bus width to reach 40, pin package be the solid encapsulation NAND FLASH memory of TSOP-72 (72 pins) encapsulation: five NAND-FLASH chips become to be connected in parallel, and the pin 11 of pin printed circuit board (PCB) 1 is as the external access signal of three-dimensional encapsulation NAND FLASH memories and the external physical connection thing of output signal.
Wherein, five NAND-FLASH chips become to be connected in parallel, and specifically comprise: the order latch signal line of five NAND-FLASH chips, address latch signal line, write-protect input signal cable, read the enable signal line, to write the enable signal line compound respectively; The data wire of each NAND-FLASH chip (also being address wire simultaneously) all is divided into two 8 holding wires and is combined into 8 position datawires, and 8 position datawires of these five NAND-FLASH chips are also put to form 40 bit data bus of three-dimensional encapsulation NAND-FLASH memory; The busy signal output signal line of two NAND-FLASH chips and chip selection signal line are respectively and put.
The preparation process of above-mentioned three-dimensional encapsulation NAND-FLASH memory is as follows:
(1) pin 11 is welded on the pin printed circuit board (PCB) 1; NAND- FLASH chip 21,31,41,51,61 is arranged on respectively on the storing printed circuit board (PCB) 2,3,4,5,6 accordingly;
(2) pin printed circuit board (PCB) 1, first printed circuit board (PCB) 2, second printed circuit board (PCB) 3, the 3rd printed circuit board (PCB) 4, the 4th printed circuit board (PCB) 5, the 5th printed circuit board (PCB) 6 are piled up from bottom to up;
(3) use 8 pairs of six printed circuit board (PCB)s of epoxy resin to carry out embedding, six printed circuit board (PCB)s after the embedding are cut to allow six printed circuit board (PCB)s expose printed circuit lines on periphery separately;
(4) six printed circuit board (PCB)s are carried out surface gold-plating to form Gold plated Layer, at this moment, Gold plated Layer is connected with the printed circuit lines that five printed circuit board (PCB)s expose on periphery separately, all interconnects between the printed circuit lines of exposing and the while also connects pin;
(5) separate for signal node this separation, Gold plated Layer is carried out surperficial line engraving to form gold-plated connecting line 7, gold-plated connecting line 7 carries out the association connection with the printed circuit lines of exposing on the printed circuit board (PCB) and reaches 160Gb to form a memory capacity, data-bus width reaches 40, pin package is the solid encapsulation NAND-FLASH memory of TSOP-72 (72 pins) encapsulation: five NAND-FLASH chips one-tenth are connected in parallel, and the pin 11 of pin printed circuit board (PCB) 1 is as the external access signal of three-dimensional encapsulation NAND-FLASH memories and the physical connection thing of external output signal.
Wherein, five NAND-FLASH chips become to be connected in parallel, and specifically comprise: the order latch signal line of five NAND-FLASH chips, address latch signal line, write-protect input signal cable, read the enable signal line, to write the enable signal line compound respectively; The data wire of each NAND-FLASH chip (also being address wire simultaneously) all is divided into two 8 holding wires and is combined into 8 position datawires, and 8 position datawires of these five NAND-FLASH chips are also put to form 40 bit data bus of three-dimensional encapsulation NAND-FLASH memory; The busy signal output signal line of two NAND-FLASH chips and chip selection signal line are respectively and put.
The concrete purposes such as the table 1 of each pin of this solid encapsulation NAND-FLASH memory.
The concrete purposes of table 1 pin
Embodiment two
As shown in Figure 4, a kind of three-dimensional encapsulation NAND-FLASH memory that present embodiment provides, comprise three printed circuit board (PCB)s that pile up from bottom to up: one is provided with the pin printed circuit board (PCB) 100 that is used for the external pin 10 that connects, one is pasted with first of NAND-FLASH chip 20 puts printed circuit board (PCB) 200, and one is pasted with the second storing printed circuit board (PCB) 300 of adorning NAND-FLASH chip 30; It is that 32Gb, data-bus width are the Plastic Package NAND-FLASH chip of 16 TSOP-48 (48 pins) that NAND- FLASH chip 20,30 all adopts memory capacity; Three printed circuit board (PCB)s that pile up expose printed circuit lines on periphery after epoxy resin 80 embeddings, cutting, and be provided with gold-plated connecting line 70 at outer surface; Gold-plated connecting line 70 carries out the printed circuit lines of exposing on the printed circuit board (PCB) related to connect that to reach 64Gb, data-bus width be that 8, pin package are the solid encapsulation NAND-FLASH memory of TSOP-48 (48 pins) encapsulation to form a memory capacity: two NAND-FLASH chips become to be connected in parallel, and the pin 10 of pin printed circuit board (PCB) 100 is as the external access signal of three-dimensional encapsulation NAND-FLASH memories and the external physical connection thing of output signal.
Wherein, two NAND-FLASH chips become to be connected in parallel, and specifically comprise: the order latch signal line of two NAND-FLASH chips, address latch signal line, write-protect input signal cable, read the enable signal line, to write the enable signal line compound respectively; The data wire of NAND-FLASH chip 20 and NAND-FLASH chip 30 (also being address wire simultaneously) all is divided into two 8 holding wires, and these four 8 holding wires carry out compound to form 8 bit data bus of three-dimensional encapsulation NAND-FLASH memory; The busy signal output signal line of two NAND-FLASH chips and chip selection signal line are also put.
The preparation process of above-mentioned three-dimensional encapsulation NAND-FLASH memory is with reference to embodiment one.
The concrete purposes such as the table 2 of each pin of this solid encapsulation NAND-FLASH memory.
The concrete purposes of table 2 pin
The utility model is not limited to the foregoing description, based on simple replacement the foregoing description, that do not make creative work, should belong to the scope that the utility model discloses.
Claims (5)
1. a solid encapsulates the NAND-FLASH memory, comprise a plurality of NAND-FLASH chips, it is characterized in that, also comprise a plurality of printed circuit board (PCB)s that pile up from bottom to up, described a plurality of printed circuit board (PCB) comprises a pin printed circuit board (PCB) and is positioned at least two storing printed circuit board (PCB)s of described pin printed circuit board (PCB) top, the pin printed circuit board (PCB) is provided with and is used for the pin that externally connects, and a plurality of NAND-FLASH chips are located at and are put on the printed circuit board (PCB) but be not located at entirely on the same storing printed circuit board (PCB); The described a plurality of printed circuit board (PCB)s that pile up expose printed circuit lines on periphery after embedding, cutting, and be provided with gold-plated connecting line at outer surface; Gold-plated connecting line carries out association with the printed circuit lines of exposing on described a plurality of printed circuit board (PCB)s and connects to form: a plurality of NAND-FLASH chips are connected in parallel, and the pin of pin printed circuit board (PCB) is as the external access signal of solid encapsulation NAND-FLASH memory and the physical connection thing of external output signal.
2. three-dimensional encapsulation NAND-FLASH memory according to claim 1, it is characterized in that, the quantity of described storing printed circuit board (PCB) is less than or equals the quantity of described NAND-FLASH chip, and each is put on the printed circuit board (PCB) and is provided with a NAND-FLASH chip at least.
3. three-dimensional encapsulation NAND-FLASH memory according to claim 2 is characterized in that the quantity of described NAND-FLASH chip is identical with the quantity of putting printed circuit board (PCB).
4. three-dimensional encapsulation NAND-FLASH memory according to claim 3 is characterized in that it is that 32Gb, data-bus width are the Plastic Package NAND-FLASH chip of 8,48 pins that described NAND-FLASH chip all adopts memory capacity.
5. according to any described three-dimensional encapsulation NAND-FLASH memory of claim 1 to 4; it is characterized in that; the order latch signal line of described a plurality of NAND-FLASH chips, address latch signal line, write-protect input signal cable, read the enable signal line, to write the enable signal line respectively compound, the busy signal output signal line of described a plurality of NAND-FLASH chips and chip selection signal line are respectively and put.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012205153194U CN203103288U (en) | 2012-09-29 | 2012-09-29 | Stereoscopically encapsulated NAND-FLASH memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012205153194U CN203103288U (en) | 2012-09-29 | 2012-09-29 | Stereoscopically encapsulated NAND-FLASH memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203103288U true CN203103288U (en) | 2013-07-31 |
Family
ID=48854672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012205153194U Expired - Lifetime CN203103288U (en) | 2012-09-29 | 2012-09-29 | Stereoscopically encapsulated NAND-FLASH memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203103288U (en) |
-
2012
- 2012-09-29 CN CN2012205153194U patent/CN203103288U/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130731 |
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| CX01 | Expiry of patent term |