CN209312764U - The non-hermetically sealed three-dimension packaging eeprom memory that a kind of capacity is 1M × 8bit - Google Patents
The non-hermetically sealed three-dimension packaging eeprom memory that a kind of capacity is 1M × 8bit Download PDFInfo
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- CN209312764U CN209312764U CN201920180110.9U CN201920180110U CN209312764U CN 209312764 U CN209312764 U CN 209312764U CN 201920180110 U CN201920180110 U CN 201920180110U CN 209312764 U CN209312764 U CN 209312764U
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- eeprom
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Abstract
The utility model discloses the non-hermetically sealed three-dimension packaging eeprom memories that a kind of capacity is 1M × 8bit, the eeprom chip being stacked together including 8, undermost eeprom chip lower end is equipped with backing plate, backing plate lower end is fixed with lead frame, lead frame is equipped with outer lead, each eeprom chip is equipped with the copper foil pin for drawing eeprom chip pin, using eight chips as three-dimensional structure stack layer in structure, layer is stacked using chip layer as interlayer interconnection copper foil, form stacked body, utilize the design of three-dimensional structure, the chip select line of eight eeprom chips is individually drawn by lead-out wire；The address wire connection of eight eeprom chips, writing for eight eeprom chips is enabled, read enabled, idle/busy be separately connected after draw, with single layer of chips occupied area close in the case where realize the extensions of 8 times of capacity, the plane space that storage component part occupies pcb board is substantially reduced, conducive to the miniaturization of system.It is particularly suitable for application to the Aeronautics and Astronautics field of High Density Integration, miniature requirement.
Description
Technical field
The utility model relates to store equipment, and in particular to the non-hermetically sealed three-dimension packaging that a kind of capacity is 1M × 8bit
Eeprom memory.
Background technique
Many electronic products are required using band Electrically Erasable Programmable Read-Only Memory (EEPROM) device, and electronics produces
It is increasing that product handle data volume, it is desirable that memory space is increasing, and the capacity of various EEPROM is limited, Yao Shixian large capacity gesture
Necessity places multi-disc EEPROM device on pcb board, these devices can occupy sizable area, causes the increasing of pcb board area
Greatly.
More and more requirement degree of the electronic product to miniaturization are higher and higher, and the area of pcb board cannot not only expand,
Also require smaller, the area that memory device can occupy on plank is almost impossible to be expanded again, system board need capacity it is bigger,
The smaller memory of volume.Therefore it is badly in need of new small in size, the big EEPROM device structure of capacity.
Utility model content
The purpose of this utility model is to provide a kind of non-hermetically sealed three-dimension packaging EEPROM that capacity is 1M × 8bit storages
Device, with overcome the deficiencies in the prior art, the utility model can satisfy system board to the SRAM memory of large capacity, small size
Demand.
In order to achieve the above objectives, the utility model adopts the following technical solution:
A kind of capacity is the non-hermetically sealed three-dimension packaging eeprom memory of 1M × 8bit, including 8 are stacked together
Eeprom chip, single eeprom chip capacity be 128k × 8bit, undermost eeprom chip lower end be equipped with backing plate, pad
Plate lower end is fixed with lead frame, and lead frame is equipped with outer lead, and each eeprom chip, which is equipped with, draws eeprom chip
The copper foil pin of pin, eeprom chip and lead frame outer layer pass through casting glue sealing, the copper foil on each eeprom chip
Pin and outer lead extend to casting glue outer surface, and casting glue outer layer is equipped with the external metallization plating of connection copper foil pin and outer lead
Change layer lead.
Further, wrapping layer is equipped on the outside of external metallization platingization layer lead.
Further, copper foil pin is encapsulated on eeprom chip by welded ball array, is connect with eeprom chip pin.
Further, outer lead uses Chisel lead-O6 outer lead.
Further, casting glue uses epoxide-resin glue.
Further, eight eeprom chips from top to bottom are followed successively by the first eeprom chip U1, the 2nd EEPROM core
Piece U2, third eeprom chip U3, the 4th eeprom chip U4, the 5th eeprom chip U5, the 6th eeprom chip U6, the 7th
Eeprom chip U7 and the 8th eeprom chip U8；The data line connection of eight eeprom chips；The piece of eight eeprom chips
Route selection is individually drawn by lead-out wire；The address wire connection of eight eeprom chips, writing for eight eeprom chips be enabled,
It is drawn after reading enabled, idle/busy be separately connected.
Compared with prior art, the utility model has technical effect beneficial below:
A kind of capacity of the utility model be 1M × 8bit non-hermetically sealed three-dimension packaging eeprom memory, including 8 mutually
The eeprom chip being stacked, single eeprom chip capacity are 128k × 8bit, undermost eeprom chip lower end
Equipped with backing plate, backing plate lower end is fixed with lead frame, ensure that the stacking quality of eeprom chip, convenient for fixed encapsulation, lead
Frame is equipped with outer lead, and each eeprom chip is equipped with the copper foil pin for drawing eeprom chip pin, eeprom chip
Pass through casting glue sealing with lead frame outer layer, the copper foil pin and outer lead on each eeprom chip extend to outside casting glue
Surface, casting glue outer layer are equipped with the external metallization platingization layer lead of connection copper foil pin and outer lead, utilize eight cores in structure
Piece stacks layer as three-dimensional structure stack layer, using chip layer as interlayer interconnection copper foil, and chip and copper foil are handed in short transverse
For stacking, stacked body is formed, using the design of three-dimensional structure, the chip select line of eight eeprom chips, which individually passes through, to be drawn
Outlet is drawn；The address wire of eight eeprom chips connects, and the enabled, reading of writing of eight eeprom chips enables, is idle/to hurry and distinguish
Drawn after connection, realize with single layer of chips occupied area close in the case where realize the extensions of 8 times of capacity, substantially reduce
Storage component part occupies the plane space of pcb board, conducive to the miniaturization of system.It has been particularly suitable for application to High Density Integration, small
The Aeronautics and Astronautics field of type demand.
Detailed description of the invention
FIG. 1 is a schematic structural view of the utility model.
Fig. 2 is the utility model schematic diagram of circuit connection structure.
Wherein, 1, eeprom chip；2, lead frame；3, copper foil pin；4, casting glue；5, outer lead；6, external metallization
Platingization layer lead；7, backing plate.
Specific embodiment
The utility model is described in further detail with reference to the accompanying drawing:
As shown in Figure 1, a kind of capacity be 1M × 8bit non-hermetically sealed three-dimension packaging eeprom memory, including 8 mutually
The eeprom chip 1 being stacked, single eeprom chip capacity is 128k × 8bit, under undermost eeprom chip 1
End is equipped with backing plate 7, and 7 lower end of backing plate is fixed with lead frame 2, and lead frame 2 is equipped with outer lead 5, on each eeprom chip
Equipped with the copper foil pin 3 for drawing eeprom chip pin, eeprom chip 1 and 2 outer layer of lead frame pass through 4 sealing of casting glue,
Copper foil pin and outer lead 5 on each eeprom chip extend to 4 outer surface of casting glue, and 4 outer layer of casting glue is equipped with connection copper
The external metallization platingization layer lead 6 of foil pin and outer lead 5；
It is equipped with wrapping layer on the outside of external metallization platingization layer lead 6, is used for exterior insulation；
Eeprom chip uses capacity 1M, the eeprom chip for the TSOP-32 encapsulation that data-bus width is 8；Outer lead
Using Chisel lead-O6 outer lead；Casting glue uses epoxide-resin glue；
Outer lead 5 on lead frame 2 is the final pin of module, and outer lead 5 is fixed by the slot on lead frame 2,
Copper foil pin 3 is encapsulated on eeprom chip by welded ball array, is connect with eeprom chip pin, by lead frame, backing plate 7
It is stacked gradually from the bottom to top with 8 eeprom chips, the module after the completion of stacking is fixed by the filling of casting glue 4, is cut later
At the module of designed size, copper foil pin 3 is leaked out, then external metallization platingization layer is set on the outside of casting glue 4, finally by sharp
Photo-etching processes complete surface etch metal-plated layer and form external metallization platingization layer lead 6, realize the assembling of module circuitry；Knot
Structure sectional view is as shown in Figure 1；
As shown in Fig. 2, eight eeprom chips from top to bottom are followed successively by the first eeprom chip U1, the 2nd EEPROM core
Piece U2, third eeprom chip U3, the 4th eeprom chip U4, the 5th eeprom chip U5, the 6th eeprom chip U6, the 7th
Eeprom chip U7 and the 8th eeprom chip U8；
The data line connection of eight eeprom chips, draws for I/00-I/O7 position datawire；Realize 8 data bit widths
Expand；The chip select line of eight eeprom chips is individually drawn by lead-out wire, realizes different chips and number by chip select line
It is controlled according to the selection of position；The address wire connection of eight eeprom chips, draws for A0-A17 bit address line；
Writing for eight eeprom chips is enabled, read enabled, idle/busy be separately connected after draw；
First eeprom chip U1 chip select line #CE0, the second eeprom chip U2 chip select line #CE1 third eeprom chip U3
Chip select line #CE2, the 4th eeprom chip U4 chip select line #CE3, the 5th eeprom chip U5 chip select line #CE4, the 6th EEPROM core
Piece U6 chip select line #CE5, the 7th eeprom chip U7 chip select line #CE6, the 8th eeprom chip U8 chip select line #CE7 are single respectively
Solely draw；
Ultimately form capacity be 8Mb, data-bus width up to 8, be encapsulated as the non-hermetically sealed three-dimensional envelope of TSOP-40 encapsulation
Dress.
It is described further with reference to the accompanying drawing to the structural principle of the utility model and using step:
Such as the particular use of each pin of 1 memory of table:
The definition of 1 pin function of table
Using eight chips as three-dimensional structure stack layer in the utility model structure, copper is interconnected using chip layer as interlayer
Foil stacks layer, and chip and copper foil are alternately stacked in short transverse, forms stacked body, and stacked body passes through encapsulating, cutting, outer surface
Gold-plated, 3 D stereo groove technique connects into the pin wiring of eight layers of chip, eight interlayers interconnection copper foil, a leadframe layers
One SRAM memory, the design of three-dimensional structure, realize with single layer of chips occupied area close in the case where realize
The extensions of 8 times of capacity substantially reduces the plane space that storage component part occupies pcb board, conducive to the miniaturization of system.It is especially suitable
Close the Aeronautics and Astronautics field for being applied to have High Density Integration, miniature requirement.
Claims (6)
1. the non-hermetically sealed three-dimension packaging eeprom memory that a kind of capacity is 1M × 8bit, which is characterized in that including 8 mutual heaps
The eeprom chip (1) stacked, single eeprom chip capacity are 128k × 8bit, undermost eeprom chip (1)
Lower end is equipped with backing plate (7), and backing plate (7) lower end is fixed with lead frame (2), and lead frame (2) is equipped with outer lead (5), each
Eeprom chip is equipped with the copper foil pin (3) for drawing eeprom chip pin, and eeprom chip (1) and lead frame (2) are outside
Layer passes through casting glue (4) sealing, and the copper foil pin and outer lead (5) on each eeprom chip extend to casting glue (4) appearance
Face, casting glue (4) outer layer are equipped with the external metallization platingization layer lead (6) of connection copper foil pin and outer lead (5).
2. a kind of capacity according to claim 1 is the non-hermetically sealed three-dimension packaging eeprom memory of 1M × 8bit, special
Sign is, wrapping layer is equipped on the outside of external metallization platingization layer lead (6).
3. a kind of capacity according to claim 1 is the non-hermetically sealed three-dimension packaging eeprom memory of 1M × 8bit, special
Sign is that copper foil pin (3) is encapsulated on eeprom chip by welded ball array, connect with eeprom chip pin.
4. a kind of capacity according to claim 1 is the non-hermetically sealed three-dimension packaging eeprom memory of 1M × 8bit, special
Sign is that outer lead uses Chisel lead-O6 outer lead.
5. a kind of capacity according to claim 1 is the non-hermetically sealed three-dimension packaging eeprom memory of 1M × 8bit, special
Sign is that casting glue uses epoxide-resin glue.
6. a kind of capacity according to claim 1 is the non-hermetically sealed three-dimension packaging eeprom memory of 1M × 8bit, special
Sign is that eight eeprom chips from top to bottom are followed successively by the first eeprom chip U1, the second eeprom chip U2, third
Eeprom chip U3, the 4th eeprom chip U4, the 5th eeprom chip U5, the 6th eeprom chip U6, the 7th EEPROM core
Piece U7 and the 8th eeprom chip U8；The data line connection of eight eeprom chips；The chip select line difference of eight eeprom chips
It is drawn separately through lead-out wire；The address wire connection of eight eeprom chips, writing for eight eeprom chips is enabled, it is enabled to read,
It is idle/busy be separately connected after draw.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920180110.9U CN209312764U (en) | 2019-01-31 | 2019-01-31 | The non-hermetically sealed three-dimension packaging eeprom memory that a kind of capacity is 1M × 8bit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920180110.9U CN209312764U (en) | 2019-01-31 | 2019-01-31 | The non-hermetically sealed three-dimension packaging eeprom memory that a kind of capacity is 1M × 8bit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112782552A (en) * | 2019-11-05 | 2021-05-11 | 深圳第三代半导体研究院 | Compression joint type power module detection system and detection method |
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2019
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112782552A (en) * | 2019-11-05 | 2021-05-11 | 深圳第三代半导体研究院 | Compression joint type power module detection system and detection method |
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