CN213071125U

CN213071125U - Stacked structure of eMMC chip provided with flip main control chip

Info

Publication number: CN213071125U
Application number: CN202022172051.6U
Authority: CN
Inventors: 李凯
Original assignee: Huatian Technology Nanjing Co Ltd
Current assignee: Huatian Technology Nanjing Co Ltd
Priority date: 2020-09-28
Filing date: 2020-09-28
Publication date: 2021-04-27
Anticipated expiration: 2030-09-28

Abstract

The utility model discloses a be provided with stacked structure of eMMC P chip of flip-chip main control chip, this structure is provided with the DRAM chip on the base plate, is provided with 3D NAND chip on the DRAM chip, and DRAM chip and 3D NAND chip are perpendicular setting, through the setting of this structure for dummy wafer in the middle of can saving between two chips, in order to increase the chip and pile up the number of piles, and then increase capacity.

Description

Stacked structure of eMMC chip provided with flip main control chip

[ technical field ] A method for producing a semiconductor device

The utility model belongs to the technical field of integrated chip, concretely relates to be provided with stacked structure of eMMC P chip of flip-chip main control chip.

[ background of the invention ]

The eMMC (Embedded Multi-Chip Package) is an Embedded Multi-layer packaging Chip, is a higher-order memory device compared with the eMMC, and is used for packaging the eMMC and the DRAM into a whole, so that the size is reduced, the circuit link design is reduced, and the Embedded Multi-Chip Package is mainly applied to smart phones with more than one thousand yuan.

When the eMMC is applied to the storage structure, the volume of the eMMC occupies a larger area in the chip stacking process, so that the final packaging structure is larger.

[ Utility model ] content

An object of the utility model is to overcome above-mentioned prior art's shortcoming, provide a stacked structure of eMMC chip that is provided with flip-chip main control chip to pile up to the eMMC chip among the solution prior art and occupy the great technical problem of volume.

In order to achieve the above purpose, the utility model adopts the following technical scheme to realize:

a stacked structure of eMCP chips provided with flip main control chips comprises a substrate, wherein DRAM chips are arranged on the substrate, a first layer of 3D NAND chips are arranged on the DRAM chips, the flip main control chips are arranged beside the DRAM chips and are arranged below the first layer of 3D NAND chips; the flip-chip main control chip is electrically connected with the substrate through a second conductive wire.

The utility model discloses a further improvement lies in:

preferably, the length direction of the first layer 3D NAND chip and the length direction of the DRAM chip are perpendicular to each other.

Preferably, the distance between the highest point of the second conductive line and the substrate is less than or equal to the height of the DRAM chip.

Preferably, the first layer of 3D NAND chips is electrically connected to the substrate through a first conductive line.

Preferably, the first conductive wire and the second conductive wire are gold wires.

Preferably, several layers of 3D NAND chips are stacked on the first layer of 3D NAND chips.

Preferably, each 3D NAND chip is offset to one side with respect to the 3D NAND chip of its lower layer.

Preferably, each of the 3D NAND chips is electrically connected to the substrate through a conductive line.

Compared with the prior art, the utility model discloses following beneficial effect has:

the utility model discloses a be provided with stacked structure of eMMC P chip of flip-chip main control chip, this structure is provided with DRAM chip and flip-chip main control chip on the base plate, is provided with 3D NAND chip on the DRAM chip, and flip-chip main control chip is in the below of DRAM chip, connects through the conductor wire electricity between flip-chip main control chip and the base plate, can save space, effectively uses the inner space, increases product capacity.

Furthermore, the DRAM chip and the 3D NAND chip are vertically arranged, and through the arrangement of the structure, intermediate dummy chips can be saved between the two chips, so that the number of chip stacking layers is increased, and further the capacity is increased.

Furthermore, the thickness of the inverted main control chip and the solder balls is less than or equal to that of the DRAM chip, so that the space of routing is saved.

Further, 3D NAND chips can be stacked on the first layer of 3D NAND chips as required, and because the first layer of 3D NAND chips and the DRAM chips are arranged perpendicular to each other, the overall structure is reduced, and more 3D NAND chips can be stacked.

[ description of the drawings ]

FIG. 1 is a front view of the present invention;

fig. 2 is a side view of the present invention;

wherein: 1 is a flip main control chip; 2 is a first conductive line; 3 is a DRAM chip; 4 is a first layer of 3D NAND chips; 5 is a substrate; 6 is a second conductive line; 7-second tier 3D NAND chip.

[ detailed description ] embodiments

The present invention will be described in further detail with reference to the accompanying drawings:

in the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention; the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and encompass, for example, both fixed and removable connections; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

The utility model discloses a be provided with stacked structure of eMMC P chip of flip-chip main control chip, the great technical problem of whole packaging structure volume that stacked structure occupies among the prior art has been solved to this structure. The utility model discloses or the purpose provide a crisscross stacked structure, solved eMMC product structure in the space more and more littleer, the chip is more and more thin, the more and more high difficult problem of capacity requirement.

Referring to fig. 1 and 2, the utility model discloses a crisscross stacked structure of eMMC chip, this structure includes base plate 5, is provided with DRAM chip 3 and flip-chip main control chip 1 on the base plate 5, and DRAM chip 3 and the adjacent setting of flip-chip main control chip 1, DRAM chip 3 directly bond on base plate 5, and flip-chip main control chip 1 is connected through second conductor wire 6 and base plate 5 electricity. The DRAM chip 3 is provided with a first layer of 3D NAND chips 4, and the length direction of the first layer of 3D NAND chips 4 is perpendicular to the length direction of the DRAM chip 3. The first layer 3D NAND chip 4 is above the flip main control chip 1, and the first layer 3D NAND chip 4 is electrically connected to the substrate 5 through the first conductive line 2. 3D NAND is an emerging type of flash memory developed by intel and magnesium optical co-venture, and addresses the limitations imposed by 2D or planar NAND flash memories by stacking memory particles together, the DRAM chip 3 being a dynamic random access memory.

The distance between the highest position of the second conductive wire 6 and the substrate 5 is less than or equal to the thickness of the DRAM chip 3, so that the flip main control chip can be placed below the 3D NAND chip, and the space can be saved.

The second layer 3D NAND chip 7, the 3 rd layer 3D NAND chip, the 4 th layer are stacked on the first layer 3D NAND chip 4 in sequence, the specific number of the layers can be set according to the packaging structure and the chip requirements, the flip main control chip 1 is arranged on the lower portion of the first layer 3D NAND chip 4, the structure is integrally saved, and the number of the 3D NAND chips stacked upwards can be increased.

The 3D NAND chips 7 are stacked upwards from the first layer 3D NAND chip 4 in a staggered manner, that is, one end of the second layer 3D NAND chip 2 moves to one side for a certain distance relative to the same end of the first layer 3D NAND chip 4, the 3D NAND chips are sequentially placed upwards, and the 3D NAND chip of each layer moves to the same side relative to the 3D NAND chip of the next layer. This way makes 3D NAND directly stack, can stack more multilayer, increases product capacity. Each of the 3D NAND chips is electrically connected to the substrate 5 through a conductive line.

The utility model discloses all related to conductor wires, be the gold thread including first conductor wire 2, second conductor wire 6 and other conductor wires.

This structure reduces the need for dummy chips because the DRAM chip 3 and the first layer 3D NAND chip 7 are arranged in parallel, and can prevent conductive lines from being pressed, compared to the existing stacked structure.

The preparation method of the stacked structure comprises the following steps:

step 1, bonding a DRAM chip 3 on a substrate 5, and bonding a plurality of solder balls 6 on the substrate 5, wherein the solder balls 6 are arranged beside the DRAM chip 3;

and 2, bonding a flip main control chip 1 on the solder balls 6 together.

Step 3, a first layer of 3D NAND chip 4 is bonded on the DRAM chip 3, and the first layer of 3D NAND chip 4 and the DRAM chip 3 are vertical to each other; the first layer of 3D NAND chips 4 is above the flip-chip master chip 1.

And 4, sequentially stacking the upper 3D NAND chips 4 on the first layer of 3D NAND chips 4.

The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. The stacked structure of the eMCP chip provided with the inverted main control chip is characterized by comprising a substrate (5), wherein a DRAM chip (3) is arranged on the substrate (5), a first layer of 3D NAND chip (4) is arranged on the DRAM chip (3), an inverted main control chip (1) is arranged beside the DRAM chip (3), and the inverted main control chip (1) is arranged below the first layer of 3D NAND chip (4); the flip main control chip (1) is electrically connected with the substrate (5) through a second conductive wire (6).

2. The stacked structure of the eMCP chip provided with the flip-chip master chip as claimed in claim 1, wherein a length direction of the first layer of 3D NAND chips (4) and a length direction of the DRAM chip (3) are perpendicular to each other.

3. The stacked structure of the eMCP chip provided with the flip-chip master chip as claimed in claim 1, wherein a distance between a highest point of the second conductive line (6) and the substrate (5) is less than or equal to a height of the DRAM chip (3).

4. The stacked structure of eMCP chips provided with a flip-chip master chip as claimed in claim 1, wherein the first layer of 3D NAND chips (4) are electrically connected with the substrate (5) through first conductive lines (2).

5. The stacked structure of eMCP chips provided with a flip-chip master chip as claimed in claim 4, wherein the first and second conductive lines (2, 6) are gold wires.

6. The stacked structure of the eMCP chip provided with the flip-chip main control chip as claimed in claim 1, wherein the first layer of 3D NAND chips (4) are stacked with a plurality of layers of 3D NAND chips.

7. The stacked structure of eMCP chips provided with a flip-chip master chip as claimed in claim 6, wherein each 3D NAND chip is offset to one side relative to its underlying 3D NAND chip.

8. The stacked structure of eMCP chips provided with a flip-chip master chip as claimed in claim 7, wherein each 3D NAND chip is electrically connected to the substrate (5) by a conductive line.