CN209312762U - The non-hermetically sealed three-dimension packaging eeprom memory that a kind of capacity is 128k × 40bit - Google Patents
The non-hermetically sealed three-dimension packaging eeprom memory that a kind of capacity is 128k × 40bit Download PDFInfo
- Publication number
- CN209312762U CN209312762U CN201920177578.2U CN201920177578U CN209312762U CN 209312762 U CN209312762 U CN 209312762U CN 201920177578 U CN201920177578 U CN 201920177578U CN 209312762 U CN209312762 U CN 209312762U
- Authority
- CN
- China
- Prior art keywords
- lead
- eeprom
- chip
- 40bit
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The utility model discloses the non-hermetically sealed three-dimension packaging eeprom memories that a kind of capacity is 128k × 40bit, eeprom chip including lead frame and five 128k × 8bit, using five eeprom chips as three-dimensional structure stack layer in structure, layer is stacked using chip layer as interconnection printed board, chip is alternately stacked with interconnection printed board in short transverse, form stacked body, by five layers of chip, five layers of interconnection printed board, the pin wiring of one leadframe layers connects into an eeprom memory, the design of three-dimensional structure, realize with single layer of chips occupied area close in the case where realize the extension of capacity and bit wide, non-airtight 3-D multi-chip packaged type improves module assembled density, the utilization of plane space when effectively improving complete machine assembling Rate is conducive to system compact, substantially reduces the plane space that storage component part occupies pcb board, is particularly suitable for application to the Aeronautics and Astronautics field of High Density Integration, miniature requirement.
Description
Technical field
The utility model relates to store equipment, and in particular to the non-hermetically sealed three-dimension packaging that a kind of capacity is 128k × 40bit
Eeprom memory module.
Background technique
Memory is to be mainly used for storing program and various numbers for protecting stored memory device in modern information technologies
According to, and can be in computer operational process high speed, the automatic access for completing program or data.The storage for constituting memory is situated between
Matter mainly uses semiconductor devices and magnetic material at present, and the smallest storage cell is exactly that a bistable state is partly led in memory
The storage member of body circuit or a CMOS transistor or magnetic material, it can store a binary code.By several storages
Member one storage unit of composition, then forms a memory by many storage units again.By access mode, memory can divide
For three kinds of random access memory (RAM), serial-access storage (SAS) and read-only memory (ROM), electrically erasable is read-only
Memory (EEPROM) is one kind of read-only memory.
Eeprom memory belongs to the computer field universal product, is widely used to aerospace, industrial automation etc.
Field, application prospect and market potential are boundless.But normal domestic is unable to reach in terms of reliability and comprehensive Flouride-resistani acid phesphatase
Existing military exigence.Traditional military field is plane distribution without the memory module with comprehensive Flouride-resistani acid phesphatase, and reliability is not
Height, area occupied is big, weight is big.
In recent years, with the high speed development of information technology and national strategy security needs, to the capacity of memory module,
Bit wide and production domesticization, miniaturization propose higher demand.There is an urgent need to small in size, light-weight, high reliablity, synthesis for system
The strong independent intellectual property right memory module of Radiation hardness, of the invention succeeding in developing solve space flight model and weaponry electricity
The problem of subsystem key components production domesticization.
Utility model content
The purpose of this utility model is to provide the non-hermetically sealed three-dimension packaging EEPROM that a kind of capacity is 128k × 40bit to deposit
Reservoir, with overcome the deficiencies in the prior art, the utility model can satisfy system board and store to the EEPROM of large capacity, small size
The demand of device.
In order to achieve the above objectives, the utility model adopts the following technical solution:
The non-hermetically sealed three-dimension packaging eeprom memory that a kind of capacity is 128k × 40bit, including lead frame and five
The eeprom chip of 128k × 8bit, five eeprom chip lower ends are sealed with an interconnection printed board, five interconnection printings
Plate stacks gradually setting, and the eeprom chip in five interconnection printed boards is upward, and lead frame is fixed on bottom interconnection print
Making sheet lower end, five eeprom chip surroundings outsides are equipped with encapsulating glue-line, are equipped with external metallization platingization layer on the outside of encapsulating glue-line and draw
Line, the fly lines in five interconnection printed boards are connected to external metallization platingization layer lead, and lead frame is equipped with outer lead, and five
Fly line in interconnection printed board is connect with outer lead by external metallization platingization layer lead.
Further, clad is equipped on the outside of external metallization platingization layer lead.
Further, outer lead is fixed on lead frame by the slot on lead frame.
Further, the data line of five eeprom chips is connected to outside difference by external metallization platingization layer lead draws respectively
Line；The address wire of five eeprom chips is connected to the same outer lead by external metallization platingization layer lead；Five EEPROM cores
The output of piece makes energy line be connected to the same outer lead by external metallization platingization layer lead；Five writing for eeprom chip make energy line
The same outer lead is connected to by external metallization platingization layer lead；The power supply line of five eeprom chips passes through external metallization platingization
Layer lead is connected to the same outer lead；The chip selection signal line of five eeprom chips is connected to together by external metallization platingization layer lead
One outer lead.
Further, outer lead uses Chisel lead-J5 outer lead.
Further, interconnection printed board uses EE5M40CS-1 or EE5M40CS-2, and lead frame uses B-EE5M40CS.
Further, encapsulating glue-line uses epoxide-resin glue.
Further, external metallization platingization layer lead is using nickel plating, nickel or golden composite layer.
Further, the pin of eeprom chip is connected to external metallization platingization layer by the fly line in interconnection printed board and draws
Line.
Compared with prior art, the utility model has technical effect beneficial below:
A kind of capacity of the utility model is the non-hermetically sealed three-dimension packaging eeprom memory of 128k × 40bit, including lead
The eeprom chip of frame and five 128k × 8bit, five eeprom chip lower ends are sealed with an interconnection printed board, and five
A interconnection printed board stacks gradually setting, and the eeprom chip in five interconnection printed boards is upward, and lead frame is fixed on most
Bottom interconnects printed board lower end, and encapsulating glue-line is equipped on the outside of five eeprom chip surroundings, external gold is equipped on the outside of encapsulating glue-line
Belong to platingization layer lead, the fly line in five interconnection printed boards is connected to external metallization platingization layer lead, and lead frame is equipped with
Outer lead, five fly lines interconnected in printed boards are connect with outer lead by external metallization platingization layer lead, and five are utilized in structure
A eeprom chip stacks layer as three-dimensional structure stack layer, using chip layer as interconnection printed board, and chip and interconnection are printed
Plate is alternately stacked in short transverse, forms stacked body, and five layers of chip, five layers of interconnection printed board, leadframe layers are drawn
Foot wiring connects into an eeprom memory, and the design of three-dimensional structure is realized and connect with single layer of chips occupied area
The extension of capacity and bit wide is realized in the case where close, it is close that non-airtight 3-D multi-chip packaged type improves module assembled
Degree, the utilization rate of plane space, is conducive to system compact when effectively improving complete machine assembling, substantially reduces storage component part occupancy
The plane space of pcb board is particularly suitable for application to the Aeronautics and Astronautics field of High Density Integration, miniature requirement.
Detailed description of the invention
FIG. 1 is a schematic structural view of the utility model.
Fig. 2 is the utility model schematic diagram of circuit connection structure.
Wherein, 1, eeprom chip；2, printed board is interconnected；3, lead frame；5, encapsulating glue-line；6, external metallization platingization layer
Lead；7, outer lead.
Specific embodiment
The utility model is described in further detail with reference to the accompanying drawing:
As shown in Figure 1 and Figure 2, a kind of capacity is the non-hermetically sealed three-dimension packaging eeprom memory of 128k × 40bit, including
The eeprom chip 1 of lead frame 3 and five 128k × 8bit, five 1 lower ends of eeprom chip are sealed with an interconnection print
The pin of making sheet 2, eeprom chip 1 is connect with the fly line in interconnection printed board 2, and five interconnection printed boards 2 stack gradually setting,
Five interconnection printed boards on eeprom chips 1 upwards, lead frame 3 be fixed on the bottom interconnection printed board lower end, five
It is equipped with encapsulating glue-line 5 on the outside of 1 surrounding of eeprom chip, external metallization platingization layer lead 6 is equipped on the outside of encapsulating glue-line 5, five mutually
Fly line in connection printed board 2 is connected to external metallization platingization layer lead 6, and lead frame 3 is equipped with outer lead 7, five interconnections
Fly line in printed board 2 is connect with outer lead 7 by external metallization platingization layer lead 6；
Clad is equipped on the outside of external metallization platingization layer lead 6；
Outer lead 7 on lead frame 3 is final module pin, and outer lead 7 is fixed by the slot on lead frame 3,
Five eeprom chips are respectively welded in five interconnection printed boards 2, on the pin on eeprom chip and interconnection printed board 2
Fly line connection, internal signal is led to module side using fly line technique by interconnection printed board edge, then by five interconnections prints
2 both ends of making sheet are alternately stacked with interlayer backing plate solid, and the module after the completion of stacking is fixed by the filling of encapsulating glue-line 5, are cut later
It is cut into the module of designed size, removes interlayer backing plate, the fly line pin in interconnection printed board 2 is leaked out, then outside encapsulating glue-line 5
External metallization platingization layer is arranged in side, completes surface etch metal-plated layer finally by laser etching process and forms external metallization plating
Change layer lead 6, realizes the assembling of module circuitry；Structural section figure is as shown in Figure 1；
Specific embodiment is as shown in Fig. 2, the five layers of eeprom chip stacked gradually from the bottom to top, respectively the 1st layer
Eeprom chip, the 2nd layer of eeprom chip, the 3rd layer of eeprom chip, the 4th layer of eeprom chip and the 5th layer of eeprom chip；
Five eeprom chips are respectively eeprom chip U1, eeprom chip U2, eeprom chip U3, eeprom chip
U4, eeprom chip U5, specific pin function definition are as shown in table 1:
The data line of five eeprom chips is connected to different outer leads by external metallization platingization layer lead respectively, is I/
000-I/039 pin；The address wire of five eeprom chips is connected to the same outer lead by external metallization platingization layer lead, is
A0-A16 pin；The output of five eeprom chips makes energy line be connected to the same outer lead by external metallization platingization layer lead,
For #OE pin；Five writing for eeprom chip make energy line be connected to the same outer lead by external metallization platingization layer lead, are #
WE pin；The power supply line of five eeprom chips is connected to the same outer lead by external metallization platingization layer lead, draws for Vcc
Foot；The chip selection signal line of five eeprom chips is connected to the same outer lead by external metallization platingization layer lead, draws for #CE0
Foot；Realize that data bits capacity extension, extension background storage available capacity are 5M, data bits is up to 40.
Outer lead uses Chisel lead-J5 outer lead；It interconnects printed board and uses EE5M40CS-1 or EE5M40CS-2, lead
Frame uses B-EE5M40CS；Encapsulating glue-line uses epoxide-resin glue；External metallization platingization layer lead is multiple using nickel plating, nickel or gold
Close layer；What five eeprom chips were all made of is that capacity is 4Mbit, the EEPROM that the TSOP-44 that data bit width is 16 is encapsulated
Chip；
Eeprom chip outer pin, copper foil electricity are drawn a layer pin by external metallization platingization layer lead, outer on lead frame draws
Foot links together, and completes the electrical connection of entire module；Outer lead on lead frame draws the outer signal wire that draws of memory
Out, ultimately forming capacity is 5M, and data bits passes through this three-dimensional structure modeling, shape up to 40 non-hermetically sealed three-dimension packagings
Size is only 18.7mm × 11mm × 9.6mm.
The definition of 1 pin function of table
Using five eeprom chips as three-dimensional structure stack layer in structure, stacked chip layer as interconnection printed board
Chip is alternately stacked with interconnection printed board in short transverse, forms stacked body, stacked body passes through encapsulating, cutting, outer surface by layer
Gold-plated, outer surface metal 3 D stereo groove technique by five layers of chip, five layers of interconnection printed board, leadframe layers pin
Wiring connects into an eeprom memory, and the design of three-dimensional structure is realized close with single layer of chips occupied area
In the case where realize the extension of capacity and bit wide, non-airtight 3-D multi-chip packaged type improves module assembled density,
Module volume is only 18.7mm × 11mm × 9.6mm, and the utilization rate of plane space, is conducive to system when effectively improving complete machine assembling
Miniaturization substantially reduces the plane space that storage component part occupies pcb board, has been particularly suitable for application to High Density Integration, small-sized
The Aeronautics and Astronautics field of change demand.
Claims (9)
1. the non-hermetically sealed three-dimension packaging eeprom memory that a kind of capacity is 128k × 40bit, which is characterized in that including lead frame
The eeprom chip (1) of frame (3) and five 128k × 8bit, five eeprom chip (1) lower ends are sealed with an interconnection print
Making sheet (2), five interconnection printed boards (2) stack gradually setting, and the eeprom chip (1) in five interconnection printed boards is upward,
Lead frame (3) is fixed on bottom interconnection printed board lower end, is equipped with encapsulating glue-line on the outside of five eeprom chip (1) surroundings
(5), it is equipped with external metallization platingization layer lead (6) on the outside of encapsulating glue-line (5), five fly lines interconnected on printed board (2) are and outside
Portion's metal-plated layer lead (6) connection, lead frame (3) are equipped with outer lead (7), the fly line on five interconnections printed board (2)
It is connect with outer lead (7) by external metallization platingization layer lead (6).
2. a kind of capacity according to claim 1 is the non-hermetically sealed three-dimension packaging eeprom memory of 128k × 40bit,
It is characterized in that, clad is equipped on the outside of external metallization platingization layer lead (6).
3. a kind of capacity according to claim 1 is the non-hermetically sealed three-dimension packaging eeprom memory of 128k × 40bit,
It is characterized in that, outer lead (7) is fixed on lead frame (3) by the slot on lead frame (3).
4. a kind of capacity according to claim 1 is the non-hermetically sealed three-dimension packaging eeprom memory of 128k × 40bit,
It is characterized in that, the data line of five eeprom chips is connected to different outer leads by external metallization platingization layer lead respectively；Five
The address wire of eeprom chip is connected to the same outer lead by external metallization platingization layer lead；The output of five eeprom chips
Energy line is set to be connected to the same outer lead by external metallization platingization layer lead；Five writing for eeprom chip make energy line pass through outside
Metal-plated layer lead is connected to the same outer lead；The power supply line of five eeprom chips is connect by external metallization platingization layer lead
To the same outer lead；The chip selection signal line of five eeprom chips is connected to outside same by external metallization platingization layer lead to be drawn
Line.
5. a kind of capacity according to claim 1 is the non-hermetically sealed three-dimension packaging eeprom memory of 128k × 40bit,
It is characterized in that, outer lead uses Chisel lead-J5 outer lead.
6. a kind of capacity according to claim 1 is the non-hermetically sealed three-dimension packaging eeprom memory of 128k × 40bit,
It is characterized in that, interconnection printed board uses EE5M40CS-1 or EE5M40CS-2, and lead frame uses B-EE5M40CS.
7. a kind of capacity according to claim 1 is the non-hermetically sealed three-dimension packaging eeprom memory of 128k × 40bit,
It is characterized in that, encapsulating glue-line uses epoxide-resin glue.
8. a kind of capacity according to claim 1 is the non-hermetically sealed three-dimension packaging eeprom memory of 128k × 40bit,
It is characterized in that, external metallization platingization layer lead is using nickel plating, nickel or golden composite layer.
9. a kind of capacity according to claim 1 is the non-hermetically sealed three-dimension packaging eeprom memory of 128k × 40bit,
It is characterized in that, the pin of eeprom chip (1) is connected to external metallization platingization layer lead by the fly line in interconnection printed board (2)
(6)。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920177578.2U CN209312762U (en) | 2019-01-31 | 2019-01-31 | The non-hermetically sealed three-dimension packaging eeprom memory that a kind of capacity is 128k × 40bit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920177578.2U CN209312762U (en) | 2019-01-31 | 2019-01-31 | The non-hermetically sealed three-dimension packaging eeprom memory that a kind of capacity is 128k × 40bit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209312762U true CN209312762U (en) | 2019-08-27 |
Family
ID=67681511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920177578.2U Active CN209312762U (en) | 2019-01-31 | 2019-01-31 | The non-hermetically sealed three-dimension packaging eeprom memory that a kind of capacity is 128k × 40bit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209312762U (en) |
-
2019
- 2019-01-31 CN CN201920177578.2U patent/CN209312762U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104575584B (en) | System-in-package memory module with embedded memory | |
| CN209401305U (en) | A kind of highly integrated single-chip solid state hard disk | |
| CN209312762U (en) | The non-hermetically sealed three-dimension packaging eeprom memory that a kind of capacity is 128k × 40bit | |
| CN209282202U (en) | The non-hermetically sealed three-dimension packaging SRAM memory that a kind of capacity is 512k × 32bit | |
| CN209312764U (en) | The non-hermetically sealed three-dimension packaging eeprom memory that a kind of capacity is 1M × 8bit | |
| CN209216959U (en) | The non-hermetically sealed three-dimension packaging NOR FLASH memory that a kind of capacity is 16M × 16bit | |
| CN209344070U (en) | The non-hermetically sealed three-dimension packaging SRAM memory module that a kind of capacity is 512k × 32bit | |
| CN209281891U (en) | The non-hermetically sealed three-dimension packaging SDRAM memory that a kind of capacity is 32M × 32bit | |
| CN209401621U (en) | The non-hermetically sealed three-dimension packaging NAND FLASH memory that a kind of capacity is 4G × 8bit | |
| CN209249457U (en) | The non-hermetically sealed three-dimension packaging NAND FLASH memory that a kind of capacity is 16G × 32bit | |
| CN209312763U (en) | The non-hermetically sealed three-dimension packaging SRAM memory that a kind of capacity is 1M × 32bit | |
| CN209216960U (en) | The non-hermetically sealed three-dimension packaging SRAM memory that a kind of capacity is 512K × 40bit | |
| CN208923118U (en) | A kind of three-dimensional encapsulation SIP module | |
| CN208284496U (en) | Packaging body with stacked chips | |
| CN203644763U (en) | Three-dimensional packaging NAND FLASH memory with capacity of 512Mx8bit | |
| CN209150044U (en) | A kind of DDR3 memory based on three-dimensional encapsulation technology | |
| CN220106512U (en) | Novel POP chip packaging structure | |
| CN203406280U (en) | Three-dimensionally packaged SDRAM memory with capacity of 512M x 8bit | |
| CN213071124U (en) | Crisscross stacked structure of eMMC chip | |
| CN213692050U (en) | System-in-package structure of CF storage card | |
| CN218333754U (en) | Chip fan-out type low-thickness packaging structure with bidirectional laminated sheets | |
| CN209471959U (en) | A kind of three-dimensional encapsulation NOR FLASH memory | |
| CN207021253U (en) | A kind of ultra-thin integrated package structure | |
| CN216719092U (en) | High-efficiency PSoC chip based on SiP technology and packaging structure thereof | |
| CN207199618U (en) | A kind of multiple-level stack formula chip-packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |