CN207199618U - A kind of multiple-level stack formula chip-packaging structure - Google Patents

Abstract

The utility model discloses a kind of multiple-level stack formula chip-packaging structure, including substrate, first layer chip is installed at the top of the substrate, leg is welded with the top of the first layer chip, second layer chip is welded with the top of the leg, the bottom of the substrate is welded with the first soldered ball, and the first pallet is provided with the top of the second layer chip, the first module is provided with the top of first pallet.The multiple-level stack formula chip-packaging structure, layers of chips is carried on substrate first, and circuit is accessed by the first soldered ball, then layers of chips is carried again on the first pallet, and in order to prevent multilayer chiop superposition from short circuit phenomenon occurs, in third layer chip and the 4th layer of chip difference module of device first and the second module, and circuit is accessed by the second soldered ball and the 3rd soldered ball respectively, finally layers of chips is carried again on the second pallet, and circuit is accessed by the 4th soldered ball, the encapsulating structure uses multiple-level stack mode.

Description

A kind of multiple-level stack formula chip-packaging structure

Technical field

Chip encapsulation technology field is the utility model is related to, specially a kind of multiple-level stack formula chip-packaging structure.

Background technology

The encapsulation complexity of electronic device and IC devices considerably increases, and the introducing of novel package structure is also increasingly It hurry up, the increasing fast of this packing forms, is attributed to device and system applies requirement in terms of technology and cost to encapsulation, with Encapsulation to become increasingly complex, electronic components fabrication business is also faced with the choice of difficulty.

In order to tackle gradually complicated and integrated chip structure, traditional encapsulating structure is difficult to meet to require, existing Encapsulating structure progressively develops toward low dimensional, low-power consumption and high-frequency direction, but in the number of plies of encapsulation, at present typically most Three to four layers of chip can only be carried more, therefore in terms of the encapsulating structure of the chip number of plies, are had much room for improvement.

Utility model content

The purpose of this utility model is to provide a kind of multiple-level stack formula chip-packaging structure, to solve above-mentioned background technology The problem of middle proposition.

To achieve the above object, the utility model provides following technical scheme：A kind of multiple-level stack formula chip-packaging structure, Including substrate, first layer chip is installed at the top of the substrate, leg, the weldering are welded with the top of the first layer chip Second layer chip is welded with the top of pin, the bottom of the substrate is welded with the first soldered ball, the top peace of the second layer chip Equipped with the first pallet, the first module is installed at the top of first pallet, third layer chip is installed in first module, The second module is welded with the top of first module, the 4th layer of chip, first pallet are installed in second module Bottom be welded with the second soldered ball, be welded with the 3rd soldered ball at the top of first pallet, the top installation of second module There is the second pallet, upper top shell is welded with the top of second pallet, the inner chamber of the upper top shell is arranged with three cavity volumes, and three Individual cavity volume is separately installed with layer 5 chip, heat absorbing sheet and layer 6 chip, the bottom welding of second pallet from top to bottom There is the 4th soldered ball.

Preferably, the left and right sides of the heat absorbing sheet through upper top shell and is extended to outside it, the top of the heat absorbing sheet Metal lead foot is mounted on bottom, and metal lead foot extends respectively to the cavity volume where layer 5 chip and layer 6 chip It is interior.

Preferably, fin is installed at the top of second module.

Preferably, the bottom of the substrate is welded with installation pin.

Compared with prior art, the beneficial effects of the utility model are：

The multiple-level stack formula chip-packaging structure, by setting substrate, first layer chip, leg, second layer chip and One soldered ball, layers of chips is carried on substrate first, and circuit is accessed by the first soldered ball, then carried again on the first pallet Layers of chips, and in order to prevent multilayer chiop superposition from occurring short circuit phenomenon, third layer chip and the 4th layer of chip difference device the In one module and the second module, and circuit is accessed by the second soldered ball and the 3rd soldered ball respectively, finally taken again on the second pallet Carrying layers of chips, (as needed, upper top shell inner casing is divided into multiple cavity volumes, can at most carry three to four layers of chip, and every two layers Heat absorbing sheet is provided between chip, plays a part of radiating), and circuit is accessed by the 4th soldered ball, the encapsulating structure uses Multiple-level stack mode, six layers of chip can be at least carried, relative to traditional encapsulating structure, carrying is more efficient, is manufactured in unit In terms of cost, also reduced.

Brief description of the drawings

Fig. 1 is structural profile illustration of the present utility model.

In figure：1 substrate, 2 first layer chips, 3 legs, 4 second layer chips, 5 first soldered balls, 6 first pallets, 7 first moulds Group, 8 third layer chips, 9 second modules, 10 the 4th layers of chip, 11 second soldered balls, 12 the 3rd soldered balls, 13 second pallets, push up on 14 Shell, 15 layer 5 chips, 16 heat absorbing sheets, 17 the 4th soldered balls, 18 layer 6 chips, 19 fin, 20 installation pins.

Embodiment

Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out Clearly and completely describing, it is clear that described embodiment is only the utility model part of the embodiment, rather than whole Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not making creative work

Referring to Fig. 1, the utility model provides a kind of technical scheme：A kind of multiple-level stack formula chip-packaging structure, including Substrate 1, the top of the substrate 1 are provided with first layer chip 2, and the top of the first layer chip 2 is welded with leg 3, described The top of leg 3 is welded with second layer chip 4, and the bottom of the substrate 1 is welded with the first soldered ball 5, by setting substrate 1, One layer of chip 2, leg 3, the soldered ball 5 of second layer chip 4 and first, carry layers of chips on substrate 1 first, and pass through the first weldering Ball 5 accesses circuit, and the top of the second layer chip 4 is provided with the first pallet 6, and the top of first pallet 6 is provided with the One module 7, third layer chip 8 being installed in first module 7, the top of first module 7 is welded with the second module 9, 4th layer of chip 10 be installed in second module 9, the bottom of first pallet 6 is welded with the second soldered ball 11, and described The top of one pallet 6 is welded with the 3rd soldered ball 12, then carries layers of chips again on the first pallet 6, and in order to prevent multilayer Short circuit phenomenon occurs for chip superposition, and third layer chip 8 and the 4th layer of chip 10 are distinguished in device the first module 7 and the second module 9, And circuit is accessed by the second soldered ball 11 and the 3rd soldered ball 12 respectively, the top of second module 9 is provided with the second pallet 13, The top of second pallet 13 is welded with upper top shell 14, and the inner chamber of the upper top shell 14 is arranged with three cavity volumes, and three appearances Chamber is separately installed with layer 5 chip 15, heat absorbing sheet 16 and layer 6 chip 18, the bottom of second pallet 13 from top to bottom The 4th soldered ball 17 is welded with, finally carries layers of chips again on the second pallet 13, as needed, the inner casing of upper top shell 14 is divided into more Individual cavity volume, three to four layers of chip can be at most carried, and heat absorbing sheet 16 is provided between every layers of chips, play the work of radiating With, and circuit is accessed by the 4th soldered ball 17, the encapsulating structure uses multiple-level stack mode, can at least carry six layers of chip, phase For traditional encapsulating structure, carrying is more efficient, in terms of unit manufacturing cost, is also reduced.

Specifically, the left and right sides of the heat absorbing sheet 16 through upper top shell 14 and is extended to outside it, the heat absorbing sheet 16 top and bottom are mounted on metal lead foot, and metal lead foot extends respectively to layer 5 chip 15 and layer 6 chip 18 In the cavity volume at place, metal lead foot can absorb heat caused by chip operation, and be absorbed by heat absorbing sheet 16, and be expelled to Outside upper top shell 14, heat is prevented to be gathered in upper top shell 14, heat absorbing sheet 16 can use copper sheet or aluminium flake.

Specifically, the top of second module 9 is provided with fin 19, sets fin 19, plays the work of radiating With.

Specifically, the bottom of the substrate 1 is welded with installation pin 20, sets installation pin 20, facilitates the encapsulation knot The installation of structure.

Operation principle：By setting substrate 1, first layer chip 2, leg 3, the soldered ball 5 of second layer chip 4 and first, first Layers of chips is carried on substrate 1, and circuit is accessed by the first soldered ball 5, then carries two layers of core again on the first pallet 6 Piece, and in order to prevent multilayer chiop superposition from short circuit phenomenon occurs, third layer chip 8 and the 4th layer of chip 10 distinguish the mould of device first In the module 9 of group 7 and second, and circuit is accessed by the second soldered ball 11 and the 3rd soldered ball 12 respectively, finally on the second pallet 13 Layers of chips is carried again, as needed, the inner casing of upper top shell 14 is divided into multiple cavity volumes, can at most carry three to four layers of chip, and Heat absorbing sheet 16 is provided between per layers of chips, plays a part of radiating, and circuit, the encapsulation are accessed by the 4th soldered ball 17 Structure uses multiple-level stack mode, can at least carry six layers of chip, and relative to traditional encapsulating structure, carrying is more efficient, In terms of unit manufacturing cost, also reduced.

While there has been shown and described that embodiment of the present utility model, for the ordinary skill in the art, It is appreciated that these embodiments can be carried out with a variety of changes in the case where not departing from principle of the present utility model and spirit, repaiied Change, replace and modification, the scope of the utility model are defined by the appended claims and the equivalents thereof.

Claims (4)

1. a kind of multiple-level stack formula chip-packaging structure, including substrate (1), it is characterised in that：The top installation of the substrate (1) There is first layer chip (2), leg (3) is welded with the top of the first layer chip (2), is welded with the top of the leg (3) Second layer chip (4), the bottom of the substrate (1) are welded with the first soldered ball (5), the top installation of the second layer chip (4) There is the first pallet (6), the first module (7) is installed at the top of first pallet (6), is provided with first module (7) Third layer chip (8), the second module (9) is welded with the top of first module (7), is provided with second module (9) 4th layer of chip (10), the bottom of first pallet (6) are welded with the second soldered ball (11), the top of first pallet (6) The 3rd soldered ball (12) is welded with, the second pallet (13) is installed at the top of second module (9), second pallet (13) Top is welded with upper top shell (14), and the inner chamber of the upper top shell (14) is arranged with three cavity volumes, and three cavity volumes divide from top to bottom Layer 5 chip (15), heat absorbing sheet (16) and layer 6 chip (18), the bottom welding of second pallet (13) are not installed There is the 4th soldered ball (17).

A kind of 2. multiple-level stack formula chip-packaging structure according to claim 1, it is characterised in that：The heat absorbing sheet (16) The left and right sides through upper top shell (14) and extending to outside it, be mounted on metal at the top and bottom of the heat absorbing sheet (16) Lead foot, and metal lead foot is extended respectively in the cavity volume where layer 5 chip (15) and layer 6 chip (18).

A kind of 3. multiple-level stack formula chip-packaging structure according to claim 1, it is characterised in that：Second module (9) fin (19) is installed at the top of.

A kind of 4. multiple-level stack formula chip-packaging structure according to claim 1, it is characterised in that：The substrate (1) Bottom is welded with installation pin (20).