CN103413802A - High power consumption chip packaging structure - Google Patents
High power consumption chip packaging structure Download PDFInfo
- Publication number
- CN103413802A CN103413802A CN2013102596039A CN201310259603A CN103413802A CN 103413802 A CN103413802 A CN 103413802A CN 2013102596039 A CN2013102596039 A CN 2013102596039A CN 201310259603 A CN201310259603 A CN 201310259603A CN 103413802 A CN103413802 A CN 103413802A
- Authority
- CN
- China
- Prior art keywords
- chip
- substrate
- power consumption
- packaging structure
- windowed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 229910000679 solder Inorganic materials 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 11
- 239000011347 resin Substances 0.000 claims abstract description 6
- 229920005989 resin Polymers 0.000 claims abstract description 6
- 239000003921 oil Substances 0.000 claims description 16
- 230000005855 radiation Effects 0.000 claims description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 239000006185 dispersion Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000002002 slurry Substances 0.000 claims description 3
- 239000007787 solid Substances 0.000 claims description 3
- 230000008901 benefit Effects 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 3
- 230000000052 comparative effect Effects 0.000 abstract description 2
- 238000012536 packaging technology Methods 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 238000005457 optimization Methods 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a high power consumption chip packaging structure, which is characterized by comprising a substrate, a chip, a plurality of through holes, a plurality of radiating solder balls and insulating resin, wherein the substrate is provided with a top surface and a bottom surface which are opposite to each other; the internal part of the substrate is a base material, the surface of the substrate is an etched metal line layer, and the metal line layer is coated with a solder resisting layer; the chip is configured on the top surface fo the substrate; a plurality of green oil windows are arranged in the solder resisting layer of the substrate just below the chip, and the exposed metal line layer in the green oil window regions is in direct contact with the chip; the plurality of through holes are arranged in the substrate below the chip; the plurality of solder balls are configured on the bottom surface of the substrate and are welded on a PCB board; and the insulating resin is filled in a packaging space of the packaging structure. The high power consumption chip packaging structure has the advantages of low technical complexity and considerable cost comparative advantage, has better radiating effect for the high power consumption packaged chips when compared with existing main mainstream bonding plastic packaging technology, and can significantly reduce the temperature difference of the chip surface junction temperature.
Description
Technical field
The invention belongs to semiconductor memory encapsulation technology field, be specifically related to a kind of large power consumption chip-packaging structure, this structure efficiently solves the heat dissipation problem of large power consumption chip in bonding BGA encapsulation.
Background technology
The power consumption of traditional die generally is no more than 0.5W, and be 2～5W for the large power consumption chip power-consumption of bonding bga structure, because power consumption has increased by 4～10 times than traditional die, corresponding heat dissipation problem also just highlights, and traditional bonding plastic package structure can not meet the heat radiation of large power consumption chip, in use, because caloric value is very large, occur that easily heat radiation is bad, can cause the components and parts spoilage to promote, reliability is bad.More existing technological improvements are can partly solve the problem of large power consumption chip cooling by the encapsulating structure that increases fin, as PBGA, FlipChip etc., but the quality to personnel, the kind of board, the material technology complexity is high, production capacity is on the low side, and the cost that this encapsulation technology is brought is much larger than maturation bonding plastic packaging encapsulating structure at a low price.
Summary of the invention
The purpose of this invention is to provide a kind of unnecessary change packing forms or additionally set up fin and change encapsulating structure, and cause the increase of packaging cost, just can solve the large power consumption chip-packaging structure of the bad problem of the high-power chip heat radiation of traditional plastic-sealed body bonding packaging structure.
For achieving the above object, the present invention has adopted following technical scheme:
A kind of large power consumption chip-packaging structure, is characterized in that, comprising:
One substrate, have a relative end face and a bottom surface; The inside of substrate is base material, and substrate surface is the metallic circuit layer that etching is good, also is coated with solder mask on described metallic circuit layer;
Chip, be disposed on the end face of described substrate; Under chip, on the solder mask of substrate, be provided with a plurality of green oils and window, the metallic circuit layer that described green oil windowed regions exposes directly contacts with chip;
Be located at a plurality of via holes on substrate, be located at the chip below;
A plurality of heat radiation tin balls, be disposed at the bottom surface of substrate, and the ball bonding of described heat radiation tin is connected to pcb board;
The insulating resin of filling in the encapsulated space of encapsulating structure.
As optimization, the circular-arc of dispersion that be shaped as that described green oil is windowed windowed.
Optimize as a supplement, it is the circle of 150um that described green oil is windowed as radius, and quantity is 9, is nine grids and arranges, be positioned at chip under, in chip outer edge 100um frame.
As optimization, described green oil is windowed inner region entirely for the metallic circuit layer, without exposed base material.
As optimization, in described via hole, plate solid copper or fill up the copper slurry, be used for increasing heat transfer efficiency.
Inventive principle:
Encapsulation heat-conduction principle of the present invention is to utilize conductive silver paste under chip and the metal speciality of substrate contacts, the material of choosing high coefficient of thermal conductivity of choosing at silver-colored pulp material, conduction heat energy is to the heat radiation tin ball of package outside, via heat radiation tin ball, conduct to PCB again, finally via PCB circuit surface, heat energy is distributed.We take the base plate for packaging solder mask is carried out to the part processing of windowing, windowing area under the increase chip, make the metallic circuit layer of substrate come out, increase the heat transfer area of metal, increase the number of vias of chip infrabasal plate, increase tin nodule number amount, increase simultaneously the number of vias of the corresponding PCB of work chip position in this.The heat energy produced when chip works can conduct by the metallic circuit layer below welding resistance is windowed faster.
The present invention is that the zone that the tin nodule number amount that increases at the chip infrabasal plate and welding resistance are windowed is the GND signal, increases after the ground connection ball return flow path that can effectively reduce high speed signal, improves system signal integrality and Power Integrity.Can, in conjunction with the collaborative design of PCB, further effectively improve the heat radiation of chip.
The invention advantage:
The present invention has low process complexity and considerable cost comparative benefits, with existing main flow bonding plastic packaging encapsulation technology, compare, radiating effect for large power consumption packaged chip is better, can significantly reduce the chip surface junction temperature temperature difference, be ripe technological process for semiconductor fabrication process fully.And compare with other encapsulation technology that improves radiating efficiency, the encapsulating products that has more cost advantage can be provided.
The accompanying drawing explanation
Fig. 1 is the profile of the large power consumption chip-packaging structure of the present invention;
Wherein, 1, substrate, 2, solder mask, 3, chip, 4, green oil windows, 5, the metallic circuit layer, 6, via hole, 7, the tin ball, 8, insulating resin, 9, gold thread, 10, base material.
Embodiment
Below in conjunction with accompanying drawing and a preferred embodiment, technical scheme of the present invention is further described.
Embodiment:
As shown in Figure 1: a kind of large power consumption chip-packaging structure comprises: a substrate 1 has a relative end face and a bottom surface; The inside of substrate 1 is base material 10, and substrate 1 surface is the metallic circuit layer 5 that etching is good, on metallic circuit layer 5, also is coated with solder mask 2;
Also comprise chip 3, be disposed on the end face of described substrate 1; Under chip 3, on the solder mask 2 of substrate 1, be provided with a plurality of green oils and window 4, the described green oil metallic circuit layers 5 that 4 zones expose of windowing directly contact with chip 3;
Also comprise a plurality of via holes 6 of being located on substrate 1, be located at chip 3 belows;
Also comprise a plurality of heat radiation tin balls 7, be disposed at the bottom surface of substrate 1, described heat radiation tin ball 7 is welded in pcb board;
The insulating resin 8 of filling in the encapsulated space of encapsulating structure.
Heat transfer path: the heat that chip 3 produces conducts to the metallic circuit layer 5 of direct contact substrate by the conductive silver paste of chip itself, then by the heat radiation tin ball 7 of via hole 6 conduction heat energy to package outside, via heat radiation tin ball 7, conduct to PCB again, finally via PCB circuit surface, heat energy is distributed, this heat radiation conductive process is direct, efficiency is high, and radiating effect is better, can significantly reduce the chip surface junction temperature temperature difference.
Window 4 the circular-arc of dispersion that be shaped as of described green oil windowed.Described green oil windows 4 for radius is the circle of 150um, and quantity is 9, is nine grids and arranges, be positioned at chip 3 under, in chip 4 outer edge 100um frames.
Described green oil is windowed 4 inner regions entirely for metallic circuit layer 5, without exposed base material 10.
The interior plating solid copper of described via hole 6 or fill up copper slurry, be used for increasing heat transfer efficiency.
Silicon core is that the chip surface junction temperature presents certain anti-correlation with the temperature difference of room temperature with the number of base plate for packaging and corresponding PCB louvre quantity quantity to the thermal resistivity of air.
It is to be noted; as described above is only in order to explain the present invention's preferred embodiment; not attempt is done any formal restriction to the present invention according to this; be with; all any modification or changes that the relevant the present invention that does under identical invention spirit is arranged, all must be included in the category that the invention is intended to protection.
Claims (5)
1. a large power consumption chip-packaging structure, is characterized in that, comprising:
One substrate, have a relative end face and a bottom surface; The inside of substrate is base material, and substrate surface is the metallic circuit layer that etching is good, also is coated with solder mask on described metallic circuit layer;
Chip, be disposed on the end face of described substrate; Under chip, on the solder mask of substrate, be provided with a plurality of green oils and window, the metallic circuit layer that described green oil windowed regions exposes directly contacts with chip;
Be located at a plurality of via holes on substrate, be located at the chip below;
A plurality of heat radiation tin balls, be disposed at the bottom surface of substrate, and the ball bonding of described heat radiation tin is connected to pcb board;
The insulating resin of filling in the encapsulated space of encapsulating structure.
2. large power consumption chip-packaging structure according to claim 1, is characterized in that, the circular-arc of dispersion that be shaped as that described green oil is windowed windowed.
3. large power consumption chip-packaging structure according to claim 2, is characterized in that, it is the circle of 150um that described green oil is windowed as radius, and quantity is 9, is nine grids and arranges, be positioned at chip under, in chip outer edge 100um frame.
4. large power consumption chip-packaging structure according to claim 3, is characterized in that, described green oil is windowed inner region entirely for the metallic circuit layer, without exposed base material.
5. large power consumption chip-packaging structure according to claim 4, is characterized in that, in described via hole, plates solid copper or fill up the copper slurry.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310259603.9A CN103413802B (en) | 2013-06-26 | 2013-06-26 | A kind of large power dissipating chip encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310259603.9A CN103413802B (en) | 2013-06-26 | 2013-06-26 | A kind of large power dissipating chip encapsulating structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103413802A true CN103413802A (en) | 2013-11-27 |
| CN103413802B CN103413802B (en) | 2016-04-27 |
Family
ID=49606800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310259603.9A Active CN103413802B (en) | 2013-06-26 | 2013-06-26 | A kind of large power dissipating chip encapsulating structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103413802B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018018848A1 (en) * | 2016-07-29 | 2018-02-01 | 广东美的制冷设备有限公司 | Intelligent power module and method for manufacturing same |
| CN112908943A (en) * | 2021-01-12 | 2021-06-04 | 华为技术有限公司 | Embedded packaging structure, preparation method thereof and terminal equipment |
| WO2023093211A1 (en) * | 2021-11-26 | 2023-06-01 | Oppo广东移动通信有限公司 | Chip heat dissipation structure and electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1790684A (en) * | 2004-12-17 | 2006-06-21 | 三星电机株式会社 | Ball grid array substrate having window and method of fabricating same |
| CN102157476A (en) * | 2010-03-04 | 2011-08-17 | 日月光半导体制造股份有限公司 | Semiconductor package with single sided substrate design and manufacturing methods thereof |
| CN203351588U (en) * | 2013-06-26 | 2013-12-18 | 力成科技（苏州）有限公司 | High power consumption type chip packaging structure |
-
2013
- 2013-06-26 CN CN201310259603.9A patent/CN103413802B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1790684A (en) * | 2004-12-17 | 2006-06-21 | 三星电机株式会社 | Ball grid array substrate having window and method of fabricating same |
| CN102157476A (en) * | 2010-03-04 | 2011-08-17 | 日月光半导体制造股份有限公司 | Semiconductor package with single sided substrate design and manufacturing methods thereof |
| CN203351588U (en) * | 2013-06-26 | 2013-12-18 | 力成科技（苏州）有限公司 | High power consumption type chip packaging structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018018848A1 (en) * | 2016-07-29 | 2018-02-01 | 广东美的制冷设备有限公司 | Intelligent power module and method for manufacturing same |
| CN112908943A (en) * | 2021-01-12 | 2021-06-04 | 华为技术有限公司 | Embedded packaging structure, preparation method thereof and terminal equipment |
| WO2023093211A1 (en) * | 2021-11-26 | 2023-06-01 | Oppo广东移动通信有限公司 | Chip heat dissipation structure and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103413802B (en) | 2016-04-27 |
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| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 215000 33 Xinghai street, Suzhou Industrial Park, Suzhou City, Jiangsu Province Patentee after: Yuancheng Technology (Suzhou) Co.,Ltd. Address before: 215000 33 Xinghai street, Suzhou Industrial Park, Suzhou City, Jiangsu Province Patentee before: Powertech Technology (Suzhou) Co.,Ltd. |
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| CP03 | Change of name, title or address |