CN102157476A

CN102157476A - Semiconductor package with single sided substrate design and manufacturing methods thereof

Info

Publication number: CN102157476A
Application number: CN2011100506113A
Authority: CN
Inventors: 苏洹漳; 黄士辅; 李明锦; 陈嘉成; 谢佳雄; 陈姿慧; 陈光雄; 谢宝明
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2010-03-04
Filing date: 2011-03-03
Publication date: 2011-08-17
Anticipated expiration: 2031-03-03
Also published as: CN104752391A; CN102157476B; TW201507084A; TWI538137B; CN104752391B

Abstract

The present invention discloses a semiconductor package and manufacturing methods thereof. The semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity.

Description

Semiconductor packages and manufacture method thereof with one-sided substrate design

Technical field

The present invention relates to a kind of semiconductor element encapsulation and manufacture method thereof, and particularly relate to a kind of semiconductor element encapsulation and manufacture method thereof with one-sided substrate design.

Background technology

Integrated circuit (IC) encapsulation technology is being played the part of important role in electronic industry.Along with lightweight, compactness and high efficiency have become the typical requirement of consumer electronics's element and communication products, Chip Packaging should provide advantageous electrical properties, less cumulative volume and a large amount of I/O port.The substrate that uses in these Chip Packaging often has a plurality of metal levels that can use circuit (traces) and/or through hole (vias) to be electrically connected.Along with the size of Chip Packaging reduces, these are used to connect the circuit of a plurality of metal levels and through hole and can become littler and tight spacing more, and this can increase the cost and the complexity of technique of integrated circuit packaging.Therefore, need develop a kind of substrate, it has thin configuration, makes, is suitable for a large amount of productions by more uncomplicated technology, and can highly produce yield production.Also need to develop the correspondence encapsulation that comprises described substrate, and the manufacture method of described substrate and described corresponding encapsulation.

Contrast known technology just and just need develop semiconductor packages described herein and correlation technique.

Summary of the invention

Example of the present invention is relevant for a kind of semiconductor packages.In an embodiment, semiconductor packages comprises base board unit, tube core and package main body.Base board unit comprises: (1) has first patterned conductive layer of upper surface; (2) be disposed at first dielectric layer of the upper surface of first patterned conductive layer, first dielectric layer exposes the part of first patterned conductive layer to form a plurality of first contact mats; (3) be positioned at first patterned conductive layer below and have second patterned conductive layer of lower surface; (4) second dielectric layer between first patterned conductive layer and second patterned conductive layer, wherein second dielectric layer defines and a plurality ofly extends to the opening of second patterned conductive layer from first patterned conductive layer, and wherein second patterned conductive layer comprises a plurality of second contact mats that exposed by second dielectric layer; And (5) a plurality of conductive projections, each conductive projection extends to one second corresponding contact mat via being arranged in a corresponding opening of second dielectric layer from first patterned conductive layer, and each conductive projection is filled in each opening of complying with that is arranged in second dielectric layer correspondence.At least one of them conductive projection defines groove.Tube core is electrically connected to first contact mat.Package main body covers first patterned conductive layer and tube core.

Another example of the present invention is relevant for a kind of manufacture method of substrate.In an embodiment, the method comprises: (1) provides the carrier with upper surface and lower surface, and forms the first metal layer of the upper surface of contiguous carrier; (2) formation is a plurality of to vertically extending first conducting block of the first metal layer, and each first conducting block has upper surface; (3) form first dielectric layer that defines a plurality of first openings, each first opening exposes the part of the upper surface of one first corresponding conducting block; (4) form first conductive projection and first patterned conductive layer, each first conductive projection extends to first patterned conductive layer from one first conducting block of correspondence, and is filled in one first corresponding opening; And (5) remove carrier to expose the first metal layer.

Another example of the present invention is relevant for a kind of manufacture method of semiconductor packages.In an embodiment, the method comprises: (1) provides substrate, and it comprises (a) metal level; (b) conducting block of a plurality of formation adjacent metal layers, each conducting block has upper surface; (c) define the dielectric layer of opening, each opening exposes the part of the upper surface of a corresponding conducting block; (d) patterned conductive layer; And (e) a plurality of conductive projections, each conductive projection extends to patterned conductive layer from a conducting block of correspondence, and is filled in a corresponding opening; (2) electrically connect chip to patterned conductive layer; (3) form package main body and cover dielectric layer and tube core; And (4) remove metal level to expose conducting block.

Other examples of the present invention and embodiment.More than general introduction and following detailed description the in detail are not to be intended to limit the invention to any specific embodiment, but only are intended to describe some embodiments of the present invention.

Description of drawings

Fig. 1 is the generalized section of a kind of semiconductor packages of embodiments of the invention.

Fig. 2 is the generalized section of a kind of semiconductor packages of embodiments of the invention.

Fig. 3 is the generalized section of a kind of semiconductor packages of embodiments of the invention.

Fig. 4 is the generalized section of a kind of semiconductor packages of embodiments of the invention.

Fig. 5 is the generalized section of a kind of semiconductor packages of embodiments of the invention.

Fig. 6 is the generalized section of a kind of semiconductor packages of embodiments of the invention.

Fig. 7 is the generalized section of a kind of semiconductor packages of embodiments of the invention.

Fig. 8 is the generalized section of a kind of semiconductor packages of embodiments of the invention.

Fig. 9 is the generalized section of a kind of semiconductor packages of embodiments of the invention.

Figure 10 is the generalized section of a kind of semiconductor packages of embodiments of the invention.

Figure 11 A to Figure 11 Y is the generalized section of manufacture method of a kind of semiconductor packages of embodiments of the invention.

Figure 12 is the generalized section of a kind of semiconductor packages of embodiments of the invention.

Figure 13 is the schematic top plan view of the semiconductor packages of Figure 12.

Be character and the purpose of understanding some embodiments of the present invention better, should be with reference to the following detailed description of making in conjunction with the accompanying drawings.In the accompanying drawings, unless context regulation clearly in addition, otherwise same reference numerals is represented similar elements.

Description of reference numerals

100,200,300,400,500,600,700,800,900,1000,1200: semiconductor packages

102,302: tube core

104,204: base board unit

106: package main body

110,210,610,710,810,910,1146,1210: patterned conductive layer

112,142,146,1102,1120,1121: upper surface

114,1110,1111: conducting block

116,134,144,234,1104: lower surface

118,124,218,228,424,524,624,724,1148,1149,1156: dielectric layer

120,402,502,611,711,811,911,1107a, 1107b, 1109a, 1109b, 1124a, 1124b, 1126a, 1126b, 1130a, 1130b, 1132a, 1132b, 1140,1141: opening

122,122a, 222a, 222b, 622,722,822,922,1137a, 1137b: conductive projection

126,226a, 226b: first contact mat

130,130a, 230,230a, 230b: second contact mat

133: electrical contact

136: bonding wire

138: active surface

140,940: the tube core adhesion coating

141: primer

148,248b, 249: circuit

150: thickness

214,1103,1105,1116,1117,1122,1123,1128,1129,1142,1142 ', 1144: conductive layer

227,1150: surface-treated layer/electrodeposited coating

335: the fusion conductive projection

723,823,923: groove

1100: carrier

1106,1108,1138,1139: the photoresist layer

1112,1114,1134,1136: layer

1152: substrate

1154: molded structure

1158,1160: dotted line

623: groove

1162,1164,1166,1168: barrier layer

1110a, 1111a: first

1110b, 1111b: second portion

1190: glass

1112a: first opening

1180,1181: Seed Layer

1182a, 1182b: part

1172: thickness

1250: ground plane

Embodiment

At first, please refer to Fig. 1, the generalized section of a kind of semiconductor packages of its explanation embodiments of the invention.Semiconductor packages 100 comprises tube core 102, base board unit 104 and package main body 106.One or more conducting block 114 that base board unit 104 comprises the patterned conductive layer 110 with upper surface 112 and has lower surface 116.Patterned conductive layer 110 horizontal expansions are in base board unit 104.Base board unit 104 also comprises the dielectric layer 118 between patterned conductive layer 110 and conducting block 114.Dielectric layer 118 has lower surface 134.Dielectric layer 118 defines a plurality of openings 120 that extend to conducting block 114 from patterned conductive layer 110.Each conductive projection 122 extends to corresponding conducting block 114 via an opening 120 of correspondence from patterned conductive layer 110.Conductive projection 122 also can form as same conductive layer, for example is Seed Layer (please refer to Figure 11 K).Perhaps, conductive projection 122 also can comprise and forming as same conductive layer, for example is the first of Seed Layer (please refer to Figure 11 K) and is formed at second portion on the Seed Layer (please refer to Figure 11 M).At least a portion of the first of conductive projection 122 is configurable between the second portion and conducting block 114 of conductive projection 122.In an embodiment, each conductive projection 122 is filled in fact in the corresponding opening 120.Base board unit 104 also comprises dielectric layer 124, and wherein dielectric layer 124 is disposed at the upper surface 112 of patterned conductive layer 110.Dielectric layer 124 can be welding resisting layer (solder mask).Dielectric layer 124 exposes the part of patterned conductive layer 110 to form a plurality of first contact mats 126.In an embodiment, for example in the application of wire-bonded, first contact mat 126 can be positioned at the outside of tube core 102 occupied areas (footprint).Perhaps, for example in the application of flip-chip bonded (flip-chip bonding), first contact mat 126 can be positioned at tube core 102 belows.In an embodiment, first contact mat 126 can not covered by surface-treated layer (surface finish layer) (illustrating).

In an embodiment, dielectric layer 118 exposes the lower surface 116 of conducting block 114 to form a plurality of second contact mats 130.Second contact mat 130 can be used for external electric and is connected to encapsulation 100, for example is electrically connected to another semiconductor packages or is electrically connected to other elements on the circuit board.For example, for example the electrical contact 133 of soldered ball can be electrically connected to and dispose one second contact mat 130 that is adjacent to correspondence.

In an embodiment, each conductive projection 122 has the height to the scope of about 150 μ m between about 30 μ m, and to about 100 μ m, and about 100 μ m are to about 150 μ m to about 50 μ m, about 30 μ m to about 100 μ m, about 50 μ m for for example about 30 μ m.The diameter of each conductive projection 122 can be in the scope of about 150 μ m to 250 μ m, and for example diameter is about 200 μ m.Each conductive projection 122 has upper surface 142 that has first area and the lower surface 144 that has second area.In an embodiment, first area is greater than second area.In addition, the upper surface 146 of each second contact mat 130 has the 3rd area.The diameter of second contact mat 130 can be between about 150 μ m to changing more than about 300 μ m.Therefore, in an embodiment, the 3rd area is greater than second area.Perhaps, the 3rd area also can be less than or equal to second area.In an embodiment, the upper surface 142 of conductive projection 122 and lower surface 144 can have and include, but is not limited to circular in fact shape, oval in shape, foursquare in fact shape and the shape of rectangle in fact in fact.

The design that has one-sided substrate in the embodiments of the invention, conductive projection 122 is electrically connected to second contact mat 130 with patterned conductive layer 110, and need not through hole, for example is the through hole through electroplating.This can significantly reduce the cost of encapsulation 100.In addition, some conductive projections 122 (for example be conductive projection 122a, it is disposed at the below of tube core to small part, and is as described below) can promote heat conduction to leave tube core 102, and leave encapsulation 100.And, second contact mat 130 can in be embedded in the dielectric layer 118, this can increase encapsulation 100 installation reliability, reduces because stress is concentrated.

In an embodiment, the lower surface 116 of conducting block 114 is recessed into the lower surface 134 in dielectric layer 118, makes second contact mat 130 be recessed in lower surface 134.Second contact mat 130 is recessed in lower surface 134 and can promotes electrical contact 133 to be attached to second contact mat 130.Perhaps, the lower surface 116 of conducting block 114 can be exposed to lower surface 134 places of dielectric layer 118.

In an embodiment, encapsulation 100 has the thickness 150 to the scope of about 500 μ m between about 200 μ m, for example about 200 μ m to about 350 μ m, about 300 μ m to about 350 μ m, about 300 μ m to about 400 μ m, about 300 μ m to about 450 μ m, and about 300 μ m are to about 500 μ m, are not limited thereto scope but encapsulate 100 thickness.

In an embodiment, the joint sheet on the active surface 138 of tube core 102 is electrically connected to first contact mat 126 via bonding wire 136.First contact mat 126 be disposed at tube core 102 around, and can center on tube core 102 wholly or in part.Package main body 106 covers or coats tube core 102, bonding wire 136 and first patterned conductive layer 110 in fact, to provide mechanical stability and to the protection of oxidation, humidity and other environmental conditions.Package main body 106 can be made by moulding material, moulding material can comprise, for example is novolaks base resin (Novolac-based resin), epoxy (epoxy-based resin), poly-siloxy resin (silicone-based resin), other suitable packaging bodies.Also can comprise for example Powdered silica (SiO ₂) wait suitable filler.

In an embodiment, tube core 102 configurations are adjacent to dielectric layer 124, and its part can be used as die pad.Tube core adhesion coating (die attach layer) the 140th is made of the chip join material, for example is stick or film, optionally makes an addition between tube core 102 and the dielectric layer 124.Tube core adhesion coating 140 can comprise epoxy resin, resin or other appropriate materials.

One-sided substrate for example is a base board unit 104, often has single metal level (for example being patterned conductive layer 110).In this single metal level, can connect up to obtain fan-in (fan-in) configuration, fan-out (fan-out) configuration or both combinations via circuit.In an embodiment, patterned conductive layer 110 can comprise circuit 148, and it is electrically connected to a corresponding conductive projection 122 with each first contact mat 126, and is electrically connected to the second corresponding contact mat 130.In the embodiment in figure 1, circuit 148 is electrically connected in the fan-out configuration first contact mat 126 in outside second contact mat 130 that extends of the footprint area of tube core 102.In an embodiment, the part at least partially in tube core 102 belows of patterned conductive layer 110 also can be electrically connected to the second contact mat 130a via conductive projection 122a.Although in the embodiment in figure 1, tube core 102 is not electrically connected to the conductive projection 122a and the second contact mat 130a, and the conductive projection 122a and the second contact mat 130a still can help to conduct heat and leave tube core 102 and leave encapsulation 100.

Fig. 2 is the generalized section of a kind of semiconductor packages 200 of embodiments of the invention.Semiconductor packages 200 is similar to the semiconductor packages 100 that Fig. 1 describes in many aspects, therefore only discusses the different examples of semiconductor packages 200 herein.Semiconductor packages 200 comprises base board unit 204, wherein base board unit 204 comprises patterned conductive layer 210 (being similar to patterned conductive layer 110), and this patterned conductive layer 210 comprises the first contact mat 226a (being similar to first contact mat 126), circuit 248 (being similar to circuit 148), conductive projection 222 (being similar to conductive projection 122), conductive layer 214 and dielectric layer 228.Conductive layer 214 comprises second contact mat 230 (being similar to second contact mat 130) and is adjacent to one or more circuit 249 of the lower surface 234 of dielectric layer 218 (being similar to dielectric layer 118).Dielectric layer 228 exposes the part of conductive layer 214 to form second contact mat 230.In an embodiment, first contact mat 226 can be covered by surface-treated layer 227.

In an embodiment, the tube core 102 second contact mat 230b that is electrically connected to tube core 102 belows via the first contact mat 226b, circuit 248b and the conductive projection 222b of the footprint area outside of bonding wire 136, tube core 102.Promote this fan-in of encapsulation 200 to support by circuit 248b, wherein circuit 248b extends laterally to the first contact mat 226b of the footprint area outside that is positioned at tube core 102 from tube core 102 belows.As the description of previous Fig. 1, can connect up to obtain fan-in configuration, fan-out configuration or both combinations via the circuit that is included in the single metal level 210.The second contact mat 230b can cover conductive projection 222b, and making does not need additional wires on the lower surface 234 of dielectric layer 218.

As described previously, the advantage of the one-sided substrate design of embodiments of the invention is, conductive projection is electrically connected to the patterned conductive layer on first side of base board unit the contact mat on second side of base board unit, and need not through hole (such as, through the through hole of plating).Encapsulation 200 utilizes this advantage of one-sided substrate design.In addition, the additional conductive layer 214 of encapsulation 200 provides extra cloth linear elasticity via the circuit 249 on the lower surface 234 of dielectric layer 218.In an embodiment, the second contact mat 230a is electrically connected to conductive projection 222a via circuit 249, and can be from its corresponding conductive projection 222a transverse shift.Circuit 249 can be covered by dielectric layer 228, and can cover conductive projection 222a.Advantageously make conductive projection 222 from second contact mat, 230 transverse shifts of its correspondence to simplify the wiring in the encapsulation 200, because the location of second contact mat 230 can be based on requiring to the outside interface that encapsulates 200 and being what fix.

Fig. 3 is the generalized section of a kind of semiconductor packages 300 of embodiments of the invention.Semiconductor packages 300 is similar to the semiconductor packages 100 that Fig. 1 describes, and difference is: tube core 302 is flip-chip bonded.Primer (underfill layer) optionally makes an addition between tube core 302 and the dielectric layer 124.Therefore, the second contact mat 130a of tube core 302 belows can be electrically connected to tube core 302 via fusion conductive projection (fused conductivebump) 335, and this fusion conductive projection 335 can be by for example being that electric conducting materials such as scolder are made.Tube core 302 also can be electrically connected to second contact mat 130 of one or more periphery that is positioned at tube core, for example is that fan-out is used.Be electrically connected tube core 302 to these second contact mats 130 of tube core periphery also can see through one or more fusion conductive projection 335 that is positioned at the tube core below to patterned conductive layer 110 to dielectric layer 118 mark gland (not illustrating).Persons skilled in the art will be understood, and the encapsulation 200 of Fig. 2 can also similar fashion be supported flip-chip bonded.

Fig. 4 is the generalized section of a kind of semiconductor packages 400 of embodiments of the invention.Semiconductor packages 400 is similar to the semiconductor packages 100 that Fig. 1 describes, and difference is: tube core adhesion coating 140 is adjacent to dielectric layer 118.Tube core adhesion coating 140 can be arranged in by the defined opening 402 of dielectric layer 424 (being similar to the dielectric layer 124 of Fig. 1 in addition).Persons skilled in the art will be understood, and the encapsulation 200 of Fig. 2 also can be supported similar structures.

Fig. 5 is the section profile of a kind of semiconductor packages 500 of embodiments of the invention.Semiconductor packages 500 is similar to the semiconductor packages 300 that Fig. 3 describes, and difference is: primer 141 is adjacent to dielectric layer 118.Primer 141 can be between tube core 302 and dielectric layer 118, and in the defined opening 502 of dielectric layer 524 (being similar to the dielectric layer 124 of Fig. 1 in addition).Persons skilled in the art will be understood, and the encapsulation 200 of Fig. 2 also can be supported the flip-chip bonded with similar structures.

Fig. 6 is the generalized section of a kind of semiconductor packages 600 of embodiments of the invention.Semiconductor packages 600 is similar to the semiconductor packages 100 that Fig. 1 describes, difference is: patterned conductive layer 610 defines the opening 611 of being filled by the part of dielectric layer 624 in fact, and one or more conductive projection 622 defines groove 623 separately, and the part of dielectric layer 624 is filled in the groove 623 in fact.Patterned conductive layer 610, dielectric layer 624 and conductive projection 622 are similar to patterned conductive layer 110, dielectric layer 124 and the conductive projection 122 of Fig. 1 in addition respectively.

Fig. 7 is the generalized section of a kind of semiconductor packages 700 of embodiments of the invention.Semiconductor packages 700 is similar to the semiconductor packages 200 that Fig. 2 describes, difference is: patterned conductive layer 710 defines the opening 711 of being filled by the part of dielectric layer 724 in fact, and one or more conductive projection 722 defines groove 723 separately, and the part of dielectric layer 724 is filled in the groove 723 in fact.Patterned conductive layer 710, dielectric layer 724 and conductive projection 722 are similar to patterned conductive layer 210, dielectric layer 124 and the conductive projection 222 of Fig. 1 and 2 in addition respectively.

Fig. 8 is the generalized section of a kind of semiconductor packages 800 of embodiments of the invention.Semiconductor packages 800 is similar to the semiconductor packages 300 that Fig. 3 describes, difference is: patterned conductive layer 810 defines and is melted the opening 811 that conductive projection 335 is filled in fact, and one or more conductive projection 822 defines groove 823 separately, and fusion conductive projection 335 is filled in the groove 823 in fact.Patterned conductive layer 810 and conductive projection 822 are similar to patterned conductive layer 110 and the conductive projection 122 of Fig. 1 in addition.Persons skilled in the art will be understood, and the encapsulation 200 of Fig. 2 also can be supported the flip-chip bonded with similar structures.

Fig. 9 is the generalized section of a kind of semiconductor packages 900 of embodiments of the invention.Semiconductor packages 900 is similar to the semiconductor packages 400 that Fig. 4 describes, difference is: patterned conductive layer 910 defines the opening 911 of being filled by tube core adhesion coating 940 in fact, and one or more conductive projection 922 defines groove 923 separately, and tube core adhesion coating 940 is filled in the groove 923 in fact.Patterned conductive layer 910, conductive projection 922 and tube core adhesion coating 940 are similar to patterned conductive layer 110, conductive projection 122 and the tube core adhesion coating 140 of Fig. 1 in addition.Persons skilled in the art will be understood, and the encapsulation 200 of Fig. 2 also can be supported similar structures.

Figure 10 is the generalized section of a kind of semiconductor packages 1000 of embodiments of the invention.Semiconductor packages 1000 is similar to the semiconductor packages 800 that Fig. 8 describes, and difference is: primer 141 is adjacent to dielectric layer 118.Persons skilled in the art will be understood, and the encapsulation 200 of Fig. 2 also can be supported the flip-chip bonded with similar structures.

Figure 11 A to Figure 11 Y is the generalized section of manufacture method of a kind of semiconductor packages of embodiments of the invention.In order to present easily, following manufacture method is described in the encapsulation 200 that please refer to Fig. 2.Yet the manufacture method of expection can be carried out similarly with formation has other semiconductor elements encapsulation with encapsulation 200 different internal structures, for example is the encapsulation of explanation among Fig. 1 and Fig. 3-10.The manufacture method of expection also can be carried out the substrate strip (substratestrip) that comprises a plurality of continuous semiconductor packages arrays with formation similarly, and each substrate strip can correspondence for example be the encapsulation that illustrates among Fig. 1 and Fig. 3-10.Describe as Figure 11 Y, but the semiconductor packages array monomer that links to each other changes into a plurality of independently encapsulation, for example is Fig. 1-10 and encapsulation illustrated in fig. 12.

At first, please refer to Figure 11 A, carrier (carrier) 1100 is provided.In an embodiment, carrier 1100 comprises core layer (core layer) (not shown), and it is being attached between two carrier conductive layers (not shown) of core layer.Each carrier conductive layer can be by metal, metal alloy, wherein be dispersed with the matrix of metal or metal alloy, or another suitable electric conducting material forms.For example, each carrier conductive layer can comprise by copper or comprise the metal forming that the alloy of copper forms.Metal forming can have the thickness to the scope of about 30 μ m between about 10 μ m, for example be at about 15 μ m to the scope of about 25 μ m.

Carrier 1100 has according to upper surface 1102 and lower surface 1104.Conductive layer 1103 (conductive foil 1103) configuration is adjacent to upper surface 1102, and conductive layer 1105 (conductive foil 1105) configuration is adjacent to lower surface 1104.Each conductive layer 1103 and conductive layer 1105 can be by metals, metal alloy, wherein be dispersed with the matrix of metal or metal alloy, or another suitable electric conducting material forms.For example, conductive layer 1103 and 1105 can comprise by copper or comprise (releasable) metal forming that removes that the alloy of copper forms.Conductive layer 1103 and 1105 can be attached to carrier 1100 by release layer (not shown).In an embodiment, release layer is the adhesive layer (adhesive layer) that can be organic or inorganic, for example adhesive tape (tape).This adhesive tape (it can be embodied as one-sided or bilateral adhesive tape) is with relative to each other appropriate intervals fastening assembly, and the assembly that allows to be adjacent to carrier 1100 for configuration is carried out follow-up manufacturing operation.Each conductive layer 1103 and conductive layer 1105 can have the thickness to the scope of about 20 μ m between about 2 μ m, for example about 3 μ m to about 5 μ m, about 3 μ m to about 10 μ m, about 10 μ m to about 20 μ m and about 15 μ m to the scope of about 20 μ m.

Then, please refer to Figure 11 B, in an embodiment, barrier layer 1162 optionally disposes adjacent conductive layer 110, so conductive layer 1103 is between carrier 1100 and barrier layer 1162.Similarly, barrier layer 1164 optionally disposes adjacent conductive layer 1105, so conductive layer 1105 is between carrier 1100 and barrier layer 1164.Barrier layer 1162 can be considered etch stop layer with barrier layer 1164.Each barrier layer can be by metal, metal alloy, wherein be dispersed with the matrix of metal or metal alloy, or another suitable electric conducting material forms.For instance, each barrier layer can and/or comprise above-mentioned at least a kind of suitable alloy by tantalum, tungsten, chromium, nickel, gold, tin, lead-in wire.In embodiment, barrier layer can comprise nickel dam and contiguous gold layer or gold layer and contiguous nickel dam.In other embodiment, barrier layer can be formed by go between alloy and sn-ag alloy of tin.The formation method of each barrier layer comprises sputtering process, immersion method, galvanoplastic and/or known suitable method.The barrier layer 1162 and the barrier layer 1164 that are utilized among these embodiment can exist as for being removed among Figure 11 X always, please refer to following explanation.

Then, please refer to Figure 11 C, photo anti-corrosion agent material (photoresist material) can form and be adjacent to conductive layer 1103 and 1105.Perhaps, photo anti-corrosion agent material can form and be adjacent to barrier layer 1162 and 1164 (please refer to Figure 11 B).Photo anti-corrosion agent material can be dry film photoresist (dry filmphotoresist), or the patternable layer or the dielectric layer of another type.Photoresist layer 1106 and 1108 can form by coating, printing or any other proper technology.Photoresist layer 1106 and 1108 predetermined or selected part can comprise opening 1107a, 1107b that exposes dielectric layer 1103 and opening 1109a, the 1109b that exposes dielectric layer 1105 through photoimaging and development so that form opening.Can use photomask (photomask) (not illustrating) to define photoresist layer 1106 and 1108 in the photochemistry mode.Photoimaging (Photoimaging) or develop and be used for comparing the advantage of the process time that can have lower cost and shortening at photoresist layer 1106 and 1108 additive methods that form openings.The gained opening can have any one in some shapes, comprises cylindrical shape, for example circular cylinder shape, elliptical cylinder shape, square cylindrical shape, or rectangle cylindrical shape; Perhaps non-cylindrical shape is such as taper, infundibulate or another convergent shape.Also expect the flexible or roughly veining (textured) of horizontal boundary of gained opening.

Then, please refer to Figure 11 D, electric conducting material is applied in the opening, comprise by photoresist layer 1106 defined opening 1107a, 1107b and by photoresist layer 1108 defined opening 1109a, 1109b, to form from conductive layer 1103 vertically extending conducting blocks 1110 and from conductive layer 1105 vertically extending conducting blocks 1111.Perhaps, conducting block 1110 can be from barrier layer 1162 (please refer to Figure 11 B) vertical extent, and conducting block 1111 can be from barrier layer 1164 (please refer to Figure 11 B) vertical

extent.Conducting block

1110 and 1111 can be by metal, metal alloy, wherein be dispersed with the matrix of metal or metal alloy, or other suitable electric conducting materials form.For example, conducting

block

1110 and 1111 can comprise copper or comprise the one layer or more of the alloy of copper.Can use any one the

formation conducting block

1110 and 1111 in some paint-on techniques, for example chemical vapour deposition (CVD) (chemical vapor deposition), electroless-plating (electroless plating), metallide (electrolytic plating), printing, spin coating (spinning), spraying (spraying), sputter (sputtering) or vacuum moulding machine (vacuum deposition).

Then, please refer to Figure 11 E, can form at least one

barrier layer

1166 and 1168 and substitute the described barrier layer 1162 of previous Figure 11 B and

1164.Barrier layer

1166 and 1168 is considered as etch stop layer.Can form the 1110a of first of conducting block 1100.Barrier layer 1166 can see through sputtering method, immersion method, galvanoplastic and/or the contiguous 1110a of first of known suitable method configuration.The second portion 1110b of conducting block 1110 can form contiguous barrier layer 1166, so barrier layer 1166 can be between 1110a of first and second portion 1110b.Barrier layer 1168 can be formed between the 1111a of first and second portion 1111b of conducting block 1111 in a similar manner.Barrier layer 1166 can be similar to 1164 formation material to barrier layer 1162 to 1168 formation material, please refer to the explanation of above-mentioned Figure 11 B.

Then, please refer to Figure 11 F, peel off

photoresist layer

1106 and 1108 to expose conductive layer 1103 and 1105.Then, provide layer 1112.In embodiment, layer 1112 can be pre-formed a plurality of first opening 1112a are set, and the position at respectively corresponding these conducting block 1110 places of a plurality of parts of these first openings 1112a.Similar layer 1114 (please refer to Figure 11 G) of the opening with corresponding conducting block 1111 positions can be provided.In embodiment, layer 1112 comprises fiber reinforced resin material (fiber-reinforcedresin material), for example is the glue material, comprises glass 1190, comes reinforced layer 1112.Shown in Figure 11 F, glass 1190 is the horizontal plane configuration along layer 1112 at first.As these first openings 1112a, please refer to Figure 11 F, part extends through layer 1112.Among other embodiment of expection, these first openings 1112a also can extend fully through layer 1112.

Then, please refer to Figure 11 G, layer 1112 forms the part that is exposed that is adjacent to conducting block 1110 and conductive layer 1103.In embodiment, layer 1112 is corresponding and comprise dielectric layer 218, please refer to Fig. 2.Similarly, layer 1114 forms and to be adjacent to the part that conducting block 1111 and conductive layer 1105 are exposed out.

Layer

1112 and 1114 covers

conductive layer

1103 and 1105 in fact respectively, makes

conductive layer

1103 and 1105 be embedded in respectively in the layer 1112 and 1114.In an embodiment, layer 1112 can be by forming on each the upper surface 1120 that dielectric material is laminated to conducting block 1110 and on the expose portion of conductive layer 1103.Similarly, layer 1114 can by each the upper surface 1121 (putting upside down) that dielectric material is laminated to conducting block 1111 at manufacturing operation go up and the expose portion of conductive layer 1105 on form.In embodiment, pile up back glass 1190 at

layer

1112 and 1114 and be directed, along with the conducting block 1110 of contiguous vertical extent direction extension along conducting

block

1110 and 1111 and 1111 part, and respectively away from

conductive layer

1103 and 1105.

Through the dielectric material of lamination can (prepreg PP) makes to increase rigidity by fiber reinforced resin material and/or prepreg.Fiber can be glass fibre or Ke Weila fiber (Kevlar fibers) (nylon).Dielectric material through lamination can be formed by the film of strengthening with fiber.Can strengthen to be used for comprising that through the example of the resin material of the dielectric material of lamination Ajinomoto increases tunic (Ajinomotobuild-up film by fiber, ABF), Bismaleimide Triazine (bismaleimide triazine, BT), polyimides (polyimide, PI), liquid crystal polymer (liquid crystal polymer, LCP), epoxy resin, and other resin materials.Resin material can be partly solidified.In an embodiment, through the dielectric material of lamination through preforming to define opening corresponding to the position of conducting block 1110 or conducting block 1111.

Perhaps,

layer

1112 and 1114 can be formed by unstrengthened material of more not having rigidity, such as solder mask (solder resist), include, but is not limited to the resin material that aginomoto (Ajinomoto) increases tunic (ABF), Bismaleimide Triazine (BT), polyimides (PI), liquid crystal polymer (LCP) and epoxy resin, or the patternable layer or the dielectric layer of another type.Can use in some paint-on techniques any one to apply this material, such as printing, spin coating or spraying.

Layer

1112 and 1114 is then covered by

conductive layer

1116 and 1117

respectively.Conductive layer

1116 and 1117 can be formed by the material with the materials similar that is used to form conductive layer 1103 and 1105.In the

conductive layer

1116 and 1117 each can have the thickness to the scope of about 20 μ m between about 10 μ m, for example at about 10 μ m to the scope of about 15 μ m.

Then, please refer to Figure 11 H, for example lose the part that (flash etching) removes each

conductive layer

1116 and 1117, to form conductive layer 1122 and 1123 by dodging.Each conductive layer 1122 and 1123 can have the thickness to the scope of about 10 μ m between about 3 μ m, for example at about 3 μ m to the scope of about 7 μ m.

Then, please refer to Figure 11 I, the opening 1124a of formation exposed surface 1112 and 1124b are to form conductive layer 1128 in conductive layer 1122.Similarly, in conductive layer 1123, form the opening 1126a of exposed surface 1114 and 1126b to form conductive layer 1129.The opening 1124 and 1126 width that can have respectively of expection less than conducting block 1110 and 1111.Perhaps, opening 1124 and 1126 can have the width that is equal to conducting

block

1110 and 1111 in fact respectively.In embodiment, patternable

conductive layer

1128 and 1128 part (not illustrating) have formed the part of at least one ground plane 1250 (please refer to Figure 12 and 13).In can be in a number of ways any one carried out patterning with

cambium layer

1128 and 1129, such as chemical etching, laser drill or machine drilling, and the gained opening can have in some shapes any one, such as cylindrical shape, such as circular cylinder shape, elliptical cylinder shape, square cylindrical shape, or the rectangle cylindrical shape; Perhaps non-cylindrical shape is such as taper, infundibulate or another convergent shape.Also expect the flexible or roughly veining of horizontal boundary of gained opening.

Then, please refer to Figure 11 H, the opening 1130a of formation exposure conducting block 1110 and 1130b are with cambium layer 1134 in layer 1112.Similarly, in layer 1114, form to expose the opening 1132a of conducting block 1111 and 1132b with cambium layer 1136.The opening 1130 and 1132 of expection can be distinguished the size (please refer to Figure 11 I) of corresponding opening 1124 and 1126.In embodiment, patternable layer 1112 and a plurality of parts of 1114 are to expose the conducting block that is positioned at ground plane 1250 (please refer to Figure 12 and 13) below.In can be in a number of ways any one carried out patterning with cambium layer 1134 and 1136, such as laser drill, plasma etching or plasma clean, and the gained opening can have in some shapes any one, such as cylindrical shape, such as circular cylinder shape, elliptical cylinder shape, square cylindrical shape, or the rectangle cylindrical shape; Perhaps non-cylindrical shape is such as taper, infundibulate or another convergent shape.Also expect the flexible or roughly veining of horizontal boundary of gained opening.In an embodiment, one of in the opening 1130 and 1132 or many persons (such as opening 1130b and the 1132b among Figure 11 J) can be in fact respectively with respect to the corresponding person in conducting block 1110 and 1111 and placed in the middle.Alternatively or in addition, one of in the opening 1130 and 1132 or many persons (such as opening 1130a and the 1132a among Figure 11 J) can be in fact respectively with respect to the corresponding person in conducting block 1110 and 1111 and off-center.

Then, please refer to Figure 11 K, metal material configuration adjacent conductive layer 1128 and conducting block 1110 are to form Seed Layer 1180.Sibling species sublayer 1181 configuration adjacent conductive layer 1129 and conducting block 1111.In embodiment, Seed Layer 1180 can be filled in opening 11130 in fact, so the part of Seed Layer 1180 formation conduction bare patch, for example is conductive projection 222a and the 222b of Fig. 2.Similarly, Seed Layer 1181 can be filled in opening 1132 in fact, so a plurality of parts formation conductive projections of Seed Layer 1181, for example is conductive projection 1137a and 1137b.(corresponding to the similar conductive projection 1137a and the 1137b of semiconductor packages are illustrated on the opposite side of carrier 1100 separately.) or, Seed Layer 1180 can be partially filled in opening 1130, so a plurality of parts of Seed Layer 1180 form the conductive projection 222a of Fig. 2 and the first of 222b.Seed Layer 1181 can be partially filled in opening 1132, so a plurality of parts of Seed Layer 1181 form the first of conductive projection 1137a and 1137b.In embodiment, conductive projection (not illustrating) can be formed at ground plane 1250 (please refer to Figure 12 and 13) and between the conducting block below the ground plane 1250.Metal material can have and the characteristic that is used to form the materials similar of conducting

block

1110 and 1111, for example copper or copper

alloy.Seed Layer

1180 and 1181 can be used any one in some paint-on techniques and form, and for example is electroless-plating.

In an embodiment, conductive projection 222a with respect to the off-centered location of conducting block 1110 corresponding to the second contact mat 230a shown in Figure 2 lateral displacement with respect to conductive projection 222a.Conductive projection 222b with respect to the location placed in the middle of conducting block 1111 corresponding to conductive projection 222b shown in Figure 2 location placed in the middle with respect to the second contact mat 230b.

Then, please refer to Figure 11 L, form the

photoresist layer

1138 and 1139 of

contiguous Seed Layer

1180 and 1181

respectively.Photoresist layer

1138 and 1139 predetermined or selected part can be through photoimaging and development so that

form opening

1140 and 1141 respectively.Opening 1140 exposes Seed Layer 1180, and opening 1141 exposes Seed Layer 1181.Photoresist layer 1138 and 1139 (and opening 1140 and 1141) has and similar characteristic of the photoresist layer of describing referring to Figure 11 C 1106 and 1108 (and opening 1107 and 1109) and similar generation type.

Then, please refer to Figure 11 M, the metal material configuration is adjacent to

Seed Layer

1180 and 1181 not by

photoresist layer

1138 and 1139 parts that covered, to form conductive layer 1142 and 1144.In embodiment,

conductive layer

1142 and 1144 is respectively adjacent to conductive projection 222 and 1137.Perhaps,

conductive layer

1142 and 1144 part can form the second portion of conductive projection 222 and 1137 respectively.Contiguous described conductive projection 222 of previous Figure 11 K of conductive projection 222 and 1137 second portion and 1137 first.Metal material can have and the characteristic that is used to form the materials similar of conducting

block

1110 and 1111, for example copper or copper alloy.Conductive projection 222 and 1137 and

conductive layer

1142 and 1144 can use any one in some paint-on techniques and form, metallide for example.

Then, please refer to Figure 11 N, peel off

photoresist layer

1138 and 1139 to expose the extra section of

Seed Layer

1180 and 1181.

In an embodiment, extra photoresist can be configured to be adjacent to conductive layer 1142, and wherein the photoresist definition is corresponding to the opening of the position of the opening 711 in the encapsulation 700 of Fig. 7.The part of conductive layer 1142 can be through removing to form opening 711.In addition, the part of each conductive projection 222 can be through removing to form groove 723 (please refer to Fig. 7).Removing of these parts of conductive layer 1142 can be carried out via chemical etching, laser drill or machine drilling.Opening 711 and groove 723 (please refer to Fig. 7) have and characteristic like the property class of before having described at opening 1124 and 1126 (seeing Figure 11 I).Then, removable extra photoresist with expose conductive layer 1142 ', shown in Figure 11 O.

Then, please refer to Figure 11 P to Figure 11 Y and follow Figure 11 N, but persons skilled in the art will understand, similar step can be followed Figure 11 O.

Then, please refer to Figure 11 P, removing the part of each

conductive layer

1128 and 1129 and the part of

Seed Layer

1180 and 1181, for example is to see through fast-etching (flash etching), to form similar in appearance to the patterned conductive layer of the patterned conductive layer 210 of Fig. 2.Patterned conductive layer 210 comprises the part 1182a and the 1182b of Seed Layer 1180, the contiguous conductive projection 222 of patterned conductive layer 210 configurations.(the similar patterned conductive layer 1146 corresponding to independent semiconductor packages is illustrated on the opposite side of carrier 1100.) in embodiment, can comprise ground plane 1250 (please refer to Figure 12 and 13) similar in appearance to the patterned conductive layer of the patterned conductive layer of Fig. 2.

Then, please refer to Figure 11 Q,

form dielectric layer

1148 and 1149 parts with difference overlay pattern conductive layer 210 and 1146.The part that comprises second contact mat 226 of dielectric layer 1148 exposure pattern conductive layers 210.

Dielectric layer

1148 and 1149 can be formed by the dielectric material of solder resist (solder mask) or another type.

Then, please refer to Figure 11 R, patterned

conductive layer

210 and 1146 rest parts are not covered by

dielectric layer

1148 and 1149 respectively, but can be covered by the electrodeposited coating of the electrodeposited coating 227 of similar Fig. 2.(the similar electrodeposited coating 1150 corresponding to independent semiconductor packages is illustrated on the opposite side of carrier 1100.)

electrodeposited coating

227 and 1150 can by tin, nickel and gold or comprise tin or comprise nickel and the alloy of gold at least one form.

Then, please refer to Figure 11 S, remove carrier 1100 to expose the conductive layer 1103 of substrate 1152.(conductive layer 1105 of another substrate also exposes by removing carrier 1100.This does not illustrate in Figure 11 S.) substrate 1152 comprises a plurality of adjacent substrates unit, it for example is similar to the base board unit 104 of (but being not limited to) Fig. 1 or the base board unit 204 of Fig. 2.

As described in Figure 1A, conductive layer 1103 can have the thickness 1172 between 15 μ m to 20 μ m.Conductive layer 1103 can be reduced in the scope of 3 μ m to 10 μ m through the thickness 1172 of chemical etching with conductive layer 1103, for example is from 3 μ m to 8 μ m.The reason of etching conductive layer 1103 is can effectively reduce the warpage of substrate 1152 between the thickness of 3 μ m to 8 μ m, and can increase the reliability of utilizing substrate 1152 to make encapsulation.The thickness of conductive layer 1103 is greater than or less than the warpage that this scope can cause substrate 1152.

Then, please refer to Figure 11 T, in an embodiment, strutting piece 1170 can optionally dispose adjacent conductive layer 1103, so conductive layer 1103 is between conducting block 1110 and strutting piece 1170.During the making of substrate 1152, reach assembling and comprise when substrate 1152 (please refer to Figure 11 W to 11Y) encapsulates, attach strutting piece 1170 to substrate 1152 and also can effectively reduce the warpage of substrate 1152, and then can increase the reliability of utilizing 1152 making of machine substrate to encapsulate.In embodiment, strutting piece can by polyethylene terephthalate (polyethylene terephthalate, PET), metal, epoxy resin, double-deck copper foil lamination and known suitable material.

Then, please refer to Figure 11 U, the previous described barrier layer 1162 of Figure 11 B optionally is disposed between conducting block 1110 and the conductive layer 1103.

Then, please refer to Figure 11 V, the previous described barrier layer 1166 of Figure 11 E optionally is disposed between the 1110a of first and second portion 1110b of conducting block 1110.

Then, please refer to Figure 11 W, one or more tube core 102 is electrically connected to substrate 1152 and is electrically connected to conductive layer 1103.Tube core 102 can be electrically connected to conductive layer 1103 via bonding wire 136.Perhaps, tube core (tube core 302 shown in Fig. 3,5,8 and 10) can be electrically connected to conductive layer 1103 via flip-chip bonded.Tube core 102 can be attached to substrate 1152 by tube core adhesion coating 140.Form molded structure 1154 to coat tube core 102.In embodiment, optionally support component 1170 (please refer to Figure 11 T) is removable to expose conductive layer 1103.

Then, please refer to Figure 11 X, can for example remove conductive layer 1103, with exposed dielectric layer 1156 via chemical etching and/or fast-etching.After removing conductive layer 1103, can for example remove the part of conducting block 1110 (seeing Figure 11 E), to form second contact mat 230 and the circuit 249 of Fig. 2 via chemical etching.Advantageously, the surface of dielectric layer 1156 and conducting block 1110 can be by conductive layer 1103 protections to prevent to be exposed to environmental condition.Can be by after attached and coating tube core 102, removing the duration that conductive layer 1103 prolongs this protection.In an embodiment, can be considered protective cover at described barrier layer 1162 of Figure 11 B and the described barrier layer 1166 of Figure 11 E, in order to avoid transition etching conducting block 1110, therefore second contact mat 230 has minimum at least required thickness with circuit 249.In another embodiment, after etching conductive layer 1103, barrier layer 1162 and barrier layer 1166 can utilize and remove barrier layer 1162 and barrier layer 1166 and chemical etching that the etching solution of harmless second contact mat 230, circuit 249 and dielectric layer 1156 is selected.

At last, please refer to Figure 11 Y, comprise that the dielectric layer of the dielectric layer 228 of Fig. 2 can make dielectric layer 228 expose second contact mat 230 through forming and patterning.Can then carry out singulation step, to obtain a plurality of independently semiconductor packages, for example semiconductor packages 200 of Fig. 2 separately along dotted line 1158 and 1160.The electrical contact of all electrical contacts 133 as shown in Figure 1 can be configured in before or after the singulation on second contact mat 230.

The patterned conductive layer 110 that persons skilled in the art should be appreciated that Fig. 1 and the patterned conductive layer 210 of conductive projection 122, Fig. 2 and conductive projection 222 and the counter structure in Fig. 3-10 encapsulation can comprise the part of Seed Layer, for example are the Seed Layer 1180 that is included in the encapsulating structure described in Figure 11 Y.

Figure 12 is the generalized section of a kind of semiconductor packages 1200 of embodiments of the invention.Semiconductor packages 1200 is similar to the semiconductor packages 100 that Fig. 1 describes, and difference is: semiconductor packages 1200 comprises ground plane 1250, and it is disposed between dielectric layer 124 and the dielectric layer 118.Ground plane 1250 comprises and is by being constituted with patterned conductive layer 1240 same materials, for example with the formation of the patterned conductive layer 110 of Fig. 1.Ground plane 1250 can be used as dual heat radiation purpose and can provide tube core 102 to be electrically connected to ground connection.Tube core 102 can see through bonding wire 136 and be electrically connected to ground plane 1250.Ground plane 1250 sees through conductive projection 122 and electrically connects outside electrical contact 133.The heat of encapsulation 1200 can see through outside electrical contact 133 disperses, and for example is to be positioned under the printed circuit board (PCB).One or more outside electrical contact 133 can provide and be electrically connected to ground connection.Perhaps, external connector 133 can only be considered as heat radiation function.Persons skilled in the art will be understood, and the encapsulation of lead-in wire embodiment also can be supported has similar structure.

Figure 13 is the schematic top plan view of the semiconductor packages 1200 of Figure 12.This schematic top plan view presents the structure of ground plane 1250.In embodiment, ground plane 1250 is a mesh shape, and the opening that it defines a plurality of two-dimensional lattice patterns please refer to Figure 13.These openings can have same size in fact, and can have uniform spacing in fact, please refer to Figure 13.Or opening can be of different sizes and can have uniform spacing (for instance, in an embodiment, some opening is bigger, and some opening is less).The ground plane 1250 of net-like pattern can provide preferred reliability compared to the interface of ground plane 1250 between dielectric layer 124 (as welding resisting layer) and ground plane 1250 of other patterns.

Perhaps, ground plane 1250 can be tight plane, annular patterns or/with strip pattern.Annular patterns can comprise single ring, maybe can comprise a plurality of rings, and it has a plurality of being opened between the various rings.A plurality of rings can be the concentric ring of different size, and ring can be essentially circle.Strip pattern can comprise that a plurality of first sides from ground plane 1250 extend to the bar of the second side of ground plane 1250, and has a plurality of openings between bar.Bar can be parallel in fact.Bar can have identical length in fact, maybe can have different length.

Though Fig. 1 to Figure 13 illustrate encapsulation comprise one-sided substrate with in be embedded in electrical conductive projection in the one-sided substrate, the substrate of the semiconductor packages of expection, usually, can comprise a plurality of dielectric layers, each dielectric layer comprise have a plurality of conductive projections in bury group (or, particularly, electrical conductive hole).The substrate that comprises a plurality of dielectric layers can be supposed to, and for instance, can consider the flexibility of circuit in the encapsulation with relative complex circuit.When the cost of controlling packaging technology and complexity, electrically conductive projection can be utilized with effective reduction package dimension and package area.In other embodiment, can comprise that the dielectric layer that buries electrical conductive projection respectively in a plurality of is to handle multiple electrical distribution to increase structural strength and structure reliability.

Though describe the present invention with reference to specific embodiment of the present invention, persons skilled in the art should be appreciated that, under the situation that does not depart from the true spirit of the present invention that defines as claim and category, can make various variations and replaceable various equivalent.In addition, can make many modifications so that particular condition, material, material component, method or technology are suitable for purpose of the present invention, spirit and category.All these type of modifications are intended in the category of the claim that invests this.Specific, though describe the method that this paper discloses with reference to the specific operation of carrying out with certain order, will understand, under the situation that does not depart from teaching of the present invention, these operations are capable of being combined, segment or again sequencing with the formation equivalent processes.Therefore, unless this paper clearly indicate, otherwise the operation order and the grouping be not limitation of the present invention.

Claims

1. semiconductor packages comprises:

Base board unit comprises:

First patterned conductive layer has upper surface;

First dielectric layer is disposed at this upper surface of this first patterned conductive layer, and this first dielectric layer exposes the part of this first patterned conductive layer to form a plurality of first contact mats;

Second patterned conductive layer is positioned at the below of this first patterned conductive layer and has lower surface;

Second dielectric layer, between this first patterned conductive layer and this second patterned conductive layer, wherein this second dielectric layer defines and a plurality ofly extends to the opening of this second patterned conductive layer from this first patterned conductive layer, and this second patterned conductive layer comprises a plurality of second contact mats that exposed by this second dielectric layer; And

A plurality of conductive projections, each conductive projection extends to one second corresponding contact mat via an opening of the correspondence that is arranged in this second dielectric layer from this first patterned conductive layer, each conductive projection is filled in an opening of the correspondence that is arranged in this second dielectric layer, and wherein at least one conducting block defines groove;

Tube core electrically connects this a plurality of first contact mats; And

Package main body covers this first patterned conductive layer and this tube core.

2. semiconductor packages as claimed in claim 1, wherein:

Each conductive projection has upper surface that has first area and the lower surface that has second area; And

Each second contact mat has the upper surface that has the 3rd area;

Wherein this first area is greater than this second area, and the 3rd area is greater than this second area.

3. semiconductor packages as claimed in claim 1, wherein:

This second dielectric layer has lower surface; And

This lower surface of this second patterned conductive layer is recessed into this lower surface in this second dielectric layer.

4. semiconductor packages as claimed in claim 1, wherein:

This first patterned conductive layer comprises ground plane, and this ground plane is between this first dielectric layer and this second dielectric layer;

At least one opening that is defined via this second electricity layer extends to second patterned conductive layer from this ground plane; And

At least one conductive projection extends at least one second contact mat via at least one opening in this second dielectric layer from this ground plane.

5. semiconductor packages as claimed in claim 4, wherein this ground plane comprises reticular part.

6. semiconductor packages as claimed in claim 4, wherein:

This tube core sees through this ground plane and at least one conductive projection and is electrically connected at least one second contact mat, is electrically connected to ground connection so that this tube core to be provided, to promote the heat radiation of this semiconductor packages.

7. semiconductor packages as claimed in claim 1, wherein this tube core flip-chip bonded is in these a plurality of first contact mats.

8. semiconductor packages as claimed in claim 7, wherein this tube core sees through and a plurality ofly to extend through the fusion conductive projection of this first dielectric layer and be electrically connected to this a plurality of first contact mats.

9. semiconductor packages as claimed in claim 7, wherein this tube core sees through a plurality of fusion conductive projections and is electrically connected to this a plurality of first contact mats, and wherein the part of at least one fusion conductive projection is filled in this groove.

10. the manufacture method of a substrate comprises:

Carrier is provided, has upper surface and lower surface, and contiguous this carrier should above on be formed with the first metal layer;

Form a plurality ofly from vertically extending first conducting block of this first metal layer, each first conducting block has upper surface;

Formation defines first dielectric layer of a plurality of openings, and each first opening exposes the part of this upper surface of first conducting block of at least one correspondence;

Form a plurality of first conductive projections and first patterned conductive layer, each first conductive projection extends to this first patterned conductive layer from one first conducting block of correspondence, and is filled in one the first corresponding opening; And

Remove this carrier, to expose this first metal layer.

11. the manufacture method of substrate as claimed in claim 10 also is included in and removes after this carrier, removes the part of this first metal layer.

12. the manufacture method of substrate as claimed in claim 10, wherein this first metal layer comprises the barrier layer of metal forming and contiguous this metal forming, and these a plurality of first conducting blocks extend perpendicularly to this barrier layer.

13. the manufacture method of substrate as claimed in claim 10, wherein second metal level is formed at this lower surface of contiguous this carrier, and also comprises:

Form a plurality ofly from vertically extending second conducting block of this second metal level, each second conducting block has lower surface;

Formation defines second dielectric layer of a plurality of second openings, and each second opening exposes the part of this lower surface of one second corresponding conducting block;

Form a plurality of second conductive projections and second patterned conductive layer, each second conductive projection extends to this second patterned conductive layer from one second conducting block of correspondence, and is filled in one the second corresponding opening; And

Remove this carrier, to expose this second metal level.

14. the manufacture method of substrate as claimed in claim 10 comprises that also a part that removes these a plurality of first conducting blocks is to form a plurality of contact mats that are electrically connected in order to the outside.

15. the manufacture method of substrate as claimed in claim 10 wherein forms this first dielectric layer and comprises:

Configuration covers the dielectric layer of this first metal layer and these a plurality of first conducting blocks, and wherein this dielectric layer is between second metal level and this a plurality of first conducting blocks;

This second metal level of patterning is to expose a plurality of parts of this dielectric layer; And

Remove these a plurality of parts that this dielectric layer is exposed out, to form these a plurality of first openings.

16. the manufacture method of a semiconductor packages comprises:

Substrate is provided, comprises:

Metal level;

A plurality of conducting blocks form and are adjacent to metal level, and each conducting block has upper surface;

Dielectric layer defines a plurality of openings, and each opening exposes the part of this upper surface of a corresponding conducting block;

Patterned conductive layer; And

A plurality of conductive projections, each conductive projection extends to this patterned conductive layer from a conducting block of correspondence, and is filled in the corresponding opening;

Electrically connect tube core to this patterned conductive layer;

Form package main body, cover this dielectric layer and this tube core; And

Remove this metal level to expose this a plurality of conducting blocks.

17. the manufacture method of semiconductor packages as claimed in claim 16, wherein this metal level comprises:

Metal forming; And

Barrier layer, contiguous this metal forming and between this metal forming and this a plurality of conducting blocks.

18. the manufacture method of semiconductor packages as claimed in claim 17 wherein removes this metal level and comprises:

Remove this metal forming to expose this barrier layer; And

Remove this barrier layer to expose this a plurality of conducting blocks.

19. the manufacture method of semiconductor packages as claimed in claim 16 wherein provides this substrate to comprise:

Provide carrier, and this metal level forms this upper surface that is adjacent to this carrier with upper surface and lower surface;

Form the upper surface vertical extent of these a plurality of conducting blocks from this metal level, each conducting block has upper surface;

Form this dielectric layer, this dielectric layer defines this a plurality of openings, and each opening exposes the part of this upper surface of a corresponding conducting block;

Form these a plurality of conductive projections and this patterned conductive layer, each conductive projection extends to this patterned conductive layer from this upper surface of a conducting block of correspondence, and is filled in the corresponding opening; And

Remove this carrier, to expose the lower surface of this metal level fully.

20. the manufacture method of semiconductor packages as claimed in claim 19 wherein forms this patterned conductive layer and comprises:

Form first conductive layer of contiguous these a plurality of conducting blocks;

Form the patterning dry film of contiguous first conductive layer;

Form second conductive layer of contiguous this first conductive layer;

Formation extends through the groove of this second conductive layer at least, and this groove is connected with a corresponding conducting block; And

Be disposed at this dielectric layer of this patterned conductive layer, the part of this dielectric layer is filled in this groove.