TW201507084A - Semiconductor package with single sided substrate design and manufacturing methods thereof - Google Patents

Abstract

A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity.

Description

Semiconductor package with single-sided substrate design and method of fabricating the same

The present invention relates to a semiconductor device package and a method of fabricating the same, and more particularly to a semiconductor device package having a single-sided substrate design and a method of fabricating the same.

Integrated circuit (IC) packaging technology plays an important role in the electronics industry. As lightness, tightness, and high efficiency have become typical requirements for consumer electronic components and communication products, wafer packages should provide excellent electrical characteristics, small overall volume, and large amounts of I/O. The substrates used in such wafer packages often have multiple metal layers that can be electrically connected using traces and/or vias. As the size of the wafer package is reduced, the lines and vias used to connect the plurality of metal layers can be made smaller and more closely spaced, which can increase the cost and complexity of the integrated circuit packaging process. Therefore, there is a need to develop a substrate which has a thin configuration, is manufactured by a relatively complicated process, is suitable for mass production, and can be produced at a high production yield. There is also a need to develop a corresponding package including the substrate, and a method of manufacturing the substrate and the corresponding package.

It is against this prior art that the semiconductor package and related methods described herein need to be developed.

One aspect of the invention is related to a semiconductor package. In an embodiment, half The conductor package includes a substrate unit, a die, and a package body. The substrate unit comprises: (1) a first patterned conductive layer having an upper surface; (2) a first dielectric layer disposed on an upper surface of the first patterned conductive layer, the first dielectric layer exposing the first a portion of the patterned conductive layer to form a plurality of first contact pads; (3) a second patterned conductive layer under the first patterned conductive layer and having a lower surface; (4) a first patterned conductive a second dielectric layer between the layer and the second patterned conductive layer, wherein the second dielectric layer defines a plurality of openings extending from the first patterned conductive layer to the second patterned conductive layer, and wherein the second pattern The conductive layer includes a plurality of second contact pads exposed by the second dielectric layer; and (5) a plurality of conductive bumps, each of the conductive bumps passing through a corresponding one of the openings in the second dielectric layer A patterned conductive layer extends to a corresponding one of the second contact pads, and each of the conductive bumps is filled in a corresponding one of the openings in the second dielectric layer. At least one of the conductive bumps defines a recess. The die is electrically connected to the first contact pad. The package body covers the first patterned conductive layer and the die.

Another aspect of the invention is directed to a method of making a substrate. In an embodiment, the method comprises: (1) providing a carrier having an upper surface and a lower surface, and forming a first metal layer adjacent to an upper surface of the carrier; (2) forming a plurality to the first a first conductive block extending vertically from the metal layer, each of the first conductive blocks having an upper surface; (3) forming a first dielectric layer defining a plurality of first openings, each of the first openings exposing a corresponding one a portion of the upper surface of the first conductive block; (4) forming a first conductive bump and a first patterned conductive layer, each of the first conductive bumps extending from the corresponding one of the first conductive blocks to the first patterning a conductive layer filled in a corresponding one of the first openings; and (5) removing the carrier to expose the first metal layer.

Another aspect of the present invention is directed to a method of fabricating a semiconductor package. In one embodiment, the method comprises: (1) providing a substrate comprising (a) a metal layer; (b) a plurality of conductive blocks forming adjacent metal layers, each conductive block having an upper surface; a dielectric layer defining an opening, each opening exposing a surface of a corresponding one of the conductive blocks a portion of (d) a patterned conductive layer; and (e) a plurality of conductive bumps, each conductive bump extending from a corresponding one of the conductive bumps to the patterned conductive layer and filled in a corresponding opening; (2) Electrically connecting a wafer to the patterned conductive layer; (3) forming a package body covering the dielectric layer and the die; and (4) removing the metal layer to expose the conductive block.

Other aspects and embodiments of the invention are also contemplated. The above summary and the following detailed description are not intended to be construed

100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1200‧‧‧ semiconductor packaging

102, 302‧‧‧ grain

104, 204‧‧‧ substrate unit

106‧‧‧Package body

110, 210, 610, 710, 810, 910, 1146, 1210‧‧‧ patterned conductive layers

112, 142, 146, 1102, 1120, 1121‧‧‧ upper surface

114, 1110, 1111‧‧‧ conductive blocks

116, 134, 144, 234, 1104‧‧‧ lower surface

118, 124, 218, 228, 424, 524, 624, 724, 1148, 1149, 1156‧‧ dielectric layers

120, 402, 502, 611, 711, 811, 911, 1107a, 1107b, 1109a, 1109b, 1124a, 1124b, 1126a, 1126b, 1130a, 1130b, 1132a, 1132b, 1140, 1141‧‧

122, 122a, 222a, 222b, 622, 722, 822, 922, 1137a, 1137b‧‧‧ conductive bumps

126, 226a, 226b‧‧‧ first contact pads

130, 130a, 230, 230a, 230b‧‧‧ second contact pads

133‧‧‧Electrical contacts

136‧‧‧welding line

138‧‧‧Active surface

140, 940‧‧‧ die adhesion layer

141‧‧‧Bottom glue

148, 248b, 249‧‧‧ lines

150‧‧‧ thickness

214, 1103, 1105, 1116, 1117, 1122, 1123, 1128, 1129, 1142, 1142', 1144‧‧‧ conductive layer

227, 1150‧‧‧ surface treatment layer / plating

335‧‧‧fused conductive bumps

723, 823, 923 ‧ ‧ grooves

1100‧‧‧carrier

1106, 1108, 1138, 1139‧‧‧ photoresist layer

1112, 1114, 1134, 1136‧‧ layers

1152‧‧‧Substrate

1154‧‧‧Molded structure

1158, 1160‧‧‧ dotted line

623‧‧‧ Groove

1162, 1164, 1166, 1168‧‧‧ barrier layers

1110a, 1111a‧‧‧ Part 1

1110b, 1111b‧‧‧ Part II

1190‧‧‧glass fiber

1112a‧‧‧first opening

1180, 1181‧‧ seed layer

Section 1182a, 1182b‧‧‧

1172‧‧‧ thickness

1250‧‧‧ Grounding layer

1 is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention.

2 is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention.

3 is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention.

4 is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention.

5 is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention.

6 is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention.

7 is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention.

FIG. 8 is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention.

9 is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention.

10 is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention.

11A-11Y are cross-sectional views showing a method of fabricating a semiconductor package in accordance with an embodiment of the present invention.

12 is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention.

13 is a top plan view of the semiconductor package of FIG.

For a better understanding of the nature and purpose of the embodiments of the invention, reference should be In the drawings, the same reference numerals are used to refer to the

First, please refer to FIG. 1 , which is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. The semiconductor package 100 includes a die 102, a substrate unit 104, and a package body 106. The substrate unit 104 includes a patterned conductive layer 110 having an upper surface 112 and one or more conductive bumps 114 having a lower surface 116. The patterned conductive layer 110 extends laterally within the substrate unit 104. The substrate unit 104 also includes a dielectric layer 118 interposed between the patterned conductive layer 110 and the conductive bumps 114. Dielectric layer 118 has a lower surface 134. Dielectric layer 118 defines a plurality of openings 120 that extend from patterned conductive layer 110 to conductive bumps 114. Each of the conductive bumps 122 extends from the patterned conductive layer 110 to a corresponding one of the conductive blocks 114 via a corresponding one of the openings 120. The conductive bumps 122 may also be formed as the same conductive layer, such as a sub-layer (please refer to FIG. 11K). Alternatively, the conductive bumps 122 may also include a first portion formed as a same conductive layer, such as a sub-layer (please refer to FIG. 11K) and a second portion formed on the seed layer (please refer to FIG. 11M). At least a portion of the first portion of the conductive bump 122 can be disposed between the second portion of the conductive bump 122 and the conductive bump 114. In an embodiment, each of the conductive bumps 122 is substantially filled in a corresponding one of the openings 120. The substrate unit 104 further includes a dielectric layer 124 having a secondary dielectric layer 124 disposed on the upper surface 112 of the patterned conductive layer 110. Dielectric layer 124 can be a solder mask. Dielectric layer 124 exposes a portion of patterned conductive layer 110 to form a plurality of first contact pads 126. In an embodiment, such as in wire bonding applications, the first contact pads 126 may be external to the footprint of the die 102. Alternatively, for example, in a flip-chip bonding application, the first contact pad 126 can be located below the die 102. In an embodiment, the first contact pad 126 can be covered by a surface finish layer (not shown).

In an embodiment, the dielectric layer 118 exposes the lower surface 116 of the conductive bumps 114 to form a plurality of second contact pads 130. The second contact pad 130 can be used for external electrical connection to the package 100, such as to another semiconductor package or to other components on the circuit board. For example, an electrical contact 133, such as a solder ball, can be electrically connected to and configured adjacent to a corresponding one. The second contact pad 130.

In one embodiment, each of the conductive bumps 122 has a height ranging from about 30 μm to about 150 μm, such as from about 30 μm to about 50 μm, from about 30 μm to about 100 μm, from about 50 μm to about 100 μm, and from about 100 μm to about 150 μm. Each of the conductive bumps 122 may have a diameter in the range of about 150 μm to 250 μm, for example, a diameter of about 200 μm. Each of the conductive bumps 122 has an upper surface 142 having a first area and a lower surface 144 having a second area. In an embodiment, the first area is greater than the second area. Additionally, the upper surface 146 of each second contact pad 130 has a third area. The diameter of the second contact pad 130 can vary from about 150 [mu]m to about 300 [mu]m. Thus, in an embodiment, the third area is greater than the second area. Alternatively, the third area may also be less than or equal to the second area. In an embodiment, the upper surface 142 and the lower surface 144 of the conductive bump 122 may have a shape including, but not limited to, a substantially circular shape, a substantially elliptical shape, a substantially square shape, and a substantially rectangular shape. shape.

In an embodiment of the invention having a single-sided substrate design, the conductive bumps 122 electrically connect the patterned conductive layer 110 to the second contact pad 130 without the need for vias, such as plated vias. This can significantly reduce the cost of the package 100. Additionally, some of the conductive bumps 122 (eg, conductive bumps 122a that are at least partially disposed below the die, as described below) may facilitate thermal conduction away from the die 102 and exit the package 100. Moreover, the second contact pad 130 can be buried in the dielectric layer 118, which can increase the mounting reliability of the package 100 because the stress concentration is reduced.

In one embodiment, the lower surface 116 of the conductive bump 114 is recessed into the lower surface 134 of the dielectric layer 118 such that the second contact pad 130 is recessed into the lower surface 134. The recess of the second contact pad 130 to the lower surface 134 may facilitate attachment of the electrical contact 133 to the second contact pad 130. Alternatively, the lower surface 116 of the conductive bump 114 can be exposed at the lower surface 134 of the dielectric layer 118.

In an embodiment, the package 100 has a thickness 150 ranging from about 200 μm to about 500 μm, such as from about 200 μm to about 350 μm, from about 300 μm to about 350 μm, about 300 μm to about 400 μm, about 300 μm to about 450 μm, and about 300 μm to about 500 μm, but the thickness of the package 100 is not limited to this range.

In one embodiment, the bond pads on the active surface 138 of the die 102 are electrically connected to the first contact pads 126 via bond wires 136. The first contact pad 126 is disposed around the die 102 and may completely or partially surround the die 102. The package body 106 substantially covers or encapsulates the die 102, bond wires 136, and the first patterned conductive layer 110 to provide mechanical stability and protection against oxidation, moisture, and other environmental conditions. The package body 106 may be made of a molding material, and the molding material may include, for example, a Novolac-based resin, an epoxy-based resin, or a silicone-based resin. Resin), other suitable packages. A suitable filler such as powdered cerium oxide (SiO ₂ ) may also be contained.

In one embodiment, the die 102 is disposed adjacent to the dielectric layer 124, a portion of which can serve as a die pad. The die attach layer 140 is formed of a die bonding material, such as an adhesive or film, which is selectively added between the die 102 and the dielectric layer 124. The die attach layer 140 may comprise an epoxy resin, a resin, or other suitable material.

The single-sided substrate, such as substrate unit 104, often has a single metal layer (e.g., patterned conductive layer 110). Within this single metal layer, wiring can be routed to obtain a fan-in configuration, a fan-out configuration, or a combination of both. In one embodiment, the patterned conductive layer 110 can include a line 148 that electrically connects each of the first contact pads 126 to a corresponding one of the conductive bumps 122 and is electrically connected to the corresponding second contact pad 130. In the embodiment of FIG. 1, line 148 electrically connects first contact pad 126 to second contact pad 130 that extends outside of the footprint of die 102 in a fan-out configuration. In an embodiment, at least a portion of the patterned conductive layer 110 below the die 102 may also be electrically connected to the second contact pad 130a via the conductive bumps 122a. Although the die 102 is not electrically connected to the conductive bump 122a and the second contact pad 130a in the embodiment of FIG. 1, the conductive bump 122a and the second contact pad 130a may help to conduct heat away from the die 102. And leave the package 100.

2 is a cross-sectional view of a semiconductor package 200 in accordance with an embodiment of the present invention. The semiconductor package 200 is similar in many respects to the semiconductor package 100 depicted in FIG. 1, and thus only the different aspects of the semiconductor package 200 are discussed herein. The semiconductor package 200 includes a substrate unit 204, wherein the substrate unit 204 includes a patterned conductive layer 210 (similar to the patterned conductive layer 110), the patterned conductive layer 210 including a first contact pad 226a (similar to the first contact pad 126) Line 248 (similar to line 148), conductive bumps 222 (similar to conductive bumps 122), conductive layer 214, and dielectric layer 228. Conductive layer 214 includes a second contact pad 230 (similar to second contact pad 130) and one or more lines 249 adjacent a lower surface 234 of a dielectric layer 218 (similar to dielectric layer 118). Dielectric layer 228 exposes a portion of conductive layer 214 to form second contact pad 230. In an embodiment, the first contact pad 226 can be covered by a surface treatment layer 227.

In one embodiment, the die 102 is electrically connected to the second contact pad 230b under the die 102 via the bond wire 136, the first contact pad 226b outside the footprint of the die 102, the line 248b, and the conductive bump 222b. This fan-in support of the package 200 is facilitated by the line 248b, wherein the line 248b extends laterally from below the die 102 to a first contact pad 226b that is external to the footprint of the die 102. As previously described in FIG. 1, wiring may be routed through a line included in a single metal layer 210 to obtain a fan-in configuration, a fan-out configuration, or a combination of both. The second contact pad 230b can cover the conductive bumps 222b such that no additional circuitry is required on the lower surface 234 of the dielectric layer 218.

As previously described, an advantage of the single-sided substrate design of one embodiment of the present invention is that the conductive bumps electrically connect the patterned conductive layer on the first side of the substrate unit to the contact on the second side of the substrate unit. Pad without through holes (such as plated through holes). Package 200 utilizes this advantage of a single-sided substrate design. Additionally, the additional conductive layer 214 of the package 200 provides additional wiring flexibility via the wires 249 on the lower surface 234 of the dielectric layer 218. In an embodiment, the second contact pad 230a is electrically coupled to the conductive bump 222a via line 249 and is laterally displaceable from its corresponding conductive bump 222a. Line 249 may be covered by dielectric layer 228. And the conductive bump 222a can be covered. It is advantageous to laterally displace the conductive bumps 222 from their corresponding second contact pads 230 to simplify routing within the package 200 because the positioning of the second contact pads 230 can be fixed based on the external interface requirements to the package 200.

3 is a cross-sectional view of a semiconductor package 300 in accordance with an embodiment of the present invention. The semiconductor package 300 is similar to the semiconductor package 100 depicted in FIG. 1 except that the die 302 is a flip chip bond. An underfill layer can be selectively added between the die 302 and the dielectric layer 124. Therefore, the second contact pad 130a under the die 302 can be electrically connected to the die 302 via a fused conductive bump 335, and the fused conductive bump 335 can be made of a conductive material such as solder. The die 302 can also be electrically connected to one or more second contact pads 130 located on the periphery of the die, such as a fan-out application. The second contact pads 130 electrically connecting the die 302 to the periphery of the die may also pass through one or more of the fused conductive bumps 335 located below the die to the patterned conductive layer 110 to the traces within the dielectric layer 118 (not Painted). Those skilled in the art will appreciate that the package 200 of Figure 2 can also support flip chip bonding in a similar manner.

4 is a cross-sectional view of a semiconductor package 400 in accordance with an embodiment of the present invention. The semiconductor package 400 is similar to the semiconductor package 100 depicted in FIG. 1 except that the die attach layer 140 is adjacent to the dielectric layer 118. The die attach layer 140 can be located in one of the openings 402 defined by a dielectric layer 424 (otherwise similar to the dielectric layer 124 of FIG. 1). Those skilled in the art will appreciate that the package 200 of Figure 2 can also support similar structures.

FIG. 5 is a cross-sectional view of a semiconductor package 500 in accordance with an embodiment of the present invention. The semiconductor package 500 is similar to the semiconductor package 300 depicted in FIG. 3 except that the primer 141 is adjacent to the dielectric layer 118. The primer 141 can be positioned between the die 302 and the dielectric layer 118 and within an opening 502 defined by a dielectric layer 524 (otherwise similar to the dielectric layer 124 of FIG. 1). Those skilled in the art will appreciate that the package 200 of Figure 2 can also support flip chip bonding having a similar structure.

FIG. 6 is a cross-sectional view of a semiconductor package 600 in accordance with an embodiment of the present invention. The semiconductor package 600 is similar to the semiconductor package 100 depicted in FIG. 1 except that the patterned conductive layer 610 defines an opening 611 that is substantially filled by a portion of a dielectric layer 624, and one or more conductive bumps Blocks 622 each define a recess 623 in which a portion of substantially dielectric layer 624 is filled. The patterned conductive layer 610, the dielectric layer 624, and the conductive bumps 622 are additionally similar to the patterned conductive layer 110, the dielectric layer 124, and the conductive bumps 122 of FIG. 1, respectively.

FIG. 7 is a cross-sectional view of a semiconductor package 700 in accordance with an embodiment of the present invention. The semiconductor package 700 is similar to the semiconductor package 200 depicted in FIG. 2, except that the patterned conductive layer 710 defines an opening 711 that is substantially filled by a portion of a dielectric layer 724, and one or more conductive bumps Each of the 722 defines a recess 723, and substantially one of the dielectric layers 724 is partially filled in the recess 723. The patterned conductive layer 710, the dielectric layer 724 and the conductive bumps 722 are additionally similar to the patterned conductive layer 210, the dielectric layer 124 and the conductive bumps 222 of FIGS. 1 and 2, respectively.

FIG. 8 is a cross-sectional view of a semiconductor package 800 in accordance with an embodiment of the present invention. The semiconductor package 800 is similar to the semiconductor package 300 depicted in FIG. 3, except that the patterned conductive layer 810 defines an opening 811 that is substantially filled by the fused conductive bumps 335, and one or more conductive bumps 822 are each A recess 823 is defined in which substantially molten conductive bumps 335 are filled. The patterned conductive layer 810 and the conductive bumps 822 are additionally similar to the patterned conductive layer 110 and the conductive bumps 122 of FIG. Those skilled in the art will appreciate that the package 200 of Figure 2 can also support flip chip bonding having a similar structure.

FIG. 9 is a cross-sectional view of a semiconductor package 900 in accordance with an embodiment of the present invention. The semiconductor package 900 is similar to the semiconductor package 400 depicted in FIG. 4, except that the patterned conductive layer 910 defines an opening 911 that is substantially filled by the die attach layer 940, and one or more conductive bumps 922 are each A recess 923 is defined, and substantially the die attach layer 940 is filled in the recess 923. The patterned conductive layer 910, the conductive bumps 922, and the die attach layer 940 are further similar to the patterned conductive layer 110, the conductive bumps 122, and the die attach layer of FIG. 140. Those skilled in the art will appreciate that the package 200 of Figure 2 can also support similar structures.

FIG. 10 is a cross-sectional view of a semiconductor package 1000 in accordance with an embodiment of the present invention. The semiconductor package 1000 is similar to the semiconductor package 800 depicted in FIG. 8 except that the primer 141 is adjacent to the dielectric layer 118. Those skilled in the art will appreciate that the package 200 of Figure 2 can also support flip chip bonding having a similar structure.

11A-11Y are cross-sectional views showing a method of fabricating a semiconductor package in accordance with an embodiment of the present invention. For ease of presentation, the following manufacturing method will be described with reference to package 200 of FIG. However, the contemplated fabrication methods can be similarly implemented to form other semiconductor component packages having different internal structures than package 200, such as the packages illustrated in Figures 1 and 3-10. The contemplated fabrication method can also be similarly implemented to form a substrate strip comprising a plurality of connected semiconductor package arrays, each substrate strip corresponding to a package such as illustrated in Figures 1 and 3-10. As depicted in Figure 11Y, the connected semiconductor package array can be singulated into a plurality of individual packages, such as the packages illustrated in Figures 1-10 and Figure 12.

First, referring to FIG. 11A, a carrier 1100 is provided. In an embodiment, the carrier 1100 includes a core layer (not shown) between two carrier conductive layers (not shown) attached to the core layer. Each carrier conductive layer may be formed of a metal, a metal alloy, a matrix in which a metal or metal alloy is dispersed, or another suitable electrically conductive material. For example, each carrier conductive layer can comprise a metal foil formed of copper or an alloy of copper. The metal foil may have a thickness ranging from about 10 [mu]m to about 30 [mu]m, such as in the range of from about 15 [mu]m to about 25 [mu]m.

The carrier 1100 has an upper surface 1102 and a lower surface 1104. The conductive layer 1103 (conductive sheet 1103) is disposed adjacent to the upper surface 1102, and a conductive layer 1105 (conductive sheet 1105) is disposed adjacent to the lower surface 1104. Each of the conductive layers 1103 and the conductive layer 1105 may be formed of a metal, a metal alloy, a matrix in which a metal or a metal alloy is dispersed, or another suitable conductive material. For example, the conductive layers 1103 and 1105 may comprise copper or copper. A releasable metal foil formed of gold. Conductive layers 1103 and 1105 can be attached to carrier 1100 by a release layer (not shown). In an embodiment, the release layer is an organic layer or an adhesive layer, such as a tape. This tape (which may be implemented as a single-sided or double-sided adhesive tape) secures the components at appropriate intervals relative to one another and allows subsequent manufacturing operations to be performed for components that are disposed adjacent to the carrier 1100. Each of the conductive layer 1103 and the conductive layer 1105 may have a thickness ranging from about 2 μm to about 20 μm, for example, from about 3 μm to about 5 μm, from about 3 μm to about 10 μm, from about 10 μm to about 20 μm, and from about 15 μm to about 20 μm. Within the scope.

Next, referring to FIG. 11B , in an embodiment, a barrier layer 1162 can be selectively disposed adjacent to the conductive layer 110 , and thus the conductive layer 1103 is located between the carrier 1100 and the barrier layer 1162 . Likewise, a barrier layer 1164 can be selectively disposed adjacent to the conductive layer 1105 such that the conductive layer 1105 is between the carrier 1100 and the barrier layer 1164. Barrier layer 1162 and barrier layer 1164 can be considered an etch stop layer. Each barrier layer may be formed of a metal, a metal alloy, a matrix in which a metal or metal alloy is dispersed, or another suitable electrically conductive material. For example, each barrier layer can be made of tantalum, tungsten, chromium, nickel, gold, tin, leads, and/or a suitable alloy including at least one of the foregoing. In an embodiment, the barrier layer may include a nickel layer and an adjacent gold layer, or a gold layer and an adjacent nickel layer. In other embodiments, the barrier layer can be formed of a tin lead alloy and/or a tin silver alloy. The method of forming each barrier layer includes a sputtering process, an immersion method, an electroplating method, and/or a conventionally appropriate method. The barrier layer 1162 and the barrier layer 1164 utilized in these embodiments will always exist as shown in FIG. 11X, please refer to the following description.

Next, referring to FIG. 11C, a photoresist material may be formed adjacent to the conductive layers 1103 and 1105. Alternatively, a photoresist material can be formed adjacent to the barrier layers 1162 and 1164 (please refer to FIG. 11B). The photoresist material can be a dry film photoresist, or another type of patternable layer or dielectric layer. Photoresist layers 1106 and 1108 can be formed by coating, printing, or any other suitable technique. Photoresist layers 1106 and 1108 The predetermined or selected portion can be photoimaged and developed to form openings, including openings 1107a, 1107b exposing dielectric layer 1103 and openings 1109a, 1109b exposing dielectric layer 1105. Photoresist layers 1106 and 1108 can be photochemically defined using a photomask (not shown). Photoimaging or development may have the advantage of lower cost and reduced process time compared to other methods for forming openings in photoresist layers 1106 and 1108. The resulting opening can have any of a number of shapes, including a cylindrical shape, such as a circular cylindrical shape, an elliptical cylindrical shape, a square cylindrical shape, or a rectangular cylindrical shape; or a non-cylindrical shape such as a cone, a funnel, or another Tapered shape. It is also contemplated that the lateral boundaries of the resulting openings may be curved or substantially textured.

Next, referring to FIG. 11D, a conductive material is applied to the opening, including openings 1107a, 1107b defined by the photoresist layer 1106 and openings 1109a, 1109b defined by the photoresist layer 1108 to form a vertical extension from the conductive layer 1103. The conductive block 1110 and the conductive block 1111 extending perpendicularly from the conductive layer 1105. Alternatively, the conductive block 1110 can extend vertically from the barrier layer 1162 (please refer to FIG. 11B), and the conductive block 1111 can extend vertically from the barrier layer 1164 (please refer to FIG. 11B). The conductive blocks 1110 and 1111 may be formed of a metal, a metal alloy, a matrix in which a metal or metal alloy is dispersed, or other suitable conductive material. For example, the conductive bumps 1110 and 1111 can comprise one or more layers of copper or an alloy including copper. Conductive blocks 1110 and 1111 may be formed using any of a number of coating techniques, such as chemical vapor deposition, electroless plating, electrolytic plating, printing, spinning. , spraying, sputtering, or vacuum deposition.

Next, referring to FIG. 11E, at least one barrier layer 1166 and 1168 may be formed in place of the barrier layers 1162 and/or 1164 previously described in FIG. 11B. Barrier layers 1166 and 1168 are considered etch stop layers. A first portion 1110a of the conductive block 1100 can be formed. The barrier layer 1166 can be disposed adjacent to the first portion 1110a by sputtering, immersion, plating, and/or conventional methods. A second portion 1110b of the conductive block 1110 can be formed adjacent to the barrier layer 1166, thus The barrier layer 1166 can be located between the first portion 1110a and the second portion 1110b. The barrier layer 1168 can be formed in a similar manner between a first portion 1111a and a second portion 1111b of the conductive block 1111. The forming materials of the barrier layers 1166 and 1168 may be similar to the forming materials of the barrier layers 1162 and 1164. Please refer to the description of FIG. 11B above.

Next, referring to FIG. 11F, the photoresist layers 1106 and 1108 are stripped to expose the conductive layers 1103 and 1105. Next, a layer 1112 is provided. In an embodiment, the layer 1112 may be pre-formed with a plurality of first openings 1112a, and the portions of the first openings 1112a respectively correspond to the positions of the conductive blocks 1110. A similar layer 1114 having an opening corresponding to the location of the conductive block 1111 can be provided (please refer to FIG. 11G). In one embodiment, layer 1112 includes a fiber-reinforced resin material, such as a gel material, including glass fiber 1190, to strengthen layer 1112. As shown in FIG. 11F, the glass 1190 is initially disposed along a level plane of the layer 1112. When these first openings 1112a, please refer to FIG. 11F, portions extend through layer 1112. In other embodiments contemplated, the first openings 1112a may also extend completely through the layer 1112.

Next, referring to FIG. 11G, the layer 1112 forms an exposed portion adjacent to the conductive block 1110 and the conductive layer 1103. In an embodiment, layer 1112 corresponds to and includes dielectric layer 218, please refer to FIG. Similarly, layer 1114 forms a portion that is exposed adjacent to conductive block 1111 and conductive layer 1105. Layers 1112 and 1114 substantially cover conductive layers 1103 and 1105, respectively, such that conductive layers 1103 and 1105 are embedded in layers 1112 and 1114, respectively. In an embodiment, layer 1112 can be formed by laminating a dielectric material on upper surface 1120 of each of conductive blocks 1110 and on exposed portions of conductive layer 1103. Similarly, layer 1114 can be formed by laminating a dielectric material on upper surface 1121 (reversed for manufacturing operations) and exposed portions of conductive layer 1105 of each of conductive blocks 1111. In one embodiment, the glass fibers 1190 are oriented after the layers 1112 and 1114 are stacked, along with portions of the conductive blocks 1110 and 1111 that extend in a direction extending perpendicularly to one of the conductive blocks 1110 and 1111, and are respectively away from the conductive layer 1103. With 1105.

The laminated dielectric material may be made of a fiber reinforced resin material and/or a prepreg (PP) to increase rigidity. The fibers may be glass fibers or Kevlar fibers (melamine fibers). The laminated dielectric material can be formed from a fiber reinforced film. Examples of resin materials that can be reinforced by fibers for use in laminated dielectric materials include Ajinomoto build-up film (ABF), bismaleimide triazine (BT), poly Polyimide (PI), liquid crystal polymer (LCP), epoxy resin, and other resin materials. The resin material can be partially cured. In an embodiment, the laminated dielectric material is preformed to define an opening at a location corresponding to conductive block 1110 or conductive block 1111.

Alternatively, layers 1112 and 1114 may be formed from an unreinforced, less rigid material, such as a solder mask (solder resist), including but not limited to Ajinomoto build-up film (ABF), bismaleimide triazine (BT) a resin material of polyimine (PI), liquid crystal polymer (LCP) and epoxy resin, or another type of patternable layer or dielectric layer. This material can be applied using any of several coating techniques, such as printing, spin coating or spraying.

Layers 1112 and 1114 are then covered by conductive layers 1116 and 1117, respectively. Conductive layers 1116 and 1117 may be formed of a material similar to that used to form conductive layers 1103 and 1105. Each of conductive layers 1116 and 1117 can have a thickness ranging from about 10 [mu]m to about 20 [mu]m, such as in the range of from about 10 [mu]m to about 15 [mu]m.

Next, referring to FIG. 11H, a portion of each of the conductive layers 1116 and 1117 is removed, for example, by flash etching to form conductive layers 1122 and 1123. Each of the conductive layers 1122 and 1123 can have a thickness ranging from about 3 μm to about 10 μm, such as from about 3 μm to about 7 μm.

Next, referring to FIG. 11I, openings 1124a and 1124b of the exposed layer 1112 are formed in the conductive layer 1122 to form a conductive layer 1128. Similarly, openings 1126a and 1126b of the exposed layer 1114 are formed in the conductive layer 1123 to form the conductive layer 1129. The openings 1124 and 1126 are contemplated to have a width that is less than the width of the conductive blocks 1110 and 1111, respectively. Or, opening 1124 and 1126 can each have a width substantially equal to that of conductive blocks 1110 and 1111. In one embodiment, portions of conductive layers 1128 and 1128 (not shown) may be patterned to form at least one portion of ground layer 1250 (please refer to FIGS. 12 and 13). Patterning can be performed in any of a number of ways to form layers 1128 and 1129, such as chemical etching, laser drilling, or mechanical drilling, and the resulting opening can have any of a number of shapes, such as a cylindrical shape, such as a circle. a cylindrical shape, an elliptical cylindrical shape, a square cylindrical shape, or a rectangular cylindrical shape; or a non-cylindrical shape such as a cone, a funnel, or another tapered shape. It is also contemplated that the lateral boundaries of the resulting openings may be curved or substantially textured.

Next, referring to FIG. 11H, openings 1130a and 1130b exposing the conductive block 1110 are formed in the layer 1112 to form a layer 1134. Similarly, openings 1132a and 1132b exposing conductive block 1111 are formed in layer 1114 to form layer 1136. The openings 1130 and 1132 are contemplated to correspond to the dimensions of the openings 1124 and 1126, respectively (please refer to FIG. 11I). In one embodiment, portions of layers 1112 and 1114 can be patterned to expose conductive pads underlying ground planes 1250 (see FIGS. 12 and 13). Patterning may be performed in any of a number of ways to form layers 1134 and 1136, such as laser drilling, plasma etching, or plasma cleaning, and the resulting opening may have any of a number of shapes, such as a cylindrical shape, such as A circular cylindrical shape, an elliptical cylindrical shape, a square cylindrical shape, or a rectangular cylindrical shape; or a non-cylindrical shape such as a cone, a funnel shape, or another tapered shape. It is also contemplated that the lateral boundaries of the resulting openings may be curved or substantially textured. In one embodiment, one or more of openings 1130 and 1132 (such as openings 1130b and 1132b in FIG. 11J) may be substantially centered relative to respective ones of conductive blocks 1110 and 1111, respectively. Alternatively or additionally, one or more of the openings 1130 and 1132 (such as openings 1130a and 1132a in FIG. 11J) may be substantially off center with respect to respective ones of the conductive blocks 1110 and 1111, respectively.

Next, referring to FIG. 11K, a metal material is disposed adjacent to the conductive layer 1128 and the conductive block 1110 to form a sub-layer 1180. A similar seed layer 1181 is disposed adjacent to the conductive layer 1129 and the conductive block 1111. In an embodiment, the seed layer 1180 can be substantially filled in the opening 11130, such that portions of seed layer 1180 form conductive bumps, such as conductive bumps 222a and 222b of FIG. Similarly, the seed layer 1181 can be substantially filled in the opening 1132 such that portions of the seed layer 1181 form conductive bumps, such as conductive bumps 1137a and 1137b. (Similar conductive bumps 1137a and 1137b corresponding to individual semiconductor packages are depicted on opposite sides of the carrier 1100.) Alternatively, the seed layer 1180 can be partially filled in the opening 1130, such that portions of the seed layer 1180 form the A first portion of the conductive bumps 222a and 222b. The seed layer 1181 can be partially filled within the opening 1132 such that portions of the seed layer 1181 form a first portion of the conductive bumps 1137a and 1137b. In one embodiment, conductive bumps (not shown) may be formed between the ground layer 1250 (please refer to FIGS. 12 and 13) and the conductive blocks under the ground layer 1250. The metal material may have properties similar to those used to form the conductive bumps 1110 and 1111, such as copper or a copper alloy. Seed layers 1180 and 1181 can be formed using any of a number of coating techniques, such as electroless plating.

In one embodiment, the off-center positioning of the conductive bumps 222a relative to the conductive bumps 1110 corresponds to the lateral displacement of the second contact pads 230a relative to the conductive bumps 222a shown in FIG. The centered positioning of the conductive bumps 222b relative to the conductive bumps 1111 corresponds to the centered positioning of the conductive bumps 222b shown in FIG. 2 relative to the second contact pads 230b.

Next, referring to FIG. 11L, photoresist layers 1138 and 1139 adjacent to the seed layers 1180 and 1181 are formed, respectively. Predetermined or selected portions of photoresist layers 1138 and 1139 can be photoimaged and developed to form openings 1140 and 1141, respectively. The opening 1140 exposes the seed layer 1180 and the opening 1141 exposes the seed layer 1181. Photoresist layers 1138 and 1139 (and openings 1140 and 1141) have similar characteristics and similar formations as photoresist layers 1106 and 1108 (and openings 1107 and 1109) described with reference to FIG. 11C.

Next, referring to FIG. 11M, a metal material is disposed adjacent to portions of the seed layers 1180 and 1181 that are not covered by the photoresist layers 1138 and 1139 to form conductive layers 1142 and 1144. In one embodiment, conductive layers 1142 and 1144 are adjacent to conductive bumps 222 and 1137, respectively. Alternatively, portions of conductive layers 1142 and 1144 may form second of conductive bumps 222 and 1137, respectively. section. The second portions of conductive bumps 222 and 1137 are adjacent to the first portions of conductive bumps 222 and 1137 previously described in FIG. 11K. The metal material may have properties similar to those used to form the conductive bumps 1110 and 1111, such as copper or a copper alloy. Conductive bumps 222 and 1137 and conductive layers 1142 and 1144 can be formed using any of a number of coating techniques, such as electrolytic plating.

Next, referring to FIG. 11N, photoresist layers 1138 and 1139 are stripped to expose additional portions of seed layers 1180 and 1181.

In an embodiment, the additional photoresist may be disposed adjacent to the conductive layer 1142, wherein the photoresist defines an opening corresponding to the location of the opening 711 in the package 700 of FIG. A portion of conductive layer 1142 can be removed to form opening 711. Additionally, a portion of each of the conductive bumps 222 can be removed to form a recess 723 (please refer to FIG. 7). Removal of such portions of conductive layer 1142 can occur via chemical etching, laser drilling, or mechanical drilling. Opening 711 and recess 723 (please refer to Figure 7) have similar characteristics as previously described for openings 1124 and 1126 (see Figure 11I). Next, additional photoresist can be removed to expose the conductive layer 1142' as shown in FIG.

Next, please refer to FIG. 11N with reference to FIGS. 11P to 11Y, but those skilled in the art will appreciate that similar steps may follow FIG.

Next, referring to FIG. 11P, a portion of each of the conductive layers 1128 and 1129 and a portion of the seed layers 1180 and 1181 are removed, for example, by flash etching to form a patterned conductive layer 210 similar to that of FIG. Patterned conductive layer. The patterned conductive layer 210 includes portions 1182a and 1182b of the seed layer 1180, and the patterned conductive layer 210 is disposed adjacent to the conductive bumps 222. (A similar patterned conductive layer 1146 corresponding to a separate semiconductor package is depicted on the opposite side of the carrier 1100.) In one embodiment, a patterned conductive layer similar to the patterned conductive layer of FIG. 2 can include a ground layer 1250 (Please refer to Figures 12 and 13).

Next, referring to FIG. 11Q, dielectric layers 1148 and 1149 are formed to cover portions of patterned conductive layers 210 and 1146, respectively. Dielectric layer 1148 exposes the inclusion of patterned conductive layer 210 A portion of the two contact pads 226. Dielectric layers 1148 and 1149 may be formed from a solder resist (solder mask) or another type of dielectric material.

Next, referring to FIG. 11R, the remaining portions of the patterned conductive layers 210 and 1146 are not covered by the dielectric layers 1148 and 1149, respectively, but may be covered by a plating layer similar to the plating layer 227 of FIG. (A similar plating layer 1150 corresponding to a separate semiconductor package is depicted on the opposite side of the carrier 1100.) The plating layers 227 and 1150 may be formed of tin, nickel, and gold or at least one of tin or an alloy comprising nickel and gold. .

Next, referring to FIG. 11S, the carrier 1100 is removed to expose the conductive layer 1103 of the substrate 1152. (The conductive layer 1105 of the other substrate is also exposed by removing the carrier 1100. This is not shown in FIG. 11S.) The substrate 1152 includes a plurality of adjacent substrate units, which are similar, for example but not limited to, FIG. The substrate unit 104 or the substrate unit 204 of FIG.

As shown in FIG. 1A, the conductive layer 1103 may have a thickness 1172 of between 15 μm and 20 μm. The conductive layer 1103 can be chemically etched to reduce the thickness 1172 of the conductive layer 1103 to a range of from 3 μm to 10 μm, for example, from 3 μm to 8 μm. The reason why the conductive layer 1103 is etched is that the warpage of the substrate 1152 can be effectively reduced by the thickness of 3 μm to 8 μm, and the reliability of making the package using the substrate 1152 can be increased. The thickness of the conductive layer 1103 is larger or smaller than this range to cause warpage of the substrate 1152.

Next, referring to FIG. 11T , in an embodiment, a support member 1170 can be randomly disposed adjacent to the conductive layer 1103 , and thus the conductive layer 1103 is located between the conductive block 1110 and the support member 1170 . During the fabrication of the substrate 1152 and the assembly including the substrate 1152 (please refer to FIGS. 11W to 11Y), attaching the support 1170 to the substrate 1152 can also effectively reduce the warpage of the substrate 1152, thereby increasing the package made by the substrate 1152. Reliability. In one embodiment, the support member may be a laminate of polyethylene terephthalate (PET), metal, epoxy, double-layer copper foil, and/or a suitable material.

Next, referring to FIG. 11U , the barrier layer 1162 described in FIG. 11B can be selectively disposed between the conductive block 1110 and the conductive layer 1103 .

Next, referring to FIG. 11V, the barrier layer 1166 previously described in FIG. 11E can be selectively disposed between the first portion 1110a and the second portion 1110b of the conductive block 1110.

Next, referring to FIG. 11W, one or more of the dies 102 are electrically connected to the substrate 1152 and electrically connected to the conductive layer 1103. The die 102 can be electrically connected to the conductive layer 1103 via a bonding wire 136. Alternatively, the die (such as die 302 as shown in Figures 3, 5, 8 and 10) may be electrically connected to conductive layer 1103 via a flip chip bond. The die 102 can be attached to the substrate 1152 by a die attach layer 140. A molded structure 1154 is formed to coat the die 102. In an embodiment, the optional support member 1170 (please refer to FIG. 11T) can be removed to expose the conductive layer 1103.

Then, referring to FIG. 11X, the conductive layer 1103 can be removed, for example, via chemical etching and/or rapid etching to expose the dielectric layer 1156. After removal of the conductive layer 1103, a portion of the conductive bumps 1110 (see FIG. 11E) may be removed, such as via chemical etching, to form the second contact pads 230 and lines 249 of FIG. Advantageously, the surface of dielectric layer 1156 and conductive block 1110 can be protected by conductive layer 1103 to prevent exposure to environmental conditions. It may be desirable to extend the duration of this protection by removing the conductive layer 1103 after attaching and cladding the die 102. In an embodiment, the barrier layer 1162 described in FIG. 11B and/or the barrier layer 1166 described in FIG. 11E can be regarded as a protective cover to avoid the transient etching of the conductive block 1110, so the second contact pad 230 and Line 249 has at least a minimum required thickness. In another embodiment, after etching the conductive layer 1103, the barrier layer 1162 and/or the barrier layer 1166 can utilize a barrier layer 1162 and/or a barrier layer 1166 without damaging the second contact pad 230, The etchant of line 249 and dielectric layer 1156 is used for selective chemical etching.

Finally, referring to FIG. 11Y, a dielectric layer including dielectric layer 228 of FIG. 2 can be formed and patterned such that dielectric layer 228 exposes second contact pads 230. A singulation step along the dashed lines 1158 and 1160 can then be performed to obtain a plurality of separate semiconductor packages, such as the semiconductor package 200 of FIG. Electrical contacts, such as electrical contacts 133 shown in FIG. 1, may be disposed on second contact pads 230 before or after singulation.

Those skilled in the art should understand the patterned conductive layer 110 and the conductive bumps 122 of FIG. The patterned conductive layer 210 and conductive bumps 222 of FIG. 2 and corresponding structures in the packages of FIGS. 3-10 can include portions of a sub-layer, such as seed layer 1180 included in the package structure depicted in FIG.

FIG. 12 is a cross-sectional view of a semiconductor package 1200 in accordance with an embodiment of the present invention. The semiconductor package 1200 is similar to the semiconductor package 100 described in FIG. 1 except that the semiconductor package 1200 includes a ground layer 1250 disposed between the dielectric layer 124 and the dielectric layer 118. The ground plane 1250 includes and is formed of the same material as a patterned conductive layer 1240, such as the patterned conductive layer 110 of FIG. The ground layer 1250 can serve as a dual heat dissipation purpose and can provide the die 102 electrically connected to the ground. The die 102 can be electrically connected to the ground layer 1250 through the bonding wire 136. The ground layer 1250 is electrically connected to the external electrical contact 133 through the conductive bumps 122. The heat of the package 1200 can be dispersed through the external electrical contacts 133, for example, under the printed circuit board. One or more external electrical contacts 133 may provide electrical connection to ground. Alternatively, the external contact 133 can only be considered a heat sinking effect. Those skilled in the art will appreciate that the package of the wire-bonding embodiment can also support a similar structure.

FIG. 13 is a top plan view of the semiconductor package 1200 of FIG. This top view shows the structure of the ground plane 1250. In one embodiment, the ground layer 1250 is a mesh shape defining a plurality of openings of a two-dimensional lattice pattern. Please refer to FIG. These openings may be substantially the same size and may have substantially uniform spacing, please refer to FIG. Alternatively, the openings can have different sizes and can have a uniform spacing (for example, in one embodiment, some openings are larger and some openings are smaller). The ground pattern 1250 of the mesh pattern provides better reliability than the interface of the other patterned ground layer 1250 between the dielectric layer 124 (eg, a solder mask) and the ground layer 1250.

Alternatively, the ground layer 1250 can be a void-free plane, an annular pattern, or/and a strip pattern. The annular pattern may comprise a single ring or may comprise a plurality of rings having a plurality of openings between the various rings. The plurality of rings can be concentric rings of different sizes, and the rings can be substantially circular. The strip pattern may include a plurality of extending from a first side of the ground layer 1250 to the ground layer 1250. a second side strip having a plurality of openings between the strips. The strips can be substantially parallel. The strips may have substantially the same length or may have different lengths.

Although FIG. 1 to FIG. 13 illustrates that the package includes a single-sided substrate and an electrically conductive bump embedded in the single-sided substrate, a substrate of one of the semiconductor packages is contemplated, and generally includes a plurality of dielectric layers, each of which may include A dielectric layer includes an embedded group (or, in particular, an electrically conductive via) having a plurality of conductive bumps. A substrate comprising a plurality of dielectric layers can be desired, for example, in a package having relatively complex circuitry that allows for line flexibility. When controlling the cost and complexity of the packaging process, electrical conductive bumps can be utilized to effectively reduce package size and package area. In other embodiments, a plurality of dielectric layers in which the respective electrically conductive bumps are buried may be included to handle various electrical distributions to increase structural strength and structural reliability.

Although the present invention has been described with reference to the specific embodiments of the present invention, it will be understood by those skilled in the art that various changes can be made without departing from the true spirit and scope of the invention as defined by the appended claims. Replace various equivalents. In addition, many modifications may be made to adapt a particular situation, material, material composition, method or process to the purpose, spirit and scope of the invention. All such modifications are intended to be within the scope of the appended claims. In particular, although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it is understood that such operations can be combined, sub-sequenced, or re-sequenced to form equivalents without departing from the teachings of the present invention. method. Therefore, the order of operations and groupings are not limiting of the invention, unless explicitly indicated herein.

100‧‧‧Semiconductor package

102‧‧‧ grain

104‧‧‧Substrate unit

106‧‧‧Package body

110‧‧‧ patterned conductive layer

112, 142, 146‧‧‧ upper surface

114‧‧‧Electrical block

116, 134, 144‧‧‧ lower surface

118, 124‧‧‧ dielectric layer

120‧‧‧ openings

122, 122a‧‧‧ conductive bumps

126‧‧‧First contact pad

130, 130a‧‧‧second contact pad

133‧‧‧Electrical contacts

136‧‧‧welding line

138‧‧‧Active surface

140‧‧‧ die adhesion layer

148‧‧‧ lines

150‧‧‧ thickness

Claims (14)

A substrate unit includes: a first patterned conductive layer having an upper surface; a first dielectric layer disposed on the upper surface of the first patterned conductive layer, the first dielectric layer exposing the first a portion of the patterned conductive layer to form a plurality of first contact pads; a second patterned conductive layer under the first patterned conductive layer and having a lower surface; a second dielectric layer located at the first Between the patterned conductive layer and the second patterned conductive layer, wherein the second dielectric layer defines a plurality of openings extending from the first patterned conductive layer to the second patterned conductive layer, and the second The patterned conductive layer includes a plurality of second contact pads exposed by the second dielectric layer; and a plurality of conductive bumps, each of the conductive bumps being via a corresponding one of the openings in the second dielectric layer The first patterned conductive layer extends to a corresponding one of the second contact pads, and each of the conductive bumps is filled in a corresponding one of the openings in the second dielectric layer; wherein each of the conductive bumps has a first One area of the upper surface and one possesses a lower surface of the second area; and each of the second contact pads has an upper surface having a third area; and wherein the first area is different from the second area, and the third area is opposite the second area different. The substrate unit of claim 1, wherein the first area is larger than the second area, and the third area is larger than the second area. The substrate unit of claim 1, wherein at least one of the conductive bumps defines a recess. The substrate unit of claim 1, wherein: the second dielectric layer has a lower surface; and the lower surface of the second patterned conductive layer is recessed on the lower surface of the second dielectric layer . The substrate unit of claim 1, wherein the first patterned conductive layer comprises a first conductive layer, a second conductive layer, and a first electrode layer and the second conductive layer Seed layer. a substrate comprising: a patterned conductive layer having an upper surface and a lower surface; a first dielectric layer configured to be adjacent to the upper surface of the patterned conductive layer, the first dielectric layer Forming a plurality of contact pads in a portion of the patterned conductive layer; a second dielectric layer configured to be adjacent to the lower surface of the patterned conductive layer, wherein the second dielectric layer defines a plurality of And a plurality of conductive bumps, each of the plurality of conductive bumps protruding from the patterned conductive layer and passing through a corresponding one of the plurality of openings in the second dielectric layer, wherein the plurality Both a dielectric layer and the second dielectric layer are unreinforced materials. The substrate of claim 6, wherein the second dielectric layer comprises a lower surface; and a carrier is disposed adjacent to the lower surface of the second dielectric layer. The substrate of claim 7, wherein the carrier comprises a support member and a conductive sheet, the conductive sheet being located between the support member and the lower surface of the second dielectric layer. The substrate of claim 6, wherein the patterned conductive layer comprises a first conductive layer, a second conductive layer, and one of the seed layers. The substrate of claim 6, wherein the patterned conductive layer and the guide The electric bumps are integrally formed. a substrate comprising: a first patterned conductive layer comprising a plurality of first contact pads and at least one first line; a second patterned conductive layer under the first patterned conductive layer and including a lower surface a first dielectric layer between the first patterned conductive layer and the second patterned conductive layer, wherein the first dielectric layer defines a plurality of extending from the first patterned conductive layer to the The second patterned conductive layer has an opening, and the second patterned conductive layer includes a plurality of second contact pads and at least one second line; a second dielectric layer configured to be adjacent to the first dielectric layer The second dielectric layer exposes the first contact pad and covers the first line; and a plurality of conductive bumps, each of the plurality of conductive bumps extending from the first patterned conductive layer to the first A patterned conductive layer, each of the plurality of conductive bumps being filled in a respective one of the plurality of openings in the second dielectric layer. The substrate of claim 11, wherein: the first dielectric layer has a lower surface; and the lower surface of the second patterned conductive layer is recessed from the lower surface of the first dielectric layer. The substrate of claim 11, further comprising: a third dielectric layer disposed on the first dielectric layer, the third dielectric layer exposing the second contact pad. The substrate of claim 11, wherein the conductive bump has an upper surface and a lower surface, the upper surface has a first area and the lower surface has a second area, and the first area is larger than the The second area.