CN209471959U - A kind of three-dimensional encapsulation NOR FLASH memory - Google Patents

Abstract

The utility model discloses a kind of three-dimensional encapsulation NOR FLASH memory, be related to storing apparatus field, including stack from bottom to up setting a backplane level and multiple chip layers；Each chip layer respectively includes a NOR FLASH chip；The backplane level is equipped with the pin for external connection, and a backplane level of the stacking and multiple chip layers form final memory finished product through processes such as encapsulating, cutting, metallization and laser engravings；It is characterized by: each chip layer respectively further comprises a fixed patch, the fixed patch double faced adhesive is in the NOR FLASH chip of the adjacent chip layer in the NOR FLASH chip lower surface of affiliated chip layer and lower section or the upper surface of backplane level.The utility model can guarantee the close connection between chip layer and chip layer and between chip layer and backplane level；The stability and impact resistance for improving memory entirety, be suitably applied it is various using field, such as Aeronautics and Astronautics field.

Description

A kind of three-dimensional encapsulation NOR FLASH memory

Technical field

The utility model relates to store apparatus field more particularly to a kind of three-dimensional encapsulation NOR FLASH memory.

Background technique

With the continuous development of contemporary electronic technology and universal, the target of sustainable development is adhered in industry, in science and technology On Innovation Road with day all into.Nowadays in the computer system in Aeronautics and Astronautics field, it is increasingly required runs software operation System, thus it is higher to the rate requirement of data storage, need NOR FLASH data storage device to store as data, at certain It is increasing to the capacity requirement of NOR FLASH memory since the complexity of operating system increases in a little applications, occur Demand of the system to large capacity NOR FLASH memory, the method for being able to satisfy this demand can be that increase NOR FLASH mono- The quantity of piece, but since this method needs to occupy biggish system bulk, therefore be not instantly emerging method already.It connects and generates Based on the mass storage of three-dimensional encapsulation since it greatly reduces the reliabilities of the volume of shared system and promotion, length The advantages that service life, is more used in aerospace at present.

Backplane level and multiple chip layers are arranged from top to bottom by the way of stacking in the prior art, but such method is simultaneously It is impossible to ensure that the close connection between chip layer and chip layer and between chip layer and backplane level, is using process for filling colloid Afterwards, between two adjacent structure sheafs may there are gaps, to cause the integrally-built stability of memory poor, shock resistance Scarce capacity.

Utility model content

The technical problem to be solved by the present invention is to provide a kind of three-dimensional encapsulation NOR FLASH memory, Neng Goubao The seamless connection between each structure sheaf is demonstrate,proved, the overall stability and impact resistance of memory are improved.

To achieve the above object, the following technical solution is employed for the utility model:

A kind of three-dimensional encapsulation NOR FLASH memory, a backplane level and multiple cores including stacking setting from bottom to up Lamella；Each chip layer respectively includes a NOR FLASH chip；The backplane level is equipped with the pin for external connection, institute The backplane level and multiple chip layers for stating stacking expose electrical connection pin on periphery after encapsulating, cutting, and in outer surface Equipped with plating gold bonding wire；Gold bonding wire is plated to carry out the electrical connection pin exposed on one backplane level and multiple chip layers It is connected with each other；It is characterized by:

Each chip layer respectively further comprises a fixed patch, and the fixed patch is double-sided adhesive structure, is set to affiliated The NOR FLASH chip of the adjacent chip layer in the NOR FLASH chip lower surface of chip layer and lower section or backplane level it is upper Surface.

As an improved technical scheme, the backplane level includes bottom plate and lead frame, and the lead frame is fixed on On the bottom plate, the pin of the external connection is arranged on the lead frame.

As an improved technical scheme, the bottom plate is an integral molding structure with lead frame.

As an improved technical scheme, the bottom plate and the lead frame are welded to connect.

As an improved technical scheme, the multiple chip layer is eight chip layers, the NOR of eight chip layers The data/address bus of FLASH chip, address wire, write-protect/acceleration, reset signal, write enable signal, byte/word mode, busy number Output, output enable signal line distinguish compound, chip selection signal juxtaposition.

It is provided with the fixation patch of double face binding between chip layer and between chip layer and backplane level, can guarantee core Close connection between lamella and chip layer and between chip layer and backplane level；Improve memory entirety stability and Impact resistance.The utility model leads to three-dimensional encapsulation mode and avoids carrying out all NOR FLASH cores of juxtaposition in a chip layer Piece reduces the plane space for occupying printed circuit board, is suitably applied various using field, such as boat in the case where condition is limited Empty, space industry.The NOR FLASH core of the further eight 4M × 16bit of specific the application itself design of the utility model Connection relationship between piece.

Detailed description of the invention

Fig. 1 is the sectional view of memory provided by the embodiment of the utility model；

Fig. 2 is eight NOR FLASH chip connection schematic diagram provided by the embodiment of the utility model.

Specific embodiment

In order to which the technical solution of the utility model is more clearly understood, below in conjunction with attached drawing and specific embodiment to this reality It is described further with novel.

Embodiment one

Such as Fig. 1, a kind of three-dimensional encapsulation NOR FLASH memory that capacity is 32M × 16bit provided in this embodiment, packet Include the backplane level stacked from bottom to up and eight chip layers: backplane level includes bottom plate 11 and lead frame 13, lead Frame 13 is arranged on bottom plate 11, and lead frame 13 is equipped with the pin 12 for external connection；Lead frame 13 and bottom plate 11 It can be an integral molding structure, be also possible to lead frame 13 and be welded on 11 on bottom plate；

Eight chip layers are respectively the first chip layer, the second chip layer, third chip layer, fourth chip layer, fifth chip Layer, the 6th chip layer, the 7th chip layer, the 8th chip layer；

Wherein the first chip layer successively includes the first fixed patch 22, the first NOR FLASH chip 21 from top to bottom；First Fixed 22 double face binding of patch is in the upper surface of backplane level and the lower surface of the first NOR FLASH chip 21；

Second chip layer successively includes the second fixed patch 32, the 2nd NOR FLASH chip 31 from top to bottom；Second is fixed 31 double face binding of patch is in the upper surface of the first NOR FLASH chip 21 and the lower surface of the 2nd NOR FLASH chip 31；

Third chip layer successively includes third fixed patch 42, the 3rd NOR FLASH chip 41 from top to bottom；Third is fixed 42 double face binding of patch is in the upper surface of the 2nd NOR FLASH chip 31 and the lower surface of the 3rd NOR FLASH chip 41；

Fourth chip layer successively includes the 4th fixed patch 52, the 4th NOR FLASH chip 51 from top to bottom；4th is fixed 52 double face binding of patch is in the upper surface of the 3rd NOR FLASH chip 41 and the lower surface of the 4th NOR FLASH chip 51；

Fifth chip layer successively includes the 5th fixed patch 62, the 5th NOR FLASH chip 61 from top to bottom；5th is fixed 62 double face binding of patch is in the upper surface of the 4th NOR FLASH chip 51 and the lower surface of the 5th NOR FLASH chip 61；

6th chip layer successively includes the 6th fixed patch 72, the 6th NOR FLASH chip 71 from top to bottom；6th is fixed 72 double face binding of patch is in the upper surface of the 5th NOR FLASH chip 61 and the lower surface of the 6th NOR FLASH chip 71；

7th chip layer successively includes the 7th fixed patch 82, the 7th NOR FLASH chip 81 from top to bottom；7th is fixed 82 double face binding of patch is in the upper surface of the 6th NOR FLASH chip 71 and the lower surface of the 7th NOR FLASH chip 81；

8th chip layer successively includes the 8th fixed patch 92, the 8th NOR FLASH chip 91 from top to bottom；8th is fixed 92 double face binding of patch is in the upper surface of the 7th NOR FLASH chip 81 and the lower surface of the 8th NOR FLASH chip 91；

The backplane level and eight chip layers that above-mentioned heap is folded expose electrical connection on periphery after encapsulating, cutting and draw Foot, and plating gold bonding wire is equipped in outer surface；The electricity that plating gold bonding wire will be exposed on one backplane level and eight chip layers Gas connection pin is connected with each other, the pin on lead frame as three-dimensional encapsulation memory external access signal with it is external The physical connection object of input signal.

Data/address bus, address wire, write-protect/acceleration, reset signal, the write enable signal, word of eight NOR FLASH chips Section/word pattern, busy number output, output enable signal line difference are compound；The chip selection signal juxtaposition of eight SRAM.

The S29JL064H90 chip of eight FLASH chip 4M × 16bit, final memory be memory capacity be 32M × 16bit, data-bus width are the encapsulation NAND FLASH chip of 22,56 pins.

The preparation process of above-mentioned three-dimensional encapsulation NOR FLASH memory is as follows:

(1) lead frame 13 is welded on bottom plate 11 as backplane level；

(2) pin of eight NOR FLASH chips is played into straight leveling, eight NOR FLASH cores with dedicated moulds of industrial equipment The pin of piece is horizontal externally to be listed；

(3) backplane level, the first chip layer, the second chip layer, third chip layer, the 4th core are sequentially placed into stack mold Lamella, fifth chip layer, the 6th chip layer, the 7th chip layer, the 8th chip layer；

It is fixed to guarantee memory high consistency by fixture after the completion of all chip layer patches are folded；

(4) backplane level folding of patch and eight chip layers are potted using epoxy resin, in baking and curing, are torn open Except mold.

(5) to after encapsulating a backplane level and eight chip layers cut, to allow a backplane level and eight chips Layer exposes electrical connection pin on respective periphery；

(6) surface metalation processing is carried out to a backplane level and eight chip layers, forming a layer thickness is about 20um's The coat of metal, at this point, the coat of metal is connect with the electrical connection pin that eight chip layers are exposed on respective periphery, exposing It is all connected with each other between electrical connection pin and also connects pin simultaneously；The coat of metal can be Gold plated Layer either nickel plating Layer.

(7) in order to which the signal node of the separation is separated, practical laser engraving carries out surface line engraving to form gold Belong to connecting line, the electrical connection pin exposed on backplane level and chip layer is carried out corresponding connection to form one by metal contact wires Memory capacity reaches 32M × 16bit, and data-bus width is the encapsulation NAND FLASH chip of 22,56 pins.Lead frame Physical connection of 13 pin 12 as external the access signal and external output signal of three-dimensional encapsulation NOR FLASH memory Object.

The particular use of each pin of this three-dimensional encapsulation NOR FLASH memory such as table 1.

The particular use of 1 pin of table

Pin number

Title

Type

Description

Pin number

Title

Type

Description

1

NC

Empty foot

56

#CE7

I

Piece choosing, it is low effective

2

#CE4

I

Piece choosing, it is low effective

55

#CE1

I

Piece choosing, it is low effective

3

A15

I

Address wire

54

A16

I

Address wire

4

A14

I

Address wire

53

#BYTE

I

Byte/word selection

5

A13

I

Address wire

52

VSS

Power supply

Ground

6

A12

I

Address wire

51

DQ15

I/O

Data/address bus

7

A11

I

Address wire

50

DQ7

I/O

Data/address bus

8

A10

I

Address wire

49

DQ14

I/O

Data/address bus

9

A9

I

Address wire

48

DQ6

I/O

Data/address bus

10

A8

I

Address wire

47

DQ13

I/O

Data/address bus

11

A19

I

Address wire

46

DQ5

I/O

Data/address bus

12

A20

I

Address wire

45

DQ12

I/O

Data/address bus

13

#WE

I

Write signal, it is low effective

44

DQ4

I/O

Data/address bus

14

#Reset

I

It resets

43

VCC

Power supply

3.3V

15

A21

I

Address wire

42

DQ11

I/O

Data/address bus

16

#WP/ACC

I

Write-protect/acceleration

41

DQ3

I/O

Data/address bus

17

RY/#BY

O

Busy signal output

40

DQ10

I/O

Data/address bus

18

A18

I

Address wire

39

DQ2

I/O

Data/address bus

19

A17

I

Address wire

38

DQ9

I/O

Data/address bus

20

A7

I

Address wire

37

DQ1

I/O

Data/address bus

21

A6

I

Address wire

36

DQ8

I/O

Data/address bus

22

A5

I

Address wire

35

DQ0

I/O

Data/address bus

23

A4

I

Address wire

34

#OE

I

Output is enabled

24

A3

I

Address wire

33

VSS

Power supply

Ground

25

A2

I

Address wire

32

#CE0

I

Piece choosing, it is low effective

26

A1

I

Address wire

31

A0

I

Address wire

27

#CE3

I

Piece choosing, it is low effective

30

#CE2

I

Piece choosing, it is low effective

28

#CE5

I

Piece choosing, it is low effective

29

#CE6

I

Piece choosing, it is low effective

The above is only the preferred embodiment of the present invention, is not intended to limit the utility model, for this field Technical staff for, various modifications and changes may be made to the present invention.Within the spirit and principle of the utility model, To should be included within the scope of protection of this utility model through creative any modification, equivalent replacement, improvement and so on.

Claims (5)

1. a kind of three-dimensional encapsulation NOR FLASH memory, a backplane level and multiple chips including stacking setting from bottom to up Layer；Each chip layer respectively includes a NOR FLASH chip；The backplane level is equipped with the pin for external connection, described The backplane level stacked and multiple chip layers expose electrical connection pin on periphery after encapsulating, cutting, and set in outer surface There is plating gold bonding wire；It plates gold bonding wire and the electrical connection pin exposed on one backplane level and multiple chip layers is subjected to phase It connects；It is characterized by:

Each chip layer respectively further comprises a fixed patch, and the fixed patch is double-sided adhesive structure, is set to affiliated chip The NOR FLASH chip of the adjacent chip layer in the NOR FLASH chip lower surface and lower section of layer or the upper surface of backplane level.

2. three-dimensional encapsulation NOR FLASH memory according to claim 1, which is characterized in that the backplane level includes bottom Plate and lead frame, the lead frame are fixed on the bottom plate, and the pin of the external connection is arranged in the lead On frame.

3. three-dimensional encapsulation NOR FLASH memory according to claim 2, which is characterized in that the bottom plate and lead frame Frame is an integral molding structure.

4. three-dimensional encapsulation NOR FLASH memory according to claim 2, which is characterized in that the bottom plate draws with described Wire frame is welded to connect.

5. three-dimensional encapsulation NOR FLASH memory described in any one according to claim 1~4, which is characterized in that described more A chip layer is eight chip layers, the data/address bus of the NOR FLASH chip of eight chip layers, address wire, write-protect/add Speed, reset signal, write enable signal, byte/word mode, busy number output, output enable signal line distinguish compound, chip selection signal Juxtaposition.