CN201436681U - Novel chip - Google Patents
Novel chip Download PDFInfo
- Publication number
- CN201436681U CN201436681U CN 200920006683 CN200920006683U CN201436681U CN 201436681 U CN201436681 U CN 201436681U CN 200920006683 CN200920006683 CN 200920006683 CN 200920006683 U CN200920006683 U CN 200920006683U CN 201436681 U CN201436681 U CN 201436681U
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- China
- Prior art keywords
- pad pin
- pin
- pad
- chip
- exposed pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dram (AREA)
Abstract
The utility model discloses a novel chip, including bonding pad pins and an exposed bonding pad, wherein the bonding pad pins are distributed in two circles on periphery of the exposed bonding pad. The bonding pad pins on periphery of the exposed bonding pad are increased to two circles in the chip under a condition of not influencing the chip property and the manufacturing technique so as to further increase the quantity of the bonding pad pins in a certain packaging size.
Description
Technical field
The utility model relates to electronic technology field, relates in particular to a kind of novel chip.
Background technology
Four sides do not have pin flat packaging (QFN, quad flat non-leaded package) be a kind of no pin package, packed chip generally is square or rectangle, packed die bottom surface middle position has an exposed pads that area is bigger, the absorption affinity that this exposed pads is mainly used to heat conduction and increases chip; At the conductive welding disk pin that the electric binding of a circle realization is arranged around this exposed pads.
See also Fig. 1, Fig. 1 is existing a kind of QFN bonding pads pin schematic diagram.As shown in Figure 1, be packaged with pad pin 1 and exposed pads 2 in the bottom surface of this QFN chip; Wherein, exposed pads 2 is positioned at the bottom surface middle position of this QFN chip, pad pin 1 be distributed in exposed pads 2 around, the circle that promptly distributes around exposed pads 2 is realized the pad pin 1 of electric binding.
The inventor finds in realizing process of the present utility model, under certain package dimension, if the increase of pad pin can't meet design requirement.Therefore, the quantity that how improves pin in the scope of certain size becomes the problem of those skilled in the art's primary study.
The utility model content
The utility model embodiment provides a kind of novel chip, can further increase the pad pin number under certain package dimension.
For achieving the above object, the utility model embodiment provides following technical scheme:
The utility model embodiment provides a kind of novel chip, comprising:
Pad pin and exposed pads;
Described pad pin is two circles and distributes around described exposed pads.
Preferably, described pad pin and exposed pads are positioned on the same plane of chip.
Preferably, the pad pin that is distributed on described exposed pads each circle all around is equally distributed.
Preferably, the pad pin between the circle of two around the described exposed pads distributes and is the W type.
The utility model embodiment provides another kind of novel chip, comprising:
Pad pin and exposed pads;
Described pad pin is two circles and distributes around described exposed pads;
Position relation between the described pad pin meets the locality condition that presets;
The described locality condition that presets comprises the spacing between the adjacent pad pin on the same circle, the spacing between the adjacent pad pin on the different circle;
Preferably, described pad pin and exposed pads are positioned on the same plane of chip.
Preferably, described pad pin is square or rectangular or two circular circle distributions around described exposed pads.
Preferably, the pad pin that is distributed on described exposed pads each circle all around is equally distributed.
Preferably, the pad pin between the circle of two around the described exposed pads distributes and is the W type.
Preferably, described pad pin comprises:
Pad pin VDD50 is connected with the 5V power supply;
Pad pin VDD33 is connected with the 3.3V power supply;
Pad pin VDD18 is connected with the 1.8V power supply;
Pad pin REXT is connected with non-essential resistance;
Pad pin DP is used for inputing or outputing of usb data;
Pad pin DM is used for inputing or outputing of usb data;
Pad pin VSS is connected with ground;
Pad pin XI is connected with crystal, is used for the input crystal frequency;
Pad pin XO is connected with crystal, is used to export crystal frequency;
Pad pin FWRN is used to write control;
Pad pin FALE is used for address control;
Pad pin WP is used for write-protect;
Pad pin FCLE is used for order control;
Pad pin FCEN is used for sheet and selects external chip;
Pad pin FRDN is used to read to enable;
Pad pin FRB is used to read sign;
Pad pin RESET is used to reset;
Pad pin FDATA0_0, FDATA0_1, FDATA0_2, FDATA0_3, FDATA0_4, FDATA0_5, FDATA0_6, FDATA0_7 is connected with the data wire of external chip respectively.
Compare with existing QFN chip, the novel chip that the utility model embodiment provides is under the condition that does not influence chip performance and production technology, pad pin around the exposed pads is increased to two circles, thereby under certain package dimension, can further increases the quantity of pad pin.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use among the embodiment below, apparently, accompanying drawing in describing below only is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is existing a kind of QFN bonding pads pin schematic diagram;
The pad pin schematic diagram of a kind of novel chip that Fig. 2 provides for the utility model embodiment one;
The pad pin schematic diagram of a kind of novel chip that Fig. 3 provides for the utility model embodiment two.
Embodiment
Below in conjunction with the accompanying drawing among the utility model embodiment, the technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment only is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the utility model protection.
Embodiment one:
See also Fig. 2, the pad pin schematic diagram of a kind of novel chip that Fig. 2 provides for the utility model embodiment one.As shown in Figure 2, the novel chip that provides of the utility model can comprise:
Described pad pin 1 is two circles and distributes around described exposed pads 2.
Particularly, described pad pin 1 and exposed pads 2 are positioned on the same plane of chip.
Particularly, described pad pin 1 is square or rectangular or two circular circle distributions around described exposed pads 2.
Particularly, the pad pin 1 that is distributed on described exposed pads 2 each circle all around is equally distributed.
Particularly, the pad pin between the circle of two around the described exposed pads distributes and is the W type.
The novel chip that the utility model embodiment one provides is increased to two circles with the pad pin 1 around the exposed pads 2, thereby can increases pin of chip quantity further under identical package dimension under the condition that does not influence chip performance and production technology; Perhaps, under identical number of pins, can further dwindle the encapsulation volume of chip.
Embodiment two:
See also Fig. 3, the pad pin schematic diagram of a kind of novel chip that Fig. 3 provides for the utility model embodiment two.As shown in Figure 3, the novel chip that provides of the utility model can comprise:
Described pad pin 1 is two circles and distributes around described exposed pads 2;
Position relation between the described pad pin 1 meets the locality condition that presets.
Particularly, described pad pin 1 and exposed pads 2 are positioned on the same plane of chip.
Particularly, described pad pin 1 is square or rectangular or two circular circle distributions around described exposed pads 2.
As shown in Figure 3, be distributed in exposed pads 2 pad pin all around and can constitute a pad pin circle, and, in the utility model embodiment, there are two pad pin circles around the exposed pads 2, pad pin circle and outer pad pin circle in can being called.
As shown in Figure 3, in the utility model embodiment, adopt W type mode to distribute between the pin on pin on the interior pad pin circle and the outer pad pin circle, pin on the promptly interior pad pin circle and the line between the pin on the outer pad pin circle have constituted the W type.Certainly, in the utility model embodiment, can take other distribution modes between the pin on pin on the interior pad pin circle and the outer pad pin circle, such as, can adopt alignment thereof distribution etc. between the pin on pin on the interior pad pin circle and the outer pad pin circle, the utility model embodiment does not limit at this.
Wherein, on the bottom surface of novel chip shown in Figure 3, the pad pin 1 that is distributed on described exposed pads 2 two pad pin circles all around is equally distributed.
As shown in Figure 3, the described locality condition that presets can comprise the spacing 3 between the adjacent pad pin on the same circle, the spacing 4 between the adjacent pad pin on the different circle, the locality condition that can also comprise other certainly is such as spacing between pad pin 1 and the chip edge or the like.
As shown in Figure 3, the novel chip that the utility model provides has comprised 48 pad pins, and the sequence number of pad pin is respectively 1,2,3 ..., 48; Wherein,
Sequence number is that 1 pad pin name is VDD50, and this pin is used for being connected with the 5V power supply;
Sequence number is that 2 pad pin name is VDD33, and this pin is used for being connected with the 3.3V power supply;
Sequence number is that 3 pad pin name is VDD18, and this pin is used for being connected with the 1.8V power supply;
Sequence number is that 4 pad pin name is VPP, and this pin is used for being connected with the 1.8V power supply;
Sequence number is that 5 pad pin name is REXT, and this pin is connected with non-essential resistance;
Sequence number is that 6 pad pin name is VD33, and this pin is used for being connected with the 3.3V power supply;
Sequence number is that 7 pad pin name is DP, and this pin is used for inputing or outputing of usb data;
Sequence number is that 8 pad pin name is DM, and this pin is used for inputing or outputing of usb data;
Sequence number is that 9 pad pin name is VSS, and this pin is connected with ground;
Sequence number is that 10 pad pin name is XI, and this pin is connected with crystal, is used for the input crystal frequency;
Sequence number is that 11 pad pin name is XO, and this pin is connected with crystal, is used to export crystal frequency;
Sequence number is that 12 pad pin name is VSSU, and this pin is connected with ground;
Sequence number is that 13 pad pin name is VDDU, and this pin is used for being connected with the 1.8V power supply;
Sequence number is that 14 pad pin name is TEST_MODE, and this pin is used to control test pattern;
Sequence number is that 15 pad pin name is FDATA1_7, and this pin is connected with the data wire of external chip;
Sequence number is that 16 pad pin name is FDATA1_6, and this pin is connected with the data wire of external chip;
Sequence number is that 17 pad pin name is VSS, and this pin is connected with ground;
Sequence number is that 18 pad pin name is FDATA1_5, and this pin is connected with the data wire of external chip;
Sequence number is that 19 pad pin name is FDATA1_4, and this pin is connected with the data wire of external chip;
Sequence number is that 20 pad pin name is FDATA1_3, and this pin is connected with the data wire of external chip;
Sequence number is that 21 pad pin name is FDATA1_2, and this pin is connected with the data wire of external chip;
Sequence number is that 22 pad pin name is FDATA1_1, and this pin is connected with the data wire of external chip;
Sequence number is that 23 pad pin name is FDATA1_0, and this pin is connected with the data wire of external chip;
Sequence number is that 24 pad pin name is X_LED, and this pin is connected with light-emitting diode;
Sequence number is that 25 pad pin name is FWRN, and this pin is used to write control;
Sequence number is that 26 pad pin name is FALE, and this pin is used for address control;
Sequence number is that 27 pad pin name is WP, and this pin is used for write-protect;
Sequence number is that 28 pad pin name is FCLE, and this pin is used for the order control number;
Sequence number is that 29 pad pin name is VDD33, and this pin is used for being connected with the 3.3V power supply;
Sequence number is that 30 pad pin name is CLKOFF, and this pin is used for clock input conversion;
Sequence number is that 31 pad pin name is FCEN0, and this pin is used for sheet and selects external chip;
Sequence number is that 32 pad pin name is FRDN, and this pin is used to read to enable;
Sequence number is that 33 pad pin name is FRB1, and this pin is used to read sign;
Sequence number is that 34 pad pin name is FCEN3, and this pin is used for sheet and selects external chip;
Sequence number is that 35 pad pin name is FCEN2, and this pin is used for sheet and selects external chip;
Sequence number is that 36 pad pin name is FCEN1, and this pin is used for sheet and selects external chip;
Sequence number is that 37 pad pin name is FRB0, and this pin is used to read control;
Sequence number is that 38 pad pin name is FDATA0_0, and this pin is connected with the data wire of external chip;
Sequence number is that 39 pad pin name is FDATA0_1, and this pin is connected with the data wire of external chip;
Sequence number is that 40 pad pin name is FDATA0_2, and this pin is connected with the data wire of external chip;
Sequence number is that 41 pad pin name is FDATA0_3, and this pin is connected with the data wire of external chip;
Sequence number is that 42 pad pin name is FDATA0_4, and this pin is connected with the data wire of external chip;
Sequence number is that 43 pad pin name is FDATA0_5, and this pin is connected with the data wire of external chip;
Sequence number is that 44 pad pin name is FDATA0_6, and this pin is connected with the data wire of external chip;
Sequence number is that 45 pad pin name is FDATA0_7, and this pin is connected with the data wire of external chip;
Sequence number is that 46 pad pin name is RST_OUT, and this pin is used to reset;
Sequence number is that 47 pad pin name is RESET, and this pin is used to reset;
Sequence number is that 48 pad pin name is VS33A, and this pin is connected with ground.
Need to prove that the utility model embodiment is that 48 QFN chip is an example with common pad number of pins just, introduces the novel chip that the utility model provides.According to the thought that the utility model provides, can also further increase the title and/or the function of pad pin or modification pad pin, the utility model does not limit at this.
If, the package dimension of the novel chip that the utility model embodiment provides is that length is that 5mm, width are 5mm, because the pad number of pins of this novel chip is 48, so the pad number of pins that is distributed on exposed pads 2 two pad pin circles all around can be 24 respectively; Again because the pad pin on each pad pin circle is evenly to divide other, so by calculating as can be known, the spacing 3 between the adjacent pad pin 1 on the same circle can be that the spacing 4 between the adjacent pad pin 1 on 0.65mm, the different circle can be 0.32mm.
Need to prove; the utility model embodiment is just to being convenient to introduction; position relation between concrete size, pad number of pins and the pad pin of the novel chip that is provided is provided; the technical scheme that provides according to the utility model; those skilled in the art can also obtain the QFN packaged chip of the position relation between other different sizes, different pad number of pins and the different pad pin, all belong to protection range of the present utility model.
The novel chip that the utility model embodiment two provides is increased to two circles with the pad pin 1 around the exposed pads 2, thereby can increases pin of chip quantity at identical package dimension under the condition that does not influence chip performance and production technology; Certainly, under identical number of pins, the novel chip that the utility model embodiment two provides can also further dwindle the encapsulation volume of chip.
More than a kind of novel chip provided by the utility model is described in detail, used specific case herein principle of the present utility model and execution mode are set forth, the explanation of above embodiment just is used for helping to understand the utility model and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present utility model, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as restriction of the present utility model.
Claims (10)
1. a novel chip is characterized in that, comprising:
Pad pin and exposed pads;
Described pad pin is two circles and distributes around described exposed pads.
2. novel chip according to claim 1 is characterized in that, described pad pin and exposed pads are positioned on the same plane of chip.
3. novel chip according to claim 1 is characterized in that, the pad pin that is distributed on described exposed pads each circle all around is equally distributed.
4. according to each described novel chip of claim 1 to 3, it is characterized in that the pad pin line between two circles around the described exposed pads is the W type.
5. a novel chip is characterized in that, comprising:
Pad pin and exposed pads;
Described pad pin is two circles and distributes around described exposed pads;
Position relation between the described pad pin meets the locality condition that presets;
The described locality condition that presets comprises the spacing between the adjacent pad pin on the same circle, the spacing between the adjacent pad pin on the different circle.
6. novel chip according to claim 5 is characterized in that, described pad pin and exposed pads are positioned on the same plane of chip.
7. novel chip according to claim 5 is characterized in that, described pad pin is square or rectangular around described exposed pads or two circular circles distribute.
8. novel chip according to claim 5 is characterized in that, the pad pin that is distributed on described exposed pads each circle all around is equally distributed.
9. according to each described novel chip of claim 5 to 8, it is characterized in that the pad pin line between two circles around the described exposed pads is the W type.
10. according to each described novel chip of claim 5 to 8, it is characterized in that described pad pin comprises:
Pad pin VDD50 is connected with the 5V power supply;
Pad pin VDD33 is connected with the 3.3V power supply;
Pad pin VDD18 is connected with the 1.8V power supply;
Pad pin REXT is connected with non-essential resistance;
Pad pin DP is used for inputing or outputing of usb data;
Pad pin DM is used for inputing or outputing of usb data;
Pad pin VSS is connected with ground;
Pad pin XI is connected with crystal, is used for the input crystal frequency;
Pad pin XO is connected with crystal, is used to export crystal frequency;
Pad pin FWRN is used to write control;
Pad pin FALE is used for address control;
Pad pin WP is used for write-protect;
Pad pin FCLE is used for order control;
Pad pin FCEN is used for sheet and selects external chip;
Pad pin FRDN is used to read to enable;
Pad pin FRB is used to read sign;
Pad pin RESET is used to reset;
Pad pin FDATA0_0, FDATA0_1, FDATA0_2, FDATA0_3, FDATA0_4, FDATA0_5, FDATA0_6, FDATA0_7 is connected with the data wire of external chip respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200920006683 CN201436681U (en) | 2009-03-31 | 2009-03-31 | Novel chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200920006683 CN201436681U (en) | 2009-03-31 | 2009-03-31 | Novel chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201436681U true CN201436681U (en) | 2010-04-07 |
Family
ID=42373129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200920006683 Expired - Lifetime CN201436681U (en) | 2009-03-31 | 2009-03-31 | Novel chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201436681U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956613A (en) * | 2011-08-26 | 2013-03-06 | 格罗方德半导体公司 | Bond pad configurations for controlling semiconductor chip package interactions |
| CN109994042A (en) * | 2019-04-11 | 2019-07-09 | 武汉华星光电技术有限公司 | Driving chip and display panel |
-
2009
- 2009-03-31 CN CN 200920006683 patent/CN201436681U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956613A (en) * | 2011-08-26 | 2013-03-06 | 格罗方德半导体公司 | Bond pad configurations for controlling semiconductor chip package interactions |
| CN102956613B (en) * | 2011-08-26 | 2016-02-10 | 格罗方德半导体公司 | For controlling the interactional bond pad arrangement of semiconductor chip package |
| CN109994042A (en) * | 2019-04-11 | 2019-07-09 | 武汉华星光电技术有限公司 | Driving chip and display panel |
| CN109994042B (en) * | 2019-04-11 | 2024-05-03 | 武汉华星光电技术有限公司 | Driving chip and display panel |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20100407 |