CN203339149U - QFN packaging structure - Google Patents
QFN packaging structure Download PDFInfo
- Publication number
- CN203339149U CN203339149U CN2013203717303U CN201320371730U CN203339149U CN 203339149 U CN203339149 U CN 203339149U CN 2013203717303 U CN2013203717303 U CN 2013203717303U CN 201320371730 U CN201320371730 U CN 201320371730U CN 203339149 U CN203339149 U CN 203339149U
- Authority
- CN
- China
- Prior art keywords
- chip
- chip layer
- packaging structure
- encapsulating structure
- heat radiation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
The utility model discloses a QFN packaging structure. The QFN packaging structure is characterized by comprising a copper support, an upper chip layer, a lower chip layer, multiple leads and insulation resin, wherein a central portion of the copper support is provided with a bare metal heat radiation disc, circumference of the copper support is provided with metal contacts instead of pins, the upper chip layer and the lower chip layer are piled on the metal heat radiation disc, the multiple leads are connected between the upper chip layer and the lower chip layer, and between the lower chip layer and the metal contacts, and the insulation resin is filled in a packaging space of the packaging structure. According to the QFN packaging structure, the metal contacts are used to replace the traditional pins, so impedance is reduced, chip information processing frequency is improved, moreover, the central bottom portion of the copper support is provided with the bare metal heat radiation disc, so rapid heat conduction during operation is facilitated, and a heat radiation effect is good.
Description
Technical field
The utility model belongs to logic semiconductor chip encapsulation technology field, is specifically related to a kind of small-size chips, without the logic chip QFN encapsulating structure of pin, rapid heat dissipation.
Background technology
The chip encapsulated in prior art is generally larger, more than 8*8mm, adopt the copper stent ground, pin is arranged, bottom does not have exposed heat dissipation plate can supply quick heat radiating, and to small size as the little chip below 3*3mm also continue to use the large scale encapsulating structure, do not have special encapsulating structure to solve poor radiation, problem that impedance is larger yet.
Summary of the invention
The purpose of this utility model is to provide and a kind ofly is applicable to small-size chips, without the logic chip QFN encapsulating structure of pin, rapid heat dissipation.
For realizing above-mentioned utility model purpose, the utility model has adopted following technical scheme:
A kind of QFN encapsulating structure, is characterized in that, comprising:
One copper stent, centre is designed with exposed heat dissipation metal dish, and surrounding is designed with the hard contact that substitutes pin;
At least one chip, be disposed on described copper stent, and described heat dissipation metal dish is pasted on the chip below;
Multiple conducting wires, be electrically connected between chip and hard contact; Wire can adopt gold thread.
The insulating resin of filling in the encapsulated space of encapsulating structure.
Further, described chip and chip or chip and copper stent adhesive tape bonding.
Further, the size≤3mm*3mm of described chip.
Make the technological process of above-mentioned QFN encapsulating structure, comprise the following steps:
Chip grinds with cutting-> chip-stacked-> gold thread welding-> resin and synthesizes-> electroplate-> cutting.
At first chip is ground to the thickness that encapsulation needs; and cut into discrete component; then connect chip and chip by adhesive tape; chip and copper stent; the welding gold thread, connect chip and substrate electronic circuit, inner each device of the synthetic whole cavity protection of resin; back metal contact and pad are zinc-plated, in order to better be connected with pcb board.In order to prevent the copper oxidation and to prevent resin and the copper stent delamination, application surface special processing technology in encapsulation process part technique, utilize nitrogen, hydrogen etc. and high-energy clean the copper stent surface impurity, the reduction surface oxidation, to reach the enhancing surface roughness, strengthen surface and resin-bonded power.
The utility model advantage:
QFN encapsulating structure described in the utility model replaces traditional pin with hard contact, can reduce impedance, improves chip information and processes frequency, simultaneously, the copper stent center bottom is designed with exposed heat dissipation metal dish, so that chip conducts fast heat, good heat dissipation effect when work.
The accompanying drawing explanation
The profile that Fig. 1 is the utility model QFN encapsulating structure;
The vertical view that Fig. 2 is the utility model QFN encapsulating structure.
Wherein, 1, heat dissipation metal dish; 2, chip; 3, hard contact; 4, gold thread; 5, insulating resin; 6, copper stent.
Embodiment
Below in conjunction with accompanying drawing and a preferred embodiment, the technical solution of the utility model is further described.
Embodiment:
As shown in Fig. 1～Fig. 2: a kind of QFN encapsulating structure comprises:
One copper stent 6, centre is designed with exposed heat dissipation metal dish 1, and surrounding is designed with the effect that hard contact 3 substitutes pin;
One chip 2, be disposed on described copper stent 6, and heat dissipation metal dish 1 is pasted on chip 2 belows;
Many gold threads 4, be electrically connected between chip 2 and hard contact 3;
The insulating resin 5 of filling in the encapsulated space of encapsulating structure.
Described chip 2 and copper stent 6 are used adhesive tape bonding.
Described chip 2 is of a size of 3mm*3mm.。
It is to be noted; as described above is only in order to explain the preferred embodiment of the utility model; not attempt is done any formal restriction to the utility model according to this; be with; all any modification or changes that the relevant the utility model of doing under identical utility model spirit is arranged, all must be included in the category that the utility model is intended to protection.
Claims (1)
1. a QFN encapsulating structure, is characterized in that, comprising:
One copper stent, centre is designed with exposed heat dissipation metal dish, and surrounding is designed with the hard contact that substitutes pin;
At least one chip, be disposed on described copper stent, and described heat dissipation metal dish is pasted on the chip below;
Multiple conducting wires, be electrically connected between chip and hard contact;
The insulating resin of filling in the encapsulated space of encapsulating structure.
2. QFN encapsulating structure according to claim 1, is characterized in that, described chip and chip or chip and copper stent adhesive tape bonding.
3. QFN encapsulating structure according to claim 2, is characterized in that, the size≤3mm*3mm of described chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203717303U CN203339149U (en) | 2013-06-26 | 2013-06-26 | QFN packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203717303U CN203339149U (en) | 2013-06-26 | 2013-06-26 | QFN packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203339149U true CN203339149U (en) | 2013-12-11 |
Family
ID=49707811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013203717303U Expired - Fee Related CN203339149U (en) | 2013-06-26 | 2013-06-26 | QFN packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203339149U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037182A (en) * | 2018-09-12 | 2018-12-18 | 深圳三地芯电子有限责任公司 | Chip-packaging structure and memory device |
-
2013
- 2013-06-26 CN CN2013203717303U patent/CN203339149U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037182A (en) * | 2018-09-12 | 2018-12-18 | 深圳三地芯电子有限责任公司 | Chip-packaging structure and memory device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10818637B2 (en) | Thin bonded interposer package | |
| CN107305875B (en) | Bidirectional semiconductor packaging part | |
| KR20150144178A (en) | Method of manufacturing the semiconductor package | |
| TW201240056A (en) | Semiconductor package and fabrication method thereof | |
| WO2014037815A3 (en) | Lead carrier with print-formed terminal pads | |
| TW201250942A (en) | Integrated circuit packaging system with routed circuit lead array and method of manufacture thereof | |
| CN105489571A (en) | Semiconductor package with cooling fin, and packaging method for semiconductor package | |
| CN204375722U (en) | A kind of semiconductor package | |
| CN201417765Y (en) | Base island free semi-conductor chip package structure | |
| CN206282838U (en) | The integrated encapsulation structure of passive device and active device | |
| CN201946588U (en) | Packaging structure for power semiconductors | |
| CN203339149U (en) | QFN packaging structure | |
| CN102646645B (en) | Packaging structure and manufacturing method thereof | |
| CN103094234A (en) | Extension pin Fan-out Panel Level ball grid array (BGA) package part and manufacture process thereof | |
| CN103354228A (en) | Semiconductor packaging part and manufacturing method thereof | |
| CN103094128A (en) | Fan-out Panel Level ball grid array (BGA) package part manufacture process | |
| CN206789535U (en) | A kind of fan-out package structure of power electronic devices | |
| CN105355567A (en) | Double-sided etching water drop salient point type package structure and process method thereof | |
| US20140284803A1 (en) | Semiconductor package and fabrication method thereof | |
| CN203118935U (en) | DFN (dual flat-pack no-lead) package structure for rectifier chip | |
| CN103441080A (en) | Chip front-mounting BGA encapsulating method | |
| CN203118936U (en) | Package structure for rectifier semiconductor chip | |
| CN202796930U (en) | Packaging body for metal-oxide-semiconductor field effect transistor (MOSFET) chip | |
| CN102376666B (en) | A kind of ball grid array package structure and manufacture method thereof | |
| CN112420649B (en) | Chip packaging structure and electronic product |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131211 Termination date: 20210626 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |