CN103094234A - Extension pin Fan-out Panel Level ball grid array (BGA) package part and manufacture process thereof - Google Patents
Extension pin Fan-out Panel Level ball grid array (BGA) package part and manufacture process thereof Download PDFInfo
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- CN103094234A CN103094234A CN2012105418467A CN201210541846A CN103094234A CN 103094234 A CN103094234 A CN 103094234A CN 2012105418467 A CN2012105418467 A CN 2012105418467A CN 201210541846 A CN201210541846 A CN 201210541846A CN 103094234 A CN103094234 A CN 103094234A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention discloses an extension pin Fan-out Panel Level ball grid array (BGA) package part and manufacture process thereof. The package part is mainly composed of a chip, a plastic package material, an insulation layer, metal copper, nickel porpezite, a solder ball, a soldering disk, a second insulation layer, a reversely-bonded chip, secondary metal copper distribution wires and a third insulation layer. The manufacture process comprises the following steps of thinning a wafer, scratching a wafer, reversely bonding a chip, plastically packing, tearing a film, turning, carrying out primary insulation treatment, punching holes first time, distributing copper wires first time, carrying out secondary insulation treatment, punching holes second time, distributing copper wires second time, carrying out third insulation treatment, punching holes third time, plating nickel porpezite, printing, reflow soldering and cutting. The manufacture process solve the wire cross problem, saves cost and improve electric performance and reliability of products.
Description
Technical field
The present invention relates to a kind of Fan-out Panel Level BGA packaging part and manufacture craft thereof of extended pin, belong to the semiconductor packaging field.
Background technology
Development along with technology; Electronic Packaging not only will provide the protection of chip; also to satisfy the requirements such as ever-increasing performance, reliability, heat radiation, power division under certain cost simultaneously; the increase of functional chip speed and disposal ability needs more number of pins, clock frequency and better power distribution faster.The market demand electronic product has greater functionality, longer battery life and less physical dimension, and adapted to leadless welding (protection of the environment) also effectively reduces costs.
Traditional QFN encapsulation technology need to be used lead frame and bonding wire, and not only packaging cost is higher to a certain extent, and package thickness is larger, can not satisfy many pins, high density, the small-sized slimming requirement of electronic product.
Fan-in Panel BGA encapsulation technology is compared traditional encapsulation technology, although reduced to a certain extent package thickness, reduced cost, but its sphere gap and I/O number can not satisfy the higher number of pins of encapsulating products and better performance requirement due to the restriction that is subject to chip size.
And for general Fan-out Panel BGA encapsulation technology, although overcome the Cost Problems of traditional Q FN encapsulation technology and the chip size restricted problem of Fan-in Panel BGA encapsulation, but in encapsulation process, have the many problems of crossing elimination during due to individual layer plane copper cabling, the output pin bit quantity can be restricted.
Fan-out Panel Level BGA encapsulation and number of pins extended method thereof have overcome current
The cost that encapsulation exists, chip size restriction and crossing elimination problem have obvious technical advantage, can realize many pins, high density, small-sized slimming encapsulation, have thermal diffusivity, electrical property
And the characteristics such as coplanarity is good.
Summary of the invention
the object of the invention is to overcome the deficiency of conventional package technology, develop a kind of Fan-out Panel Level BGA packaging part and manufacture craft thereof of extended pin, this technology has solved the crossing elimination problem, adopt the double layer planar cabling, can make the output cabling form stereoscopic-state, thereby to the output pin position expanding, it does not use lead frame, PCB, do not use the metal bonding wire, reduced packaging cost, package dimension reduces greatly, adopt and do eye location technology and punching copper wiring technique on glued membrane, make joint efficiency higher, electric current and signal transmission distance have been shortened, electrical property and product reliability have been improved.
Technical scheme of the present invention is: a kind of Fan-out Panel Level BGA packaging part of extended pin, and mainly by chip, plastic packaging material, insulating barrier, metallic copper, NiPdAu, tin ball, pad, insulating barrier, the wiring of secondary metals copper for the second time, insulating barrier forms for the third time.described chip and two-sided glued membrane are bonding, described chip is by the plastic packaging material plastic packaging, on described chip, pad is arranged, described chip has insulating barrier, pad and insulating barrier are adjacent, the insulating barrier at described pad place is porose, the place, hole is coated with metallic copper, there is insulating barrier for the second time at insulating barrier and metallic copper place, insulating barrier is corresponding for the second time metallic copper place is porose, the place, hole is coated with the wiring of secondary metals copper, insulating barrier and wiring place of secondary metals copper for the second time has insulating barrier for the third time, direct corresponding metallic copper place and wiring place of secondary metals copper of insulating barrier for the third time is porose, be coated with NiPdAu at hole wall, the tin ball that the NiPdAu place has Reflow Soldering to form.
Described manufacture craft is carried out according to following steps: core, plastic packaging, dyestripping and upset in wafer attenuate, Wafer Dicing, upside-down mounting, insulation processing, punching for the first time and copper wiring for the first time, insulation processing, punching for the second time and copper wiring for the second time, insulation processing, punching for the third time and nickel plating porpezite, printing and Reflow Soldering, cutting for the third time.
The invention has the beneficial effects as follows: (1) this invention packaging part has solved the crossing elimination problem, adopts the double layer planar cabling, can make the output cabling form stereoscopic-state, thereby to the output pin position expanding; (2) this packaging part does not need lead frame, without routing, has saved to a certain extent cost, has satisfied the miniaturization, slimming of encapsulating products, the lower requirements such as warpage rate; (3) this packaging part cloth line position is flexible, and tin sphere gap and I/O are not subjected to the restriction of die size, and product has more I/O number and better electrical property, has shortened electric current and signal transmission distance, has improved electrical property and product reliability.The present invention is environment-friendly type Advanced Packaging unleaded, halogen, can be applicable on wider movement, consumption electronic product, satisfy the portable e-machine in mobile communication and mobile computer field, as the needs of the ultrathin electronic products such as PDA, 3G mobile, MP3, MP4, MP5 development, it is a kind of novel encapsulated technology that shoots up.
Figure of description
Core profile in Fig. 1 upside-down mounting;
Fig. 2 plastic packaging profile;
Fig. 3 dyestripping with unload profile after body;
Profile after Fig. 4 Rotate 180 ℃;
Fig. 5 primary insulation processing profiles figure;
Fig. 6 once punches, copper wiring profile;
Fig. 7 secondary insulating processing profiles figure;
The punching of Fig. 8 secondary, copper wiring profile;
Fig. 9 is the insulation processing profile for the third time;
Figure 10 punches for the third time, nickel plating porpezite profile;
Figure 11 steel mesh brush tin cream profile;
Profile after Figure 12 Reflow Soldering.
In figure, 1 is that chip, 2 connects up, 13 is insulating barrier for the third time for secondary metals copper for pyroceram, 12 for tin cream, 11 for insulating barrier for the second time, 10 for pad, 9 for two-sided glued membrane, 8 for tin ball, 7 for NiPdAu, 6 for metallic copper, 5 for insulating barrier, 4 for plastic packaging material, 3.
Embodiment
Below in conjunction with accompanying drawing, the present invention is done and be described in further detail.
As shown in the figure, a kind of Fan-out Panel Level BGA packaging part of extended pin is mainly by chip 1, plastic packaging material 2, insulating barrier 3, metallic copper 4, NiPdAu 5, tin ball 6, pad 8, insulating barrier 9, secondary metals copper wiring 12 for the second time, insulating barrier 13 forms for the third time.described chip 1 bonds on two-sided glued membrane 7 by core in upside-down mounting, wherein the another side of two-sided glued membrane 7 and pyroceram 11 are bonding, described chip 1 carries out plastic packaging with plastic packaging material 2 subsequently, then manually tearing the related pyroceram 11 of two-sided glued membrane 7 removes in the lump, the chip integrated overturn 180 that plastic packaging is good is spent again, chip 1 is faced up, layer of cloth 3 on the good chip 1 of described plastic packaging, carry out insulation processing, insulating barrier 3 punchings to pad 8 places, at punching place plating copper 4, signal and the current channel of copper wiring forming circuit, then apply insulating barrier 9 for the second time, carrying out secondary insulating processes, part copper wiring place of insulating barrier 9 is for the second time punched for the second time, carry out secondary metals copper wiring 12 in secondary punching place, then, apply insulating barrier 13 for the third time, punch for the third time in copper wiring corresponding position at insulating barrier for the second time 9 and insulating barrier 13 for the third time, and at hole wall nickel plating porpezite 5, the signal of forming circuit and current channel, then carry out steel mesh brush tin cream 10, form tin ball 6 after Reflow Soldering, carry out at last the product cutting.
As shown in the figure, a kind of manufacture craft of Fan-out Panel Level BGA packaging part of extended pin, specifically carry out according to following steps:
The first step, wafer attenuate: the reduced thickness of wafer is between 250 μ m～200 μ m;
Second step, Wafer Dicing: adopt common scribing process;
The 3rd step, core in upside-down mounting: in upside-down mounting before core, two-sided glued membrane 7 is sticked on surperficial smooth enough, smooth pyroceram 11, wherein, the bondline thickness of two-sided glued membrane 7 is unsuitable large, must be less than 3um, two-sided glued membrane 7 is positive needs in advance core position on mark, sets up eyespot, on the two-sided glued membrane 7 that core in chip 1 upside-down mounting is supported to pyroceram 11;
The 4th step, plastic packaging: the chip 1 use plastic packaging material 2 that core in upside-down mounting is good carries out plastic packaging, and the plastic packaging zone should less than the glued membrane area, facilitate dyestripping;
The 5th step, dyestripping and upset: manual dyestripping, related pyroceram 11 removes in the lump, and the glue-line that cleans in case of necessity chip 1 front is residual, then chip 1 integrated overturn 180 degree that plastic packaging is good;
The 6th step, insulation processing for the first time: positive and be coated with insulating layer coating 3 on plastic packaging material 2 on every side at chip 1, cover chip 1 and plastic packaging material 2 surfaces around it;
The 7th step, punching for the first time and copper wiring: corresponding with the position of chip 1 pad 8, punching on insulating barrier 3, then at hole wall and plating copper 4 on every side thereof, concrete technology can be with reference to the PCB manufacturing process, get hold of aperture type, pore size and aperture quantity, copper deposition technique requirement etc., signal and the current channel of copper wiring forming circuit;
The 8th step, insulation processing for the second time: apply insulating material on insulating barrier 3 and metallic copper 4, form insulating barrier 9 for the second time;
The 9th step, punching for the second time and copper wiring; Corresponding with metallic copper 4 wirings on insulating barrier 9 for the second time, punching on insulating barrier 9 for the second time, and around hole wall copper plate, form secondary metals copper and connect up 12;
The tenth step, insulation processing for the third time: apply insulating material in insulating barrier 9 for the second time and secondary metals copper wiring 12, form insulating barrier 13 for the third time;
The 11 step, punching and nickel plating porpezite for the third time: in insulating barrier for the second time 9 and the copper wiring layer corresponding position punching of insulating barrier 13 for the third time, make the wiring of output copper form stereoscopic-state, expansion output pin position is then at hole wall nickel plating porpezite 5;
The 12 step, printing and Reflow Soldering: carry out steel mesh brush tin cream 10 on NiPdAu 5 coats of insulating barrier for the second time 9 and insulating barrier 13 for the third time, then carry out Reflow Soldering, form tin ball 6;
The 13 step, cutting: the product after backflow is cut into dish (pipe).
Claims (2)
1. the Fan-out Panel Level BGA packaging part of an extended pin is characterized in that: mainly by chip (1), plastic packaging material (2), insulating barrier (3), metallic copper (4), NiPdAu (5), tin ball (6), pad (8), insulating barrier (9), secondary metals copper wiring (12) for the second time, insulating barrier (13) forms for the third time, described chip (1) is bonding with two-sided glued membrane (7), described chip (1) is by plastic packaging material (2) plastic packaging, pad (8) is arranged on described chip (1), described chip (1) has insulating barrier (3), pad (8) is adjacent with insulating barrier (3), the insulating barrier (3) that described pad (8) is located is porose, the place, hole is coated with metallic copper (4), insulating barrier (3) and metallic copper (4) have been located insulating barrier (9) for the second time, the metallic copper (4) that insulating barrier (9) is corresponding is for the second time located porose, the place, hole is coated with secondary metals copper wiring (12), insulating barrier (13) has for the third time been located in insulating barrier (9) and secondary metals copper wiring (12) for the second time, the direct corresponding metallic copper (4) of insulating barrier (13) is located to locate porose with secondary metals copper wiring (12) for the third time, be coated with NiPdAu (5) at hole wall, NiPdAu (5) is located the tin ball (6) that Reflow Soldering forms.
2. the manufacture craft of the Fan-out Panel Level BGA packaging part of an extended pin is characterized in that: specifically carry out according to following steps:
The first step, wafer attenuate: the reduced thickness of wafer is between 250 μ m～200 μ m;
Second step, Wafer Dicing: adopt common scribing process;
The 3rd step, core in upside-down mounting: in upside-down mounting before core, two-sided glued membrane (7) is sticked on surperficial smooth enough, smooth pyroceram (11), wherein, the bondline thickness of two-sided glued membrane (7) is unsuitable large, must be less than 3um, two-sided glued membrane (7) is positive needs in advance core position on mark, sets up eyespot, with core in chip (1) upside-down mounting to the two-sided glued membrane (7) of pyroceram (11) support;
The 4th step, plastic packaging: the chip that core in upside-down mounting is good (1) carries out plastic packaging with plastic packaging material (2), and the plastic packaging zone should less than the glued membrane area, facilitate dyestripping;
The 5th step, dyestripping and upset: manual dyestripping, related pyroceram (11) removes in the lump, cleans in case of necessity the positive glue-line of chip (1) residual, then the chip that plastic packaging is good (1) integrated overturn 180 degree;
The 6th step, insulation processing for the first time: positive and be coated with insulating layer coating (3) on plastic packaging material (2) on every side at chip (1), cover chip (1) and plastic packaging material (2) surface around it;
The 7th step, punching and copper wiring for the first time: corresponding with the position of chip (1) pad (8), punch insulating barrier (3) is upper, then at hole wall and plating copper (4) on every side thereof;
The 8th step, insulation processing for the second time: at the upper insulating material that applies of insulating barrier (3) and metallic copper (4), form insulating barrier (9) for the second time;
The 9th step, punching for the second time and copper wiring; Corresponding with metallic copper (4) wiring on insulating barrier (9) for the second time, in the upper punching of insulating barrier (9) for the second time, and around hole wall copper plate, form secondary metals copper connect up (12);
The tenth step, insulation processing for the third time: at insulating barrier (9) and the upper insulating material that applies of secondary metals copper wiring (12) for the second time, form insulating barrier (13) for the third time;
The 11 step, punching and nickel plating porpezite for the third time: in insulating barrier (9) for the second time and the copper wiring layer corresponding position punching of insulating barrier (13) for the third time, make the wiring of output copper form stereoscopic-state, expansion output pin position is then at hole wall nickel plating porpezite (5);
The 12 step, printing and Reflow Soldering: carry out steel mesh brush tin cream (10) on NiPdAu (5) coat of insulating barrier (9) for the second time and insulating barrier (13) for the third time, then carry out Reflow Soldering, form tin ball (6);
The 13 step, cutting: the product after backflow is cut into dish (pipe).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210541846.7A CN103094234B (en) | 2012-12-14 | 2012-12-14 | The fan-out-type panel grade BGA package part and its manufacture craft of a kind of extended pin |
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| CN201210541846.7A CN103094234B (en) | 2012-12-14 | 2012-12-14 | The fan-out-type panel grade BGA package part and its manufacture craft of a kind of extended pin |
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| CN103094234B CN103094234B (en) | 2018-06-19 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104754856A (en) * | 2013-12-30 | 2015-07-01 | 深圳市共进电子股份有限公司 | Method for arranging solder ball on printed circuit board |
| CN109023277A (en) * | 2018-08-29 | 2018-12-18 | 江苏长电科技股份有限公司 | A kind of magnetically controlled sputter method of BGA package electronic product |
| CN109155476A (en) * | 2017-01-06 | 2019-01-04 | 卓英社有限公司 | Metal pad interface |
| TWI706522B (en) * | 2017-12-14 | 2020-10-01 | 南韓商三星電子股份有限公司 | Fan-out semiconductor package |
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| JP2008227355A (en) * | 2007-03-15 | 2008-09-25 | Shinko Electric Ind Co Ltd | Electronic equipment and method for manufacturing the same |
| CN102194717A (en) * | 2010-03-09 | 2011-09-21 | 新科金朋有限公司 | Semiconductor device and method of forming insulating layer around semiconductor die |
| US20120211886A1 (en) * | 2011-02-21 | 2012-08-23 | ISC8 Inc. | Method for Fabricating a Small Footprint Chip-Scale Package and a Device Made from the Method |
| CN203260569U (en) * | 2012-12-14 | 2013-10-30 | 华天科技（西安）有限公司 | Pin extended fan-in diffusion panel type BGA package |
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| CN1767184A (en) * | 2005-09-09 | 2006-05-03 | 威盛电子股份有限公司 | Embedded packaging structure and its packaging method |
| JP2008227355A (en) * | 2007-03-15 | 2008-09-25 | Shinko Electric Ind Co Ltd | Electronic equipment and method for manufacturing the same |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104754856A (en) * | 2013-12-30 | 2015-07-01 | 深圳市共进电子股份有限公司 | Method for arranging solder ball on printed circuit board |
| CN104754856B (en) * | 2013-12-30 | 2018-05-01 | 深圳市共进电子股份有限公司 | The method that tin ball is set on a printed circuit |
| CN109155476A (en) * | 2017-01-06 | 2019-01-04 | 卓英社有限公司 | Metal pad interface |
| TWI706522B (en) * | 2017-12-14 | 2020-10-01 | 南韓商三星電子股份有限公司 | Fan-out semiconductor package |
| CN109023277A (en) * | 2018-08-29 | 2018-12-18 | 江苏长电科技股份有限公司 | A kind of magnetically controlled sputter method of BGA package electronic product |
| CN109023277B (en) * | 2018-08-29 | 2020-09-08 | 江苏长电科技股份有限公司 | Magnetron sputtering method for BGA packaged electronic product |
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| CN103094234B (en) | 2018-06-19 |
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