CN103094128A - Fan-out Panel Level ball grid array (BGA) package part manufacture process - Google Patents
Fan-out Panel Level ball grid array (BGA) package part manufacture process Download PDFInfo
- Publication number
- CN103094128A CN103094128A CN2012105425598A CN201210542559A CN103094128A CN 103094128 A CN103094128 A CN 103094128A CN 2012105425598 A CN2012105425598 A CN 2012105425598A CN 201210542559 A CN201210542559 A CN 201210542559A CN 103094128 A CN103094128 A CN 103094128A
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- Prior art keywords
- chip
- plastic packaging
- glued membrane
- insulating layer
- core
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
Abstract
The invention discloses a Fan-out Panel Level ball grid array (BGA) package part manufacture process. The manufacture process comprises the following steps of thinning a wafer, scratching a wafer, reversely bonding a chip, plastically packing, tearing a film, turning, carrying out primary insulation treatment, punching holes, distributing copper wires, carrying out secondary insulation treatment, punching holes, plating nickel porpezite, printing, reflow soldering and cutting. Compared with traditional package technique, the manufacture process saves cost, can achieve multi-pin, high-density, small and thin package and has the advantages of being good in radiation, electric performance and coplanarity and the like.
Description
Technical field
The present invention relates to a kind of manufacture craft of Fan-out Panel Level BGA packaging part, belong to the semiconductor packaging field.
Background technology
The Electronic Packaging of today not only will provide the protection of chip; also to satisfy the requirements such as ever-increasing performance, reliability, heat radiation, power division under certain cost simultaneously; the increase of functional chip speed and disposal ability needs more number of pins, clock frequency and better power distribution faster.The market demand electronic product has greater functionality, longer battery life and less physical dimension, and adapted to leadless welding (protection of the environment) also effectively reduces costs.
Traditional QFN encapsulation technology need to be used lead frame and bonding wire, and not only packaging cost is higher to a certain extent, and package thickness is larger, can not satisfy many pins, high density, the small-sized slimming requirement of electronic product.
Fan-in Panel BGA encapsulation technology is compared traditional encapsulation technology, although reduced to a certain extent package thickness, reduced cost, but its sphere gap and I/O number can not satisfy the higher number of pins of encapsulating products and better performance requirement due to the restriction that is subject to chip size.
Summary of the invention
The object of the invention is to overcome the deficiency of conventional package technology, develop a kind of manufacture craft of Fan-out Panel Level BGA packaging part, this technology is not used lead frame, PCB, do not use the metal bonding wire, reduced packaging cost, package dimension reduces greatly, adopt and do eye location technology and punching copper step line technology on glued membrane, make joint efficiency higher, shortened electric current and signal transmission distance, improved electrical property and product reliability.
A kind of Fan-out Panel Level BGA packaging part comprises chip, plastic packaging material, insulating material, metallic copper, NiPdAu, tin ball.
technical scheme of the present invention is: described manufacture craft is carried out according to following steps: described chip bonds on two-sided glued membrane by core in upside-down mounting, wherein the another side of two-sided glued membrane and pyroceram are bonding, described chip carries out plastic packaging subsequently, then manually the related high-temperature resistant carrier of dyestripping removes in the lump, the chip integrated overturn 180 that plastic packaging is good is spent again, chip front side up, at the good chip top plating insulating barrier of described plastic packaging, carry out insulation processing, after insulating barrier punching for pad PAD place, carry out metal copper facing in insulating barrier punching place, signal and the current channel of copper cabling forming circuit, then carrying out secondary insulating processes, copper cabling place to the second insulating barrier carries out the secondary punching, at secondary punching place nickel plating porpezite, the signal of forming circuit and current channel, then carry out steel mesh brush tin cream, Reflow Soldering, carry out at last the product cutting.
The invention has the beneficial effects as follows: (1) this invention packaging part does not need lead frame, without routing, has saved to a certain extent cost, has satisfied the miniaturization, slimming of encapsulating products, the lower requirements such as warpage rate; (2) the cloth line position is flexible, and tin sphere gap and I/O are not subjected to the restriction of die size, and product has more I/O number and better electrical property and heat dispersion, has shortened electric current and signal transmission distance, has improved electrical property and product reliability.The present invention is environment-friendly type Advanced Packaging unleaded, halogen, can be applicable on wider movement, consumption electronic product, satisfy the portable e-machine in mobile communication and mobile computer field, as the needs of the ultrathin electronic products such as PDA, 3G mobile, MP3, MP4, MP5 development, it is a kind of novel encapsulated technology that shoots up.
Figure of description
Core profile in Fig. 1 upside-down mounting;
Fig. 2 plastic packaging profile;
Fig. 3 dyestripping with unload profile after body;
Profile after Fig. 4 Rotate 180 ℃;
Fig. 5 insulation processing profile;
Fig. 6 punching, copper wiring profile;
Fig. 7 secondary insulating profile;
Fig. 8 punching, nickel plating porpezite profile;
Fig. 9 steel mesh brush tin cream profile;
Profile after Figure 10 Reflow Soldering.
In figure, 1 is that chip, 2 is that plastic packaging material, 3 is that insulating barrier, 4 is that metallic copper, 5 is that NiPdAu, 6 is that tin ball, 7 is that two-sided glued membrane, 8 is that pad, 9 is that secondary insulating layer, 10 is that tin cream, 11 is pyroceram.
Embodiment
Below in conjunction with accompanying drawing, the present invention is done and be described in further detail.
As shown in the figure: a kind of manufacture craft of Fan-out Panel Level BGA packaging part, it carries out in accordance with the following steps:
The first step, wafer attenuate: adopt and prevent that fragment technique is thinned to specific thickness;
Second step, Wafer Dicing: the thickness 150 above wafers of μ m adopt common scribing process, and thickness adopts double-pole scribing machine and technique thereof at the 150 following wafers of μ m;
The 3rd step, core in upside-down mounting: in upside-down mounting before core, two-sided glued membrane 7 is sticked on surperficial smooth enough, smooth pyroceram 11, wherein, the bondline thickness of two-sided glued membrane 7 is unsuitable large, must be less than 3um, glued membrane is positive needs in advance core position on mark, sets up eyespot, on the two-sided glued membrane 7 that core in chip 1 upside-down mounting is supported to pyroceram 11;
The 4th step, plastic packaging: the chip 1 use plastic packaging material 2 that core in upside-down mounting is good carries out plastic packaging, and the plastic packaging zone should less than the glued membrane area, facilitate dyestripping;
The 5th step, dyestripping and upset: manual dyestripping, related pyroceram 11 removes in the lump, and the glue-line that cleans in case of necessity chip 1 front is residual, then chip 1 integrated overturn 180 degree that plastic packaging is good;
The 6th step, primary insulation are processed: positive and be coated with insulating layer coating 3 on plastic packaging material 2 on every side at chip 1, cover chip 1 and plastic packaging material 2 surfaces around it;
The 7th step, punching and copper wiring: corresponding with the position of the pad 8 of chip 1, punching on insulating barrier 3, and then hole wall and plating copper 4 on every side thereof, concrete technology can be with reference to the PCB manufacturing process, get hold of aperture type, pore size and aperture quantity, copper deposition technique requirement etc., signal and the current channel of copper wiring forming circuit;
The 8th step, secondary insulating are processed: apply the secondary insulating material on insulating barrier 3 and metallic copper 4, form secondary insulating layer 9;
The 9th step, punching and nickel plating porpezite: corresponding with the metallic copper 4 below secondary insulating layer 9, punching on secondary insulating layer 9, and plate one deck NiPdAu 5 around hole wall;
The tenth step, printing and Reflow Soldering: carry out steel mesh brush tin cream 10 on the NiPdAu 5 of secondary insulating layer 9, then carry out Reflow Soldering, form tin ball 6;
Product after the 11 step, cutting reflux is cut into dish (pipe).
Claims (1)
1. the manufacture craft of a Fan-out Panel Level BGA packaging part, it is characterized in that: it carries out in accordance with the following steps:
The first step, wafer attenuate: adopt and prevent that fragment technique is thinned to specific thickness;
Second step, Wafer Dicing: the thickness 150 above wafers of μ m adopt common scribing process, and thickness adopts double-pole scribing machine and technique thereof at the 150 following wafers of μ m;
The 3rd step, core in upside-down mounting: in upside-down mounting before core, two-sided glued membrane (7) is sticked on surperficial smooth enough, smooth pyroceram (11), wherein, the bondline thickness of two-sided glued membrane (7) is unsuitable large, must be less than 3um, glued membrane is positive needs in advance core position on mark, sets up eyespot, with core in chip (1) upside-down mounting to the two-sided glued membrane (7) of pyroceram (11) support;
The 4th step, plastic packaging: the chip that core in upside-down mounting is good (1) carries out plastic packaging with plastic packaging material (2), and the plastic packaging zone should less than the glued membrane area, facilitate dyestripping;
The 5th step, dyestripping and upset: manual dyestripping, related pyroceram (11) removes in the lump, cleans in case of necessity the positive glue-line of chip (1) residual, then the chip that plastic packaging is good (1) integrated overturn 180 degree;
The 6th step, primary insulation are processed: positive and be coated with insulating layer coating (3) on plastic packaging material (2) on every side at chip (1), cover chip (1) and plastic packaging material (2) surface around it;
The 7th step, punching and copper wiring: corresponding with the position of the pad (8) of chip (1), punch insulating barrier (3) is upper, and then hole wall and plating copper (4) on every side thereof;
The 8th step, secondary insulating are processed: at the upper secondary insulating material that applies of insulating barrier (3) and metallic copper (4), form secondary insulating layer (9);
The 9th step, punching and nickel plating porpezite: corresponding with the metallic copper (4) below secondary insulating layer (9), in the upper punching of secondary insulating layer (9), and plate one deck NiPdAu (5) around hole wall;
The tenth step, printing and Reflow Soldering: carry out steel mesh brush tin cream (10) on the NiPdAu (5) of secondary insulating layer (9), then carry out Reflow Soldering, form tin ball (6);
Product after the 11 step, cutting reflux is cut into dish (pipe).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105425598A CN103094128A (en) | 2012-12-15 | 2012-12-15 | Fan-out Panel Level ball grid array (BGA) package part manufacture process |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012105425598A CN103094128A (en) | 2012-12-15 | 2012-12-15 | Fan-out Panel Level ball grid array (BGA) package part manufacture process |
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| CN103094128A true CN103094128A (en) | 2013-05-08 |
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| CN2012105425598A Pending CN103094128A (en) | 2012-12-15 | 2012-12-15 | Fan-out Panel Level ball grid array (BGA) package part manufacture process |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105603497A (en) * | 2016-03-14 | 2016-05-25 | 武汉欧普兰光电技术股份有限公司 | Semiconductor wafer electroplating clamping device, clamping method and electroplating process thereof |
| CN109023277A (en) * | 2018-08-29 | 2018-12-18 | 江苏长电科技股份有限公司 | A kind of magnetically controlled sputter method of BGA package electronic product |
| CN112672539A (en) * | 2020-12-07 | 2021-04-16 | 苏州浪潮智能科技有限公司 | Circuit board chip packaging device and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101202265A (en) * | 2006-08-30 | 2008-06-18 | 三洋电机株式会社 | Packaging board, semiconductor module, and portable apparatus |
| CN101477955A (en) * | 2008-01-04 | 2009-07-08 | 南茂科技股份有限公司 | Encapsulation structure and method for tablet reconfiguration |
| CN102194717A (en) * | 2010-03-09 | 2011-09-21 | 新科金朋有限公司 | Semiconductor device and method of forming insulating layer around semiconductor die |
| US20120049388A1 (en) * | 2010-08-31 | 2012-03-01 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Adhesive Material Over Semiconductor Die and Carrier to Reduce Die Shifting During Encapsulation |
-
2012
- 2012-12-15 CN CN2012105425598A patent/CN103094128A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101202265A (en) * | 2006-08-30 | 2008-06-18 | 三洋电机株式会社 | Packaging board, semiconductor module, and portable apparatus |
| CN101477955A (en) * | 2008-01-04 | 2009-07-08 | 南茂科技股份有限公司 | Encapsulation structure and method for tablet reconfiguration |
| CN102194717A (en) * | 2010-03-09 | 2011-09-21 | 新科金朋有限公司 | Semiconductor device and method of forming insulating layer around semiconductor die |
| US20120049388A1 (en) * | 2010-08-31 | 2012-03-01 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Adhesive Material Over Semiconductor Die and Carrier to Reduce Die Shifting During Encapsulation |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105603497A (en) * | 2016-03-14 | 2016-05-25 | 武汉欧普兰光电技术股份有限公司 | Semiconductor wafer electroplating clamping device, clamping method and electroplating process thereof |
| CN105603497B (en) * | 2016-03-14 | 2018-09-11 | 武汉欧普兰光电技术股份有限公司 | A kind of semiconductor crystal wafer plating clamping device, clamp method and its electroplating technology |
| CN109023277A (en) * | 2018-08-29 | 2018-12-18 | 江苏长电科技股份有限公司 | A kind of magnetically controlled sputter method of BGA package electronic product |
| CN109023277B (en) * | 2018-08-29 | 2020-09-08 | 江苏长电科技股份有限公司 | Magnetron sputtering method for BGA packaged electronic product |
| CN112672539A (en) * | 2020-12-07 | 2021-04-16 | 苏州浪潮智能科技有限公司 | Circuit board chip packaging device and method |
| CN112672539B (en) * | 2020-12-07 | 2022-06-10 | 苏州浪潮智能科技有限公司 | Circuit board chip packaging device and method |
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Application publication date: 20130508 |
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