CN102194708A - Thin encapsulation process - Google Patents
Thin encapsulation process Download PDFInfo
- Publication number
- CN102194708A CN102194708A CN2010101487098A CN201010148709A CN102194708A CN 102194708 A CN102194708 A CN 102194708A CN 2010101487098 A CN2010101487098 A CN 2010101487098A CN 201010148709 A CN201010148709 A CN 201010148709A CN 102194708 A CN102194708 A CN 102194708A
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- Prior art keywords
- lead frame
- chip
- technology
- encapsulation
- pin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention relates to a thin encapsulation process. The thin encapsulation process comprises the following steps of: manufacturing a lead wire frame which comprises a welding disk and a pin; arranging a chip on the lead wire frame; electrically connecting the chip and the pin of the lead wire frame; encapsulating the lead wire frame and the chip so as to form an encapsulated body, electroplating an exposed part of the encapsulated bottom and cutting the encapsulated body; and the process is characterized in that: after encapsulation, the encapsulated body is thinned. The thick lead wire frame is used for installing and encapsulating the chip, so that the encapsulation quality and the safety of the chip can be guaranteed; after encapsulation is finished, the lead wire frame is thinned, and the thinned lead wire frame has no influence on the encapsulation process, and effectively reduces the size and the weight of semiconductor encapsulation; furthermore, the process can be applied to encapsulation of exposed welding disks and non-exposed welding disks, and can be applied flexibly and conveniently.
Description
Technical field
The present invention relates to a kind of packaging technology, relate in particular to a kind of slim packaging technology.
Background technology
Modern society, the utilization of electronic product is increasingly extensive, especially on the market of information technology and portable product, people are when paying close attention to the electronic product function, also more pay attention to light, the miniaturization of product, thereby people have carried out a large amount of research to the small size and the light weight of semiconductor packages at present.
Disclose a kind of slim encapsulating structure as Chinese patent publication number CN201319380, comprised a pedestal, had at least one fluting; A plurality of pins are positioned at the pedestal below; And at least one chip, be positioned at fluting, and by a plurality of metal couplings and pin formation electric connection, on the inner surface of fluting a reflector is arranged, the coating metal in reflector is tin, silver or green, and metal coupling is copper, nickel, billon, can cover on the pedestal and cover the layer of metal layer, pedestal is interior and have the dielectric medium of one deck based on the copper base, connects metal level and pin, helps electrical conduction.Can be provided with fin under the pin.This patent can significantly be reduced the height of this encapsulation by chip being arranged in the fluting of pedestal, makes overall dimensions slimming more.
CN1901146A has disclosed a kind of semiconductor device and manufacture method thereof as the Chinese patent publication number, it can realize microminiaturization and highly integrated FeRAM ultrathin semiconductor chip, although wherein be slim encapsulating structure, but the performance degradation of ferroelectric condenser can be inhibited, the sealing resin in the scope of percentage by weight 90%～93% that utilizes its filler content to set, this semiconductor die package is got up, thereby form encapsulating structure.The semi-conductive device of this invention comprises: semiconductor chip, comprise by arranging the memory cell that a plurality of semiconductor elements constitute, each semiconductor element comprises ferroelectric capacitor structure, and this ferroelectric capacitor structure is clipped between two electrodes by the ferroelectric film that will have ferroelectric properties and constitutes; And sealing resin, in order to covering and to seal above-mentioned semiconductor chip, this semiconductor device forms the slim encapsulating structure with 1.27mm or lower setting height(from bottom).
The mainly application in slim packaging technology of above-mentioned prior art based on encapsulating structure and encapsulating material, its complex process, cost height.In fact, the thickness of electronic product encapsulation is by the height of the thickness of chip, on line, and especially the thickness of lead frame limits, so the attenuate of leadframe thickness can make the semiconductor packages slimming.Yet thin lead frame is not suitable for explained hereafter, because in art production process, especially when the installation of chip and encapsulation, thin lead frame can produce fracture, makes chip that instability is set.Prior art can increase the material of other compression resistances usually on lead frame, but this method can not effectively obtain thin and light encapsulation, and this method complex process, the cost height.
Summary of the invention
The technology that the purpose of this invention is to provide a kind of slim encapsulation, this technical process adopt thick lead frame to be used for the installation and the encapsulation of chip in the production process for encapsulating process, have guaranteed Chip Packaging quality and safety.After encapsulation finishes lead frame is carried out thinning, the lead frame after the thinning does not influence potting process, and has effectively reduced the size and the weight of semiconductor packages.
In order to achieve the above object, technical scheme of the present invention is: a kind of technology of slim encapsulation, comprise following steps: make lead frame, described lead frame comprises pad and pin, chip is arranged on the described lead frame, chip is electrically connected with pin on the lead frame, lead frame and chip are encapsulated the exposed parts that constitutes packaging body, electroplates package bottom, cut apart packaging body; Be characterized in: the encapsulation back is carried out thinning to packaging body and is handled.
The technology of above-mentioned a kind of slim encapsulation, wherein, described thinning is treated to carries out slicing to package bottom, thereby makes the packaging body thinning.
The technology of above-mentioned a kind of slim encapsulation, wherein, described slicing is carried out package bottom by slicer.
The technology of above-mentioned a kind of slim encapsulation wherein, also comprises the steps, slicing is polished, cleaned package bottom after finishing.
The technology of above-mentioned a kind of slim encapsulation, wherein, the original thickness of described lead frame is 0.1mm.
The technology of above-mentioned a kind of slim encapsulation, wherein, the original thickness of described lead frame is 0.125mm.
The technology of above-mentioned a kind of slim encapsulation, wherein, the thickness of the lead frame bottom that slicing is removed is 0.05mm.
The technology of above-mentioned a kind of slim encapsulation, wherein, the base plane of described pad is higher than the base plane of described pin, and after slicing finished, described pad was coated in the packaging body, and described pin exposes the bottom of packaging body.
The technology of above-mentioned a kind of slim encapsulation, wherein, the base plane of described pad and the base plane of described pin at grade, after slicing finishes, the bottom that described pad and described pin all expose packaging body.
Technology as a kind of preferred slim encapsulation of the present invention can comprise following these steps successively,
Step 1: make a lead frame, described lead frame comprises pad and pin;
Step 2: shown in chip is arranged on by bonding agent on the lead frame;
Step 3: by the pin on lead-in wire connection chip and the lead frame;
Step 4: lead frame, chip and lead-in wire are encapsulated;
Step 5: the bottom of slicing packaging body is also polished, is cleaned the bottom of packaging body;
Step 6: electroplate the part of exposing package bottom;
Step 7: cut apart packaging body.
The process using technique scheme of a kind of slim encapsulation of the present invention makes it compared with prior art, has the following advantages and good effect:
1, process of the present invention is in the production process for encapsulating process, adopts thick lead frame to be used for the installation and the encapsulation of chip, and thick lead frame can not produce fracture in this technical process.After encapsulation finishes lead frame is carried out thinning, the lead frame after the thinning does not influence potting process, and has effectively reduced the size and the weight of semiconductor packages.
2, technical process of the present invention is simple to operation, and cost is low.
Description of drawings
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.Yet appended accompanying drawing only is used for explanation and sets forth, and does not constitute limitation of the scope of the invention.
Fig. 1 is the flow chart of packaging technology of the present invention.
Fig. 2 is for being arranged on chip in the embodiment of the invention 1 structural representation on the lead frame.
Fig. 3 is the structural representation that connects chip and pin in the embodiment of the invention 1 with lead-in wire.
Fig. 4 is the structural representation of packaged chip and lead frame in the embodiment of the invention 1.
Fig. 5 is to the structural representation of package bottom slicing in the embodiment of the invention 1.
Fig. 6 is the structural representation of in the embodiment of the invention 1 pin being electroplated.
Fig. 7 is for being arranged on chip in the embodiment of the invention 2 structural representation on the lead frame.
Fig. 8 is the structural representation that connects chip and pin in the embodiment of the invention 2 with lead-in wire.
Fig. 9 is the structural representation of packaged chip and lead frame in the embodiment of the invention 2.
Figure 10 is to the structural representation of package bottom slicing in the embodiment of the invention 2.
Figure 11 is the structural representation of in the embodiment of the invention 2 pin and pad being electroplated.
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the content that this specification disclosed.
Embodiment 1, a kind of technology of slim encapsulation, as shown in Figure 1, comprise following steps: at first as shown in Figure 2, lead frame 11 of structure fabrication according to encapsulation, lead frame 11 comprises pad 112 and pin 111, and the base plane of pad 112 is higher than the base plane of pin 111, and the thickness of lead frame is in the scope of 0.08mm～0.2mm.Preferably, the thickness of lead frame is 0.1mm, or the thickness of lead frame is 0.125mm, the technology intensity after the lead frame of this thickness can bear.By adhesives chip is arranged on the described lead frame 11 then.Adhesives preferably adopts the antistatic adhesives, chip is fixed on the described lead frame 11.Then, as shown in Figure 3, provide a lead-in wire 13, adopt metal wire usually.Preferably, lead-in wire 13 be a gold thread, by going between 13 with 11 pin 111 bondings on chip 12 and the lead frame, so that chip is connected with the pin of lead frame, and the connection pin, can realize being connected of chip and external circuit or electronic device.Then, as shown in Figure 4, the semi-finished product of finishing the connection of chip setting and electricity are sealed lead frame 11, chip 12, lead-in wire 13 and relevant portion by packaging body 14, be cured then, with the safety of protection lead frame, lead-in wire and chip.Then, as shown in Figure 5, the bottom of thinning packaging body 14; Preferably, thinning adopts the mode that slicing is carried out in the bottom of packaging body to carry out; More preferred, thinning is carried out slicing by slicer to the bottom of packaging body, in the time of the slicing packaging body lead frame 11 has been carried out slicing.As preferred scheme, the thickness that lead frame bottom slicing is fallen is 0.05mm, the promptly whole thickness that reduces, at this moment, lead frame after the wear down can bear the intensity of later stage technology, and after slicing finished, pad was covered by in the packaging body 14, and pin exposes outside the packaging body, and package bottom is polished, cleaned.Then, as shown in Figure 6, the pin 111 that exposes the lead frame outside the packaging body 14 is electroplated; Preferably, electroplate the pin 111 that exposes the lead frame outside the packaging body 14, with protection pin 111 with Sn.At last packaging body is separated, thereby obtain slim encapsulating structure.
In sum, the present invention adopts thick lead frame to be used for the installation and the encapsulation of chip, Chip Packaging quality and safety have been guaranteed, after encapsulation finishes lead frame is carried out thinning, the lead frame after the thinning does not influence potting process, and has effectively reduced the size and the weight of semiconductor packages, in addition, the present invention both can be applied to expose the encapsulation of pad, also can be used for not exposing the encapsulation of pad, and applying flexible is convenient.
Certainly, must recognize that above-mentioned introduction is the explanation of the relevant preferred embodiment of the present invention, only otherwise depart from the shown spirit and scope of claims subsequently, the present invention also exists many modifications.
The present invention only is confined to shown details of above-mentioned explanation or accompanying drawing and method anything but.The present invention can have other embodiment, and can adopt multiple mode to be implemented.In addition, everybody must recognize that also employed wording and term and digest be the purpose in order to realize introducing just, only is confined to this anything but here.
Just because of this, one skilled in the art will appreciate that the present invention based on viewpoint can be used as at any time and implement several targets of the present invention and design other structure, method and system.So, it is essential that appended claim will be regarded as the construction that comprised that all these are of equal value, as long as they are without departing from the spirit and scope of the present invention.
Claims (9)
1. the technology of a slim encapsulation, comprise following steps: make lead frame, described lead frame comprises pad and pin, chip is arranged on the described lead frame, chip is electrically connected with pin on the lead frame, lead frame and chip are encapsulated the exposed parts that constitutes packaging body, electroplates package bottom, cut apart packaging body; It is characterized in that: the encapsulation back is carried out thinning to packaging body and is handled.
2. the technology of a kind of slim encapsulation according to claim 1, it is characterized in that: described thinning is treated to carries out slicing to package bottom, thereby makes the packaging body thinning.
3. the technology of a kind of slim encapsulation according to claim 2, it is characterized in that: described slicing is carried out package bottom by slicer.
4. the technology of a kind of slim encapsulation according to claim 3 is characterized in that: comprise the steps that also slicing is polished, cleaned package bottom after finishing.
5. the technology of a kind of slim encapsulation according to claim 4, it is characterized in that: the original thickness of described lead frame is 0.1mm.
6. the technology of a kind of slim encapsulation according to claim 4, it is characterized in that: the original thickness of described lead frame is 0.125mm.
7. according to the technology of claim 5 or 6 described a kind of slim encapsulation, it is characterized in that: the thickness of the lead frame bottom that slicing is removed is 0.05mm.
8. the technology of a kind of slim encapsulation according to claim 7, it is characterized in that: the base plane of described pad is higher than the base plane of described pin, and after slicing finished, described pad was coated in the packaging body, and described pin exposes the bottom of packaging body.
9. the technology of a kind of slim encapsulation according to claim 7 is characterized in that: the base plane of described pad and the base plane of described pin at grade, after slicing finishes, the bottom that described pad and described pin all expose packaging body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101487098A CN102194708A (en) | 2010-03-19 | 2010-03-19 | Thin encapsulation process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101487098A CN102194708A (en) | 2010-03-19 | 2010-03-19 | Thin encapsulation process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102194708A true CN102194708A (en) | 2011-09-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101487098A Pending CN102194708A (en) | 2010-03-19 | 2010-03-19 | Thin encapsulation process |
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| Country | Link |
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| CN (1) | CN102194708A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103887225A (en) * | 2012-12-21 | 2014-06-25 | 万国半导体股份有限公司 | Semiconductor device based on aluminum alloy lead wire frame, and preparation method |
| CN103972181A (en) * | 2013-02-01 | 2014-08-06 | 意法半导体制造(深圳)有限公司 | Packaging device and packaging method of silicon chip comprising surface coating glass layer inside |
| CN104505346A (en) * | 2014-11-03 | 2015-04-08 | 南通富士通微电子股份有限公司 | Semiconductor packaging technology |
| CN104821306A (en) * | 2015-04-28 | 2015-08-05 | 上海凯虹科技电子有限公司 | Ultra small-scale encapsulation method and encapsulation body |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010041424A1 (en) * | 1999-12-27 | 2001-11-15 | Takao Matsuura | Semiconductor device and a method of manufacturing the same |
| CN1571150A (en) * | 2004-05-01 | 2005-01-26 | 江苏长电科技股份有限公司 | Mini flipchip transistor and method for manufacturing same |
| CN1755908A (en) * | 2004-09-29 | 2006-04-05 | 上海贝岭股份有限公司 | Method for improving qualification rate of plastic encapsulated integrated circuit |
-
2010
- 2010-03-19 CN CN2010101487098A patent/CN102194708A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010041424A1 (en) * | 1999-12-27 | 2001-11-15 | Takao Matsuura | Semiconductor device and a method of manufacturing the same |
| CN1571150A (en) * | 2004-05-01 | 2005-01-26 | 江苏长电科技股份有限公司 | Mini flipchip transistor and method for manufacturing same |
| CN1755908A (en) * | 2004-09-29 | 2006-04-05 | 上海贝岭股份有限公司 | Method for improving qualification rate of plastic encapsulated integrated circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103887225A (en) * | 2012-12-21 | 2014-06-25 | 万国半导体股份有限公司 | Semiconductor device based on aluminum alloy lead wire frame, and preparation method |
| CN103887225B (en) * | 2012-12-21 | 2017-02-22 | 万国半导体股份有限公司 | Semiconductor device based on aluminum alloy lead wire frame, and preparation method |
| CN103972181A (en) * | 2013-02-01 | 2014-08-06 | 意法半导体制造(深圳)有限公司 | Packaging device and packaging method of silicon chip comprising surface coating glass layer inside |
| CN104505346A (en) * | 2014-11-03 | 2015-04-08 | 南通富士通微电子股份有限公司 | Semiconductor packaging technology |
| CN104821306A (en) * | 2015-04-28 | 2015-08-05 | 上海凯虹科技电子有限公司 | Ultra small-scale encapsulation method and encapsulation body |
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Application publication date: 20110921 |