CN100459123C - Stack type chip packaging structure, chip packaging body and manufacturing method - Google Patents
Stack type chip packaging structure, chip packaging body and manufacturing method Download PDFInfo
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- CN100459123C CN100459123C CNB2005101025045A CN200510102504A CN100459123C CN 100459123 C CN100459123 C CN 100459123C CN B2005101025045 A CNB2005101025045 A CN B2005101025045A CN 200510102504 A CN200510102504 A CN 200510102504A CN 100459123 C CN100459123 C CN 100459123C
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- 238000004806 packaging method and process Methods 0.000 title claims description 62
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims description 22
- 230000004308 accommodation Effects 0.000 claims description 17
- 238000005452 bending Methods 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 238000007789 sealing Methods 0.000 abstract 2
- 229910000679 solder Inorganic materials 0.000 description 13
- 239000000084 colloidal system Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 238000012856 packing Methods 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 238000005304 joining Methods 0.000 description 3
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
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- 238000003466 welding Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
This invention relates to chip sealing part, which comprises one flexible circuit board, one first and second chip, wherein, the flexible circuit board is bent to form one containing space; first and second chips are set on flexible circuit; the first and second chips are contained in one space with first one upon second one; this invention chip thickness can change. This invention provides one overlap chip sealing structure and its process method.
Description
Technical field
The invention relates to a kind of encapsulating structure, and particularly relevant for a kind of stack chip packaging structure with high encapsulation integration.
Background technology
In information society now, the user pursues electronic product high-speed, high-quality, multiplex's energy property.With regard to product appearance, the design of electronic product also strides forward towards light, thin, short, little trend.In order to achieve the above object, many companies all incorporate systematized notion when carrying out circuit design, make single chips to possess to have multiple function, are configured in chip in the electronic product (chip is wafer, below all be called chip) number with saving.In addition, with regard to the Electronic Packaging technology, in order to cooperate light, thin, short, little designer trends, also develop and multi-chip modules (multi-chipmodule, MCM) package design notion, chip size structure dress (chip scale package, the notion of package design notion CSP) and stacked multicore sheet package design etc.Below just describe at several known stack chip packaging structures respectively.
Fig. 1 is the cutaway view that has known stack chip packaging structure now.See also shown in Figure 1ly, existing known stack chip packaging structure 100 comprises a base plate for packaging (package substrate) 110, chip 120a, 120b, a sept (spacer) 130, many leads 140 and a packing colloid (encapsulant) 150.Wherein, chip 120a and 120b are disposed on the base plate for packaging 110, and sept 130 is disposed between chip 120a and the 120b.Part lead 140 is electrically connected at respectively between chip 120a and the base plate for packaging 110, and other part leads 140 then are electrically connected at respectively between chip 120b and the base plate for packaging 110.In addition, packing colloid 150 is disposed on the base plate for packaging 110, and coats these leads 140, chip 120a, 120b and sept 130.
Because must be between chip 120a and the 120b at a distance of certain distance, so that carry out routing processing procedure (wire bonding process), therefore the integral thickness of known stack chip packaging structure 100 can can't further reduce because of the thickness of sept 130.In addition, known stack chip packaging structure 100 also can produce the problem of heat radiation aspect.Therefore, in order to address the above problem, the known development another kind of stack chip packaging structure.
Seeing also shown in Figure 2ly, is cutaway view of another existing known stack chip packaging structure.Existing known stack chip packaging structure 10 comprises a base plate for packaging 12 and a plurality of chip packing-body 200a, 200b, and wherein these chip packing-bodies 200a, 200b are stacked on the base plate for packaging 12, and electrically connects with base plate for packaging 12.Each chip packing-body 200a, 200b comprise a base plate for packaging 210, a chip 220, a plurality of projection 230, a primer 240 and a plurality of soldered balls 250.Chip 220 is disposed on the base plate for packaging 210 with these projections 230, and these projections 230 are disposed between chip 220 and the base plate for packaging 210, and chip 220 is electrically connected to base plate for packaging 210 via these projections.Primer 240 is disposed between chip 220 and the base plate for packaging 210, to coat these projections 230.
Base plate for packaging 210 has a plurality of conductive poles 212 and a plurality of solder ball pads 214, and wherein these conductive poles 212 run through base plate for packaging 210 respectively, and these solder ball pads 214 are disposed at respectively on these conductive poles 212.In addition, these soldered balls 250 are disposed on these solder ball pads 214.It should be noted that chip packing-body 200a and 200b are electrically connected to each other via soldered ball 250, and chip packing-body 200b is electrically connected to base plate for packaging 12 via soldered ball 250.
Compared to known stack chip packaging structure 100, though known stack chip packaging structure 10 process complexity of this kind are lower, the thickness of the stack chip packaging structure 10 that this kind is known is the thickness greater than known stack chip packaging structure 100.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of chip packing-body, the thinner thickness that it is whole exactly.
In addition, a further object of the present invention just provides a kind of stack chip packaging structure, and it has higher encapsulation integration.
In addition, another purpose of the present invention just provides a kind of manufacture method of chip packing-body, to improve the encapsulation integration.
Based on above-mentioned purpose or other purposes, the present invention proposes a kind of chip packing-body, it comprises a flexible circuit board, one first chip and one second chip, wherein flexible circuit board is that bending is to form an accommodation space, flexible circuit board comprises that a flexible substrate and is disposed at the patterned line layer on the flexible substrate, wherein flexible base plate has a plurality of perforations, expose partially patterned line layer, first chip and second chip are disposed on the flexible circuit board respectively, and electrically connect with flexible circuit board respectively.In addition, first chip and second chip are positioned at accommodation space, and first chip is positioned at second chip top, and first chip and second chip are disposed at respectively on this patterned line layer, and electrically connect with patterned line layer; A plurality of external connection terminals be disposed at respectively in those perforations of part, and each those external connection terminals are electrically connected to first chip and/or second chip via this patterned line layer.
According to the embodiment of the invention, chip packing-body more can comprise an adhesion coating, and it is disposed between first chip and second chip, to fix the relative position between first chip and second chip.
According to the embodiment of the invention, chip packing-body more can comprise a plurality of first projections and a plurality of second projection, wherein these first projections are disposed between first chip and the flexible circuit board, and first chip is electrically connected to flexible circuit board via these first projections.In addition, second projection is disposed between second chip and the flexible circuit board, and second chip is electrically connected to flexible circuit board via these second projections.
According to the embodiment of the invention, chip packing-body more can comprise many first leads and many second leads, and wherein first chip is electrically connected to flexible circuit board via these first leads.In addition, second chip is electrically connected to flexible circuit board via these second leads.
Based on above-mentioned purpose or other purposes, the present invention proposes a kind of stack chip packaging structure, and it comprises that a plurality of chip packing-bodies are electrically connected to each other.Each chip packing-body comprises a flexible circuit board, one first chip, one second chip and a plurality of external connection terminals, and wherein the flexible circuit board bending is to form an accommodation space.In addition, flexible circuit board comprises a flexible substrate and a patterned line layer that is disposed on the flexible substrate, and wherein flexible substrate has a plurality of perforations, and it exposes partially patterned line layer.First chip and second chip are disposed on the patterned line layer respectively, and electrically connect with patterned line layer respectively.In addition, first chip and second chip are positioned at accommodation space, and first chip is positioned at second chip top.These external connection terminals are disposed at respectively in these perforations, and each external connection terminals is electrically connected to first chip and/or second chip via patterned line layer, and each chip packing-body is electrically connected to another chip packing-body via the external connection terminals of correspondence.
According to the embodiment of the invention, stack chip packaging structure more can comprise a common carrier, and these chip packing-bodies are stacked on the common carrier, and electrically connects with common carrier.In addition, common carrier can be circuit board or lead frame.
Based on above-mentioned purpose or other purposes, the present invention proposes a kind of manufacture method of chip packing-body, and it comprises the following steps.At first, one first chip, one second chip and a flexible circuit board are provided, wherein flexible circuit board comprises a flexible substrate and a patterned line layer that is disposed on the flexible substrate, and has formed a plurality of perforations in flexible substrate, and it exposes partially patterned line layer.Then, with first chip and second chip configuration on flexible circuit board, so that first chip and second chip are electrically connected to patterned line layer respectively.Then, with the flexible circuit board bending, to form an accommodation space, wherein first chip and second chip are positioned at accommodation space, and first chip is positioned at second chip top.
Based on above-mentioned, the formed stack chip packaging structure of the present invention or the thickness of chip packing-body have higher encapsulation integration.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the cutaway view of known stack chip packaging structure.
Fig. 2 is the cutaway view of another known stack chip packaging structure.
Fig. 3 A to Fig. 3 C is the manufacturing process cutaway view according to the stack chip packaging structure of first embodiment of the invention.
Fig. 4 A to Fig. 4 B is the manufacturing process cutaway view according to the stack chip packaging structure of second embodiment of the invention.
10,100: known stack chip packaging structure
12,110,210: base plate for packaging
20,30: stack chip packaging structure
22a, 214: solder ball pad
24,250,360: soldered ball
120a, 120b, 220,320a, 320b, 410a, 410b: chip
130: sept
140,420a, 420b: lead
150,430a, 430b: packing colloid
200a, 200b, 300a, 300b, 300c: chip packing-body
400a, 400b, 400c: Chip Packaging
212: conductive pole
230,330a, 330b: projection
240,340a, 340b: primer
310: flexible circuit board
310a: accommodation space
312: flexible substrate
312a: perforation
314: patterned line layer
350,440: adhesion coating
450: external connection terminals
Embodiment
[first embodiment]
Fig. 3 A to Fig. 3 C is the manufacturing process cutaway view according to the stack chip packaging structure of first embodiment of the invention.See also shown in Fig. 3 A, the manufacture method of the stack chip packaging structure of present embodiment comprises the following steps.At first, provide a flexible circuit board 310, and flexible circuit board 310 comprises a flexible substrate 312 and a patterned line layer 314 that is disposed on the flexible substrate 312.In the present embodiment, the material of flexible substrate 312 can be polyimides (polyimide) or other pliability plastic materials.
Then, in flexible substrate 312, form a plurality of perforation 312a, and these perforations 312a exposes partially patterned line layer 314.In addition, the method that forms these perforations 312a can be an etch process or other can form the processing procedure of perforation.Then, provide chip 320a and 320b, and chip 320a and 320b are disposed on the flexible circuit board 310, so that chip 320a and 320b are electrically connected to patterned line layer 314 respectively.Wherein, chip 320a and 320b can be electrically connected to patterned line layer 314 with the chip bonding technology respectively.
With regard to present embodiment, projection 330a is formed on the patterned line layer 314 or on chip 320a, and then electrically connects so that chip 320a can be electrically connected to patterned line layer 314 by projection 330a through reflow (reflow).Similarly, projection 330b is formed on the patterned line layer 314 or on chip 320b, and then electrically connects so that chip 320b can be electrically connected to patterned line layer 314 by projection 330b through reflow.Then, present embodiment also can form a primer 340a between chip 320a and flexible circuit board 310, to coat these projections 330a.Similarly, present embodiment also can form a primer 340b between chip 320b and flexible circuit board 310, to coat these projections 330b.
See also shown in Fig. 3 B, to form an accommodation space 310a, at this moment, chip 320a and 320b are positioned at accommodation space 310a with flexible circuit board 310 bendings, and chip 320a is positioned at chip 320b top.In addition, before this flexible circuit board 310 of bending, also an adhesion coating 350 can be formed on chip 320a or 320b, with the relative position between fixed chip 320a and the 320b.
Then, form a plurality of soldered balls 360 in part perforation 312a, with the usefulness as external connection terminals, and each soldered ball 360 is electrically connected to chip 320a and/or chip 320b via patterned line layer 314 respectively.In addition, these soldered balls 360 can be lead-free solder ball or tin lead welding ball.Yet, also can be that scolder or other conductive material of lead-free solder, tin-lead solder, other types are inserted in the part perforation 312a, to form external connection terminals (shown in Fig. 4 A).So far, roughly finish the making of chip packing-body 300a.
See also shown in Fig. 3 C, repeat above-mentioned step, to produce chip packing-body 300b and 300c.Then, provide a shared carrier 22, and shared carrier 22 have a plurality of solder ball pad 22a.In the present embodiment, shared carrier 22 carrier that can be circuit board or other type.Then, chip packing-body 300a, 300b and 300c are stacked on the shared carrier 22.Then, carry out back welding process (reflow process),, and make chip packing-body 300c be connected with shared carrier 22 so that these chip packing-bodies 300a, 300b and 300c are electrical each other for said structure.It should be noted that under the situation of not using shared carrier 22 chip packing-body 300a, 300b and 300c also can become one earlier and directly be disposed on the circuit board or on the electronic installation.
In the present embodiment, the chip 320a of each chip packing- body 300a, 300b and 300c and 320b adopt the chip bonding technology to be electrically connected to flexible circuit board 310.Yet chip 320a among each chip packing-body 300a, 300b and the 300c and 320b also can adopt routing joining technique or other chip encapsulation technologies and be electrically connected to flexible circuit board 310.
Then, on the solder ball pad 22a of shared carrier 22, form a plurality of soldered balls 24, to finish the making of stack chip packaging structure 20.This stack chip packaging structure 20 just can be disposed on the circuit board by soldered ball 24.What deserves to be mentioned is that present embodiment does not limit the quantity of the chip packing-body in the stack chip packaging structure 20.
Because the thickness of each chip packing-body 300a, 300b and 300c can attenuation, so the integral thickness of stack chip packaging structure 20 is also along with attenuation.In addition, the stack chip packaging structure 20 employed process technique of present embodiment are comparatively ripe.In addition, because each chip packing-body 300a, 300b and 300c make separately to form, so the chip packing-body of defective products can not use to stack chip packaging structure 20, with the yield of raising stack chip packaging structure 20.
[second embodiment]
Fig. 4 A to Fig. 4 B illustrates the manufacturing process cutaway view according to the stack chip packaging structure of second embodiment of the invention.Please refer to Fig. 4 A, present embodiment is similar to the aforementioned embodiment, and the two main difference part is: chip 410a and 420b are disposed at respectively on the flexible circuit board 310, form many lead 420a and 420b then.Chip 410a is electrically connected to patterned line layer 314 by lead 420a, and chip 410b is electrically connected to patterned line layer 314 by lead 420b.Then, on flexible circuit board 310, form packing colloid 430a and 430b respectively, wherein packing colloid 430a coating chip 410a and lead 420a.In addition, packing colloid 430b coating chip 410b and lead 420a.
Then, bending flexible circuit board 310, to form an accommodation space 310a, its chips 410a and 410b are positioned at accommodation space 310a, and chip 410a is positioned at chip 410b top.In addition, before this flexible circuit board 310 of bending, also an adhesion coating 440 can be formed on packing colloid 430a or 430b, with the relative position between fixed chip 410a and the 410b.So far, tentatively finish the making of chip packing-body 400a.
Then, scolder or other electric conducting materials of lead-free solder, tin-lead solder, other types are inserted in these perforations of part 312a, to form a plurality of external connection terminals 450.Yet the soldered ball 360 in the foregoing description also can replace the external connection terminals 450 of present embodiment.
See also shown in Fig. 4 B, repeat above-mentioned steps, to form chip packing-body 400b and 400c.Then, these chip packing- bodies 400a, 400b and 400c are stacked on the common carrier 22, and these chip packing- bodies 400a, 400b and 400c are electrically connected to each other by external connection terminals 440.In addition, chip packing-body 400c is electrically connected to common carrier 22 by external connection terminals 440.Similarly, this stack chip packaging structure 30 also can be disposed on the circuit board (not illustrating) by scolder (solder) or pre-welding material (pre-solder).In addition, as the foregoing description, under the situation of not using shared carrier 22, chip packing- body 400a, 400b and 400c also can become one earlier and directly be disposed on the circuit board or on the electronic installation.
What deserves to be mentioned is that the chip 410a of each chip packing- body 400a, 400b and 400c and 410b all adopt the routing joining technique to be electrically connected to flexible circuit board 310.Yet each chip of the various embodiments described above also can be electrically connected to flexible circuit board 310 with chip bonding technology, routing joining technique or other chip encapsulation technologies respectively.In addition, present embodiment does not limit the quantity of the chip packing-body in the stack chip packaging structure 30.
In sum, the present invention has following advantage at least:
1, the stack chip packaging structure of the present invention or the thinner thickness of chip packing-body.
2, the stack chip packaging structure of the present invention or Chip Packaging physical efficiency is applied to chip bonding processing procedure or line connection process.
3, process technique used in the present invention is comparatively ripe, and therefore manufacture method of the present invention has preferable process rate.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (8)
1, a kind of chip packing-body is characterized in that it comprises:
One flexible circuit board, be that bending is to form an accommodation space, this flexible circuit board comprises that a flexible substrate and is disposed at the patterned line layer on this flexible substrate, and wherein this flexible base plate has a plurality of perforations, exposes this patterned line layer of part;
One first chip is disposed on this flexible circuit board, and electrically connects with this flexible circuit board; And
One second chip, be disposed on this flexible circuit board, and electrically connect with this flexible circuit board, wherein this first chip and this second chip are positioned at this accommodation space, and this first chip is positioned at this second chip top, this first chip and this second chip are disposed at respectively on this patterned line layer, and electrically connect with this patterned line layer;
A plurality of external connection terminals be disposed at respectively in those perforations of part, and each those external connection terminals are electrically connected to this first chip and/or this second chip via this patterned line layer.
2, chip packing-body according to claim 1 is characterized in that it more comprises an adhesion coating, is disposed between this first chip and this second chip, to fix the relative position between this first chip and this second chip.
3, chip packing-body according to claim 1, it is characterized in that it more comprises a plurality of first projections and a plurality of second projection, wherein those first projections are disposed between this first chip and this flexible circuit board, and this first chip is electrically connected to this flexible circuit board via those first projections, and those second projections are disposed between this second chip and this flexible circuit board, and this second chip is electrically connected to this flexible circuit board via those second projections.
4, chip packing-body according to claim 1, it is characterized in that it more comprises many first leads and many second leads, wherein this first chip is electrically connected to this flexible circuit board via those first leads, and this second chip is electrically connected to this flexible circuit board via those second leads.
5, a kind of stack chip packaging structure is characterized in that it comprises:
A plurality of chip packing-bodies are electrically connected to each other, and each those chip packing-body comprises:
One flexible circuit board, be that bending is to form an accommodation space, and this flexible circuit board comprises a flexible substrate and a patterned line layer that is disposed on this flexible substrate, and wherein this flexible substrate has most perforations, exposes this patterned line layer of part;
One first chip is disposed on this patterned line layer, and electrically connects with this patterned line layer; And
One second chip is disposed on this patterned line layer, and electrically connects with this patterned line layer, and wherein this first chip and this second chip are positioned at this accommodation space, and this first chip is positioned at this second chip top; And
A plurality of external connection terminals, be disposed at respectively in those perforations of part, and each those external connection terminals is electrically connected to this first chip and/or this second chip via this patterned line layer, and each those chip packing-body is electrically connected to another those chip packing-bodies via those external connection terminals of correspondence.
6, stack chip packaging structure according to claim 5 it is characterized in that it more comprises a common carrier, and those chip packing-bodies is stacked on this common carrier, and electrically connects with this common carrier.
7, stack chip packaging structure according to claim 6 is characterized in that wherein said common carrier comprises circuit board or lead frame.
8, a kind of manufacture method of chip packing-body is characterized in that it may further comprise the steps:
One first chip, one second chip and a flexible circuit board are provided, wherein this flexible circuit board comprises a flexible substrate and a patterned line layer that is disposed on this flexible substrate, and in this flexible substrate, be formed with a plurality of perforations, to expose this patterned line layer of part;
With this first chip and this second chip configuration on this flexible circuit board, so that this first chip and this second chip are electrically connected to this patterned line layer respectively; And
With this flexible circuit board bending, to form an accommodation space, wherein this first chip and this second chip are positioned at this accommodation space, and this first chip is positioned at this second chip top.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101025045A CN100459123C (en) | 2005-09-08 | 2005-09-08 | Stack type chip packaging structure, chip packaging body and manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101025045A CN100459123C (en) | 2005-09-08 | 2005-09-08 | Stack type chip packaging structure, chip packaging body and manufacturing method |
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| CN1929129A CN1929129A (en) | 2007-03-14 |
| CN100459123C true CN100459123C (en) | 2009-02-04 |
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| CNB2005101025045A Active CN100459123C (en) | 2005-09-08 | 2005-09-08 | Stack type chip packaging structure, chip packaging body and manufacturing method |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI550785B (en) * | 2014-05-15 | 2016-09-21 | 南茂科技股份有限公司 | Chip package structure |
| DE102016213697A1 (en) * | 2016-07-26 | 2018-02-01 | Zf Friedrichshafen Ag | Printed circuit board assembly |
| CN106299098B (en) * | 2016-10-12 | 2018-10-26 | 成都寰宇科芯科技有限责任公司 | The manufacturing method of the outer electrode of COMMB-LED light sources |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040124527A1 (en) * | 2002-12-31 | 2004-07-01 | Chia-Pin Chiu | Folded BGA package design with shortened communication paths and more electrical routing flexibility |
| US20040212063A1 (en) * | 2003-04-28 | 2004-10-28 | Jaeck Edward W. | Electronic package having a flexible substrate with ends connected to one another |
| US20050062141A1 (en) * | 2003-09-22 | 2005-03-24 | Salta Jose R. | Electronic package having a folded flexible substrate and method of manufacturing the same |
-
2005
- 2005-09-08 CN CNB2005101025045A patent/CN100459123C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040124527A1 (en) * | 2002-12-31 | 2004-07-01 | Chia-Pin Chiu | Folded BGA package design with shortened communication paths and more electrical routing flexibility |
| US20040212063A1 (en) * | 2003-04-28 | 2004-10-28 | Jaeck Edward W. | Electronic package having a flexible substrate with ends connected to one another |
| US20050062141A1 (en) * | 2003-09-22 | 2005-03-24 | Salta Jose R. | Electronic package having a folded flexible substrate and method of manufacturing the same |
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| CN1929129A (en) | 2007-03-14 |
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